drivers/pinctrl/qcom/pinctrl-spmi-gpio.c

   1 /*
   2  * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/gpio.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/pinctrl/pinconf-generic.h>
  18 #include <linux/pinctrl/pinconf.h>
  19 #include <linux/pinctrl/pinmux.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regmap.h>
  22 #include <linux/slab.h>
  23 #include <linux/types.h>
  24
  25 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
  26
  27 #include "../core.h"
  28 #include "../pinctrl-utils.h"
  29
  30 #define PMIC_GPIO_ADDRESS_RANGE                 0x100
  31
  32 /* type and subtype registers base address offsets */
  33 #define PMIC_GPIO_REG_TYPE                      0x4
  34 #define PMIC_GPIO_REG_SUBTYPE                   0x5
  35
  36 /* GPIO peripheral type and subtype out_values */
  37 #define PMIC_GPIO_TYPE                          0x10
  38 #define PMIC_GPIO_SUBTYPE_GPIO_4CH              0x1
  39 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH             0x5
  40 #define PMIC_GPIO_SUBTYPE_GPIO_8CH              0x9
  41 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH             0xd
  42
  43 #define PMIC_MPP_REG_RT_STS                     0x10
  44 #define PMIC_MPP_REG_RT_STS_VAL_MASK            0x1
  45
  46 /* control register base address offsets */
  47 #define PMIC_GPIO_REG_MODE_CTL                  0x40
  48 #define PMIC_GPIO_REG_DIG_VIN_CTL               0x41
  49 #define PMIC_GPIO_REG_DIG_PULL_CTL              0x42
  50 #define PMIC_GPIO_REG_DIG_OUT_CTL               0x45
  51 #define PMIC_GPIO_REG_EN_CTL                    0x46
  52
  53 /* PMIC_GPIO_REG_MODE_CTL */
  54 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT          0x1
  55 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT       1
  56 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK        0x7
  57 #define PMIC_GPIO_REG_MODE_DIR_SHIFT            4
  58 #define PMIC_GPIO_REG_MODE_DIR_MASK             0x7
  59
  60 /* PMIC_GPIO_REG_DIG_VIN_CTL */
  61 #define PMIC_GPIO_REG_VIN_SHIFT                 0
  62 #define PMIC_GPIO_REG_VIN_MASK                  0x7
  63
  64 /* PMIC_GPIO_REG_DIG_PULL_CTL */
  65 #define PMIC_GPIO_REG_PULL_SHIFT                0
  66 #define PMIC_GPIO_REG_PULL_MASK                 0x7
  67
  68 #define PMIC_GPIO_PULL_DOWN                     4
  69 #define PMIC_GPIO_PULL_DISABLE                  5
  70
  71 /* PMIC_GPIO_REG_DIG_OUT_CTL */
  72 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT        0
  73 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK         0x3
  74 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT            4
  75 #define PMIC_GPIO_REG_OUT_TYPE_MASK             0x3
  76
  77 /*
  78  * Output type - indicates pin should be configured as push-pull,
  79  * open drain or open source.
  80  */
  81 #define PMIC_GPIO_OUT_BUF_CMOS                  0
  82 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS       1
  83 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS       2
  84
  85 /* PMIC_GPIO_REG_EN_CTL */
  86 #define PMIC_GPIO_REG_MASTER_EN_SHIFT           7
  87
  88 #define PMIC_GPIO_PHYSICAL_OFFSET               1
  89
  90 /* Qualcomm specific pin configurations */
  91 #define PMIC_GPIO_CONF_PULL_UP                  (PIN_CONFIG_END + 1)
  92 #define PMIC_GPIO_CONF_STRENGTH                 (PIN_CONFIG_END + 2)
  93
  94 /**
  95  * struct pmic_gpio_pad - keep current GPIO settings
  96  * @base: Address base in SPMI device.
  97  * @irq: IRQ number which this GPIO generate.
  98  * @is_enabled: Set to false when GPIO should be put in high Z state.
  99  * @out_value: Cached pin output value
 100  * @have_buffer: Set to true if GPIO output could be configured in push-pull,
 101  *      open-drain or open-source mode.
 102  * @output_enabled: Set to true if GPIO output logic is enabled.
 103  * @input_enabled: Set to true if GPIO input buffer logic is enabled.
 104  * @num_sources: Number of power-sources supported by this GPIO.
 105  * @power_source: Current power-source used.
 106  * @buffer_type: Push-pull, open-drain or open-source.
 107  * @pullup: Constant current which flow trough GPIO output buffer.
 108  * @strength: No, Low, Medium, High
 109  * @function: See pmic_gpio_functions[]
 110  */
 111 struct pmic_gpio_pad {
 112         u16             base;
 113         int             irq;
 114         bool            is_enabled;
 115         bool            out_value;
 116         bool            have_buffer;
 117         bool            output_enabled;
 118         bool            input_enabled;
 119         unsigned int    num_sources;
 120         unsigned int    power_source;
 121         unsigned int    buffer_type;
 122         unsigned int    pullup;
 123         unsigned int    strength;
 124         unsigned int    function;
 125 };
 126
 127 struct pmic_gpio_state {
 128         struct device   *dev;
 129         struct regmap   *map;
 130         struct pinctrl_dev *ctrl;
 131         struct gpio_chip chip;
 132 };
 133
 134 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
 135         {"qcom,pull-up-strength",       PMIC_GPIO_CONF_PULL_UP,         0},
 136         {"qcom,drive-strength",         PMIC_GPIO_CONF_STRENGTH,        0},
 137 };
 138
 139 #ifdef CONFIG_DEBUG_FS
 140 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
 141         PCONFDUMP(PMIC_GPIO_CONF_PULL_UP,  "pull up strength", NULL, true),
 142         PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
 143 };
 144 #endif
 145
 146 static const char *const pmic_gpio_groups[] = {
 147         "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
 148         "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
 149         "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
 150         "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
 151         "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
 152 };
 153
 154 static const char *const pmic_gpio_functions[] = {
 155         PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
 156         PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
 157         PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
 158         PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
 159 };
 160
 161 static inline struct pmic_gpio_state *to_gpio_state(struct gpio_chip *chip)
 162 {
 163         return container_of(chip, struct pmic_gpio_state, chip);
 164 };
 165
 166 static int pmic_gpio_read(struct pmic_gpio_state *state,
 167                           struct pmic_gpio_pad *pad, unsigned int addr)
 168 {
 169         unsigned int val;
 170         int ret;
 171
 172         ret = regmap_read(state->map, pad->base + addr, &val);
 173         if (ret < 0)
 174                 dev_err(state->dev, "read 0x%x failed\n", addr);
 175         else
 176                 ret = val;
 177
 178         return ret;
 179 }
 180
 181 static int pmic_gpio_write(struct pmic_gpio_state *state,
 182                            struct pmic_gpio_pad *pad, unsigned int addr,
 183                            unsigned int val)
 184 {
 185         int ret;
 186
 187         ret = regmap_write(state->map, pad->base + addr, val);
 188         if (ret < 0)
 189                 dev_err(state->dev, "write 0x%x failed\n", addr);
 190
 191         return ret;
 192 }
 193
 194 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
 195 {
 196         /* Every PIN is a group */
 197         return pctldev->desc->npins;
 198 }
 199
 200 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
 201                                             unsigned pin)
 202 {
 203         return pctldev->desc->pins[pin].name;
 204 }
 205
 206 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
 207                                     const unsigned **pins, unsigned *num_pins)
 208 {
 209         *pins = &pctldev->desc->pins[pin].number;
 210         *num_pins = 1;
 211         return 0;
 212 }
 213
 214 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
 215         .get_groups_count       = pmic_gpio_get_groups_count,
 216         .get_group_name         = pmic_gpio_get_group_name,
 217         .get_group_pins         = pmic_gpio_get_group_pins,
 218         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 219         .dt_free_map            = pinctrl_utils_dt_free_map,
 220 };
 221
 222 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
 223 {
 224         return ARRAY_SIZE(pmic_gpio_functions);
 225 }
 226
 227 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
 228                                                unsigned function)
 229 {
 230         return pmic_gpio_functions[function];
 231 }
 232
 233 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
 234                                          unsigned function,
 235                                          const char *const **groups,
 236                                          unsigned *const num_qgroups)
 237 {
 238         *groups = pmic_gpio_groups;
 239         *num_qgroups = pctldev->desc->npins;
 240         return 0;
 241 }
 242
 243 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
 244                                 unsigned pin)
 245 {
 246         struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
 247         struct pmic_gpio_pad *pad;
 248         unsigned int val;
 249         int ret;
 250
 251         pad = pctldev->desc->pins[pin].drv_data;
 252
 253         pad->function = function;
 254
 255         val = 0;
 256         if (pad->output_enabled) {
 257                 if (pad->input_enabled)
 258                         val = 2;
 259                 else
 260                         val = 1;
 261         }
 262
 263         val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
 264         val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
 265         val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
 266
 267         ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
 268         if (ret < 0)
 269                 return ret;
 270
 271         val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
 272
 273         return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
 274 }
 275
 276 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
 277         .get_functions_count    = pmic_gpio_get_functions_count,
 278         .get_function_name      = pmic_gpio_get_function_name,
 279         .get_function_groups    = pmic_gpio_get_function_groups,
 280         .set_mux                = pmic_gpio_set_mux,
 281 };
 282
 283 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
 284                                 unsigned int pin, unsigned long *config)
 285 {
 286         unsigned param = pinconf_to_config_param(*config);
 287         struct pmic_gpio_pad *pad;
 288         unsigned arg;
 289
 290         pad = pctldev->desc->pins[pin].drv_data;
 291
 292         switch (param) {
 293         case PIN_CONFIG_DRIVE_PUSH_PULL:
 294                 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_CMOS;
 295                 break;
 296         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 297                 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
 298                 break;
 299         case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 300                 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
 301                 break;
 302         case PIN_CONFIG_BIAS_PULL_DOWN:
 303                 arg = pad->pullup == PMIC_GPIO_PULL_DOWN;
 304                 break;
 305         case PIN_CONFIG_BIAS_DISABLE:
 306                 arg = pad->pullup = PMIC_GPIO_PULL_DISABLE;
 307                 break;
 308         case PIN_CONFIG_BIAS_PULL_UP:
 309                 arg = pad->pullup == PMIC_GPIO_PULL_UP_30;
 310                 break;
 311         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 312                 arg = !pad->is_enabled;
 313                 break;
 314         case PIN_CONFIG_POWER_SOURCE:
 315                 arg = pad->power_source;
 316                 break;
 317         case PIN_CONFIG_INPUT_ENABLE:
 318                 arg = pad->input_enabled;
 319                 break;
 320         case PIN_CONFIG_OUTPUT:
 321                 arg = pad->out_value;
 322                 break;
 323         case PMIC_GPIO_CONF_PULL_UP:
 324                 arg = pad->pullup;
 325                 break;
 326         case PMIC_GPIO_CONF_STRENGTH:
 327                 arg = pad->strength;
 328                 break;
 329         default:
 330                 return -EINVAL;
 331         }
 332
 333         *config = pinconf_to_config_packed(param, arg);
 334         return 0;
 335 }
 336
 337 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 338                                 unsigned long *configs, unsigned nconfs)
 339 {
 340         struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
 341         struct pmic_gpio_pad *pad;
 342         unsigned param, arg;
 343         unsigned int val;
 344         int i, ret;
 345
 346         pad = pctldev->desc->pins[pin].drv_data;
 347
 348         for (i = 0; i < nconfs; i++) {
 349                 param = pinconf_to_config_param(configs[i]);
 350                 arg = pinconf_to_config_argument(configs[i]);
 351
 352                 switch (param) {
 353                 case PIN_CONFIG_DRIVE_PUSH_PULL:
 354                         pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
 355                         break;
 356                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 357                         if (!pad->have_buffer)
 358                                 return -EINVAL;
 359                         pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
 360                         break;
 361                 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 362                         if (!pad->have_buffer)
 363                                 return -EINVAL;
 364                         pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
 365                         break;
 366                 case PIN_CONFIG_BIAS_DISABLE:
 367                         pad->pullup = PMIC_GPIO_PULL_DISABLE;
 368                         break;
 369                 case PIN_CONFIG_BIAS_PULL_UP:
 370                         pad->pullup = PMIC_GPIO_PULL_UP_30;
 371                         break;
 372                 case PIN_CONFIG_BIAS_PULL_DOWN:
 373                         if (arg)
 374                                 pad->pullup = PMIC_GPIO_PULL_DOWN;
 375                         else
 376                                 pad->pullup = PMIC_GPIO_PULL_DISABLE;
 377                         break;
 378                 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 379                         pad->is_enabled = false;
 380                         break;
 381                 case PIN_CONFIG_POWER_SOURCE:
 382                         if (arg > pad->num_sources)
 383                                 return -EINVAL;
 384                         pad->power_source = arg;
 385                         break;
 386                 case PIN_CONFIG_INPUT_ENABLE:
 387                         pad->input_enabled = arg ? true : false;
 388                         break;
 389                 case PIN_CONFIG_OUTPUT:
 390                         pad->output_enabled = true;
 391                         pad->out_value = arg;
 392                         break;
 393                 case PMIC_GPIO_CONF_PULL_UP:
 394                         if (arg > PMIC_GPIO_PULL_UP_1P5_30)
 395                                 return -EINVAL;
 396                         pad->pullup = arg;
 397                         break;
 398                 case PMIC_GPIO_CONF_STRENGTH:
 399                         if (arg > PMIC_GPIO_STRENGTH_LOW)
 400                                 return -EINVAL;
 401                         pad->strength = arg;
 402                         break;
 403                 default:
 404                         return -EINVAL;
 405                 }
 406         }
 407
 408         val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
 409
 410         ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
 411         if (ret < 0)
 412                 return ret;
 413
 414         val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
 415
 416         ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
 417         if (ret < 0)
 418                 return ret;
 419
 420         val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
 421         val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
 422
 423         ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
 424         if (ret < 0)
 425                 return ret;
 426
 427         val = 0;
 428         if (pad->output_enabled) {
 429                 if (pad->input_enabled)
 430                         val = 2;
 431                 else
 432                         val = 1;
 433         }
 434
 435         val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
 436         val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
 437         val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
 438
 439         return pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
 440 }
 441
 442 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
 443                                       struct seq_file *s, unsigned pin)
 444 {
 445         struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
 446         struct pmic_gpio_pad *pad;
 447         int ret, val;
 448
 449         static const char *const biases[] = {
 450                 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
 451                 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
 452         };
 453         static const char *const buffer_types[] = {
 454                 "push-pull", "open-drain", "open-source"
 455         };
 456         static const char *const strengths[] = {
 457                 "no", "high", "medium", "low"
 458         };
 459
 460         pad = pctldev->desc->pins[pin].drv_data;
 461
 462         seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
 463
 464         val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
 465
 466         if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
 467                 seq_puts(s, " ---");
 468         } else {
 469
 470                 if (pad->input_enabled) {
 471                         ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
 472                         if (ret < 0)
 473                                 return;
 474
 475                         ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
 476                         pad->out_value = ret;
 477                 }
 478
 479                 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
 480                 seq_printf(s, " %-7s", pmic_gpio_functions[pad->function]);
 481                 seq_printf(s, " vin-%d", pad->power_source);
 482                 seq_printf(s, " %-27s", biases[pad->pullup]);
 483                 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
 484                 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
 485                 seq_printf(s, " %-7s", strengths[pad->strength]);
 486         }
 487 }
 488
 489 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
 490         .is_generic                     = true,
 491         .pin_config_group_get           = pmic_gpio_config_get,
 492         .pin_config_group_set           = pmic_gpio_config_set,
 493         .pin_config_group_dbg_show      = pmic_gpio_config_dbg_show,
 494 };
 495
 496 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
 497 {
 498         struct pmic_gpio_state *state = to_gpio_state(chip);
 499         unsigned long config;
 500
 501         config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
 502
 503         return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
 504 }
 505
 506 static int pmic_gpio_direction_output(struct gpio_chip *chip,
 507                                       unsigned pin, int val)
 508 {
 509         struct pmic_gpio_state *state = to_gpio_state(chip);
 510         unsigned long config;
 511
 512         config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
 513
 514         return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
 515 }
 516
 517 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
 518 {
 519         struct pmic_gpio_state *state = to_gpio_state(chip);
 520         struct pmic_gpio_pad *pad;
 521         int ret;
 522
 523         pad = state->ctrl->desc->pins[pin].drv_data;
 524
 525         if (!pad->is_enabled)
 526                 return -EINVAL;
 527
 528         if (pad->input_enabled) {
 529                 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
 530                 if (ret < 0)
 531                         return ret;
 532
 533                 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
 534         }
 535
 536         return pad->out_value;
 537 }
 538
 539 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
 540 {
 541         struct pmic_gpio_state *state = to_gpio_state(chip);
 542         unsigned long config;
 543
 544         config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
 545
 546         pmic_gpio_config_set(state->ctrl, pin, &config, 1);
 547 }
 548
 549 static int pmic_gpio_request(struct gpio_chip *chip, unsigned base)
 550 {
 551         return pinctrl_request_gpio(chip->base + base);
 552 }
 553
 554 static void pmic_gpio_free(struct gpio_chip *chip, unsigned base)
 555 {
 556         pinctrl_free_gpio(chip->base + base);
 557 }
 558
 559 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
 560                               const struct of_phandle_args *gpio_desc,
 561                               u32 *flags)
 562 {
 563         if (chip->of_gpio_n_cells < 2)
 564                 return -EINVAL;
 565
 566         if (flags)
 567                 *flags = gpio_desc->args[1];
 568
 569         return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
 570 }
 571
 572 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
 573 {
 574         struct pmic_gpio_state *state = to_gpio_state(chip);
 575         struct pmic_gpio_pad *pad;
 576
 577         pad = state->ctrl->desc->pins[pin].drv_data;
 578
 579         return pad->irq;
 580 }
 581
 582 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 583 {
 584         struct pmic_gpio_state *state = to_gpio_state(chip);
 585         unsigned i;
 586
 587         for (i = 0; i < chip->ngpio; i++) {
 588                 pmic_gpio_config_dbg_show(state->ctrl, s, i);
 589                 seq_puts(s, "\n");
 590         }
 591 }
 592
 593 static const struct gpio_chip pmic_gpio_gpio_template = {
 594         .direction_input        = pmic_gpio_direction_input,
 595         .direction_output       = pmic_gpio_direction_output,
 596         .get                    = pmic_gpio_get,
 597         .set                    = pmic_gpio_set,
 598         .request                = pmic_gpio_request,
 599         .free                   = pmic_gpio_free,
 600         .of_xlate               = pmic_gpio_of_xlate,
 601         .to_irq                 = pmic_gpio_to_irq,
 602         .dbg_show               = pmic_gpio_dbg_show,
 603 };
 604
 605 static int pmic_gpio_populate(struct pmic_gpio_state *state,
 606                               struct pmic_gpio_pad *pad)
 607 {
 608         int type, subtype, val, dir;
 609
 610         type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
 611         if (type < 0)
 612                 return type;
 613
 614         if (type != PMIC_GPIO_TYPE) {
 615                 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
 616                         type, pad->base);
 617                 return -ENODEV;
 618         }
 619
 620         subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
 621         if (subtype < 0)
 622                 return subtype;
 623
 624         switch (subtype) {
 625         case PMIC_GPIO_SUBTYPE_GPIO_4CH:
 626                 pad->have_buffer = true;
 627         case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
 628                 pad->num_sources = 4;
 629                 break;
 630         case PMIC_GPIO_SUBTYPE_GPIO_8CH:
 631                 pad->have_buffer = true;
 632         case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
 633                 pad->num_sources = 8;
 634                 break;
 635         default:
 636                 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
 637                 return -ENODEV;
 638         }
 639
 640         val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
 641         if (val < 0)
 642                 return val;
 643
 644         pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
 645
 646         dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
 647         dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
 648         switch (dir) {
 649         case 0:
 650                 pad->input_enabled = true;
 651                 pad->output_enabled = false;
 652                 break;
 653         case 1:
 654                 pad->input_enabled = false;
 655                 pad->output_enabled = true;
 656                 break;
 657         case 2:
 658                 pad->input_enabled = true;
 659                 pad->output_enabled = true;
 660                 break;
 661         default:
 662                 dev_err(state->dev, "unknown GPIO direction\n");
 663                 return -ENODEV;
 664         }
 665
 666         pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
 667         pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
 668
 669         val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
 670         if (val < 0)
 671                 return val;
 672
 673         pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
 674         pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
 675
 676         val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
 677         if (val < 0)
 678                 return val;
 679
 680         pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
 681         pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
 682
 683         val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
 684         if (val < 0)
 685                 return val;
 686
 687         pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
 688         pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
 689
 690         pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
 691         pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
 692
 693         /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
 694         pad->is_enabled = true;
 695         return 0;
 696 }
 697
 698 static int pmic_gpio_probe(struct platform_device *pdev)
 699 {
 700         struct device *dev = &pdev->dev;
 701         struct pinctrl_pin_desc *pindesc;
 702         struct pinctrl_desc *pctrldesc;
 703         struct pmic_gpio_pad *pad, *pads;
 704         struct pmic_gpio_state *state;
 705         int ret, npins, i;
 706         u32 res[2];
 707
 708         ret = of_property_read_u32_array(dev->of_node, "reg", res, 2);
 709         if (ret < 0) {
 710                 dev_err(dev, "missing base address and/or range");
 711                 return ret;
 712         }
 713
 714         npins = res[1] / PMIC_GPIO_ADDRESS_RANGE;
 715
 716         if (!npins)
 717                 return -EINVAL;
 718
 719         BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups));
 720
 721         state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
 722         if (!state)
 723                 return -ENOMEM;
 724
 725         platform_set_drvdata(pdev, state);
 726
 727         state->dev = &pdev->dev;
 728         state->map = dev_get_regmap(dev->parent, NULL);
 729
 730         pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
 731         if (!pindesc)
 732                 return -ENOMEM;
 733
 734         pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
 735         if (!pads)
 736                 return -ENOMEM;
 737
 738         pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
 739         if (!pctrldesc)
 740                 return -ENOMEM;
 741
 742         pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
 743         pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
 744         pctrldesc->confops = &pmic_gpio_pinconf_ops;
 745         pctrldesc->owner = THIS_MODULE;
 746         pctrldesc->name = dev_name(dev);
 747         pctrldesc->pins = pindesc;
 748         pctrldesc->npins = npins;
 749         pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
 750         pctrldesc->custom_params = pmic_gpio_bindings;
 751 #ifdef CONFIG_DEBUG_FS
 752         pctrldesc->custom_conf_items = pmic_conf_items;
 753 #endif
 754
 755         for (i = 0; i < npins; i++, pindesc++) {
 756                 pad = &pads[i];
 757                 pindesc->drv_data = pad;
 758                 pindesc->number = i;
 759                 pindesc->name = pmic_gpio_groups[i];
 760
 761                 pad->irq = platform_get_irq(pdev, i);
 762                 if (pad->irq < 0)
 763                         return pad->irq;
 764
 765                 pad->base = res[0] + i * PMIC_GPIO_ADDRESS_RANGE;
 766
 767                 ret = pmic_gpio_populate(state, pad);
 768                 if (ret < 0)
 769                         return ret;
 770         }
 771
 772         state->chip = pmic_gpio_gpio_template;
 773         state->chip.dev = dev;
 774         state->chip.base = -1;
 775         state->chip.ngpio = npins;
 776         state->chip.label = dev_name(dev);
 777         state->chip.of_gpio_n_cells = 2;
 778         state->chip.can_sleep = false;
 779
 780         state->ctrl = pinctrl_register(pctrldesc, dev, state);
 781         if (!state->ctrl)
 782                 return -ENODEV;
 783
 784         ret = gpiochip_add(&state->chip);
 785         if (ret) {
 786                 dev_err(state->dev, "can't add gpio chip\n");
 787                 goto err_chip;
 788         }
 789
 790         ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
 791         if (ret) {
 792                 dev_err(dev, "failed to add pin range\n");
 793                 goto err_range;
 794         }
 795
 796         return 0;
 797
 798 err_range:
 799         gpiochip_remove(&state->chip);
 800 err_chip:
 801         pinctrl_unregister(state->ctrl);
 802         return ret;
 803 }
 804
 805 static int pmic_gpio_remove(struct platform_device *pdev)
 806 {
 807         struct pmic_gpio_state *state = platform_get_drvdata(pdev);
 808
 809         gpiochip_remove(&state->chip);
 810         pinctrl_unregister(state->ctrl);
 811         return 0;
 812 }
 813
 814 static const struct of_device_id pmic_gpio_of_match[] = {
 815         { .compatible = "qcom,pm8916-gpio" },   /* 4 GPIO's */
 816         { .compatible = "qcom,pm8941-gpio" },   /* 36 GPIO's */
 817         { .compatible = "qcom,pma8084-gpio" },  /* 22 GPIO's */
 818         { },
 819 };
 820
 821 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
 822
 823 static struct platform_driver pmic_gpio_driver = {
 824         .driver = {
 825                    .name = "qcom-spmi-gpio",
 826                    .of_match_table = pmic_gpio_of_match,
 827         },
 828         .probe  = pmic_gpio_probe,
 829         .remove = pmic_gpio_remove,
 830 };
 831
 832 module_platform_driver(pmic_gpio_driver);
 833
 834 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
 835 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
 836 MODULE_ALIAS("platform:qcom-spmi-gpio");
 837 MODULE_LICENSE("GPL v2");