include/dt-bindings/clock/exynos5410.h

   1 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
   2 #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
   3
   4 /* core clocks */
   5 #define CLK_FIN_PLL 1
   6 #define CLK_FOUT_APLL 2
   7 #define CLK_FOUT_CPLL 3
   8 #define CLK_FOUT_MPLL 4
   9 #define CLK_FOUT_BPLL 5
  10 #define CLK_FOUT_KPLL 6
  11
  12 /* gate for special clocks (sclk) */
  13 #define CLK_SCLK_UART0 128
  14 #define CLK_SCLK_UART1 129
  15 #define CLK_SCLK_UART2 130
  16 #define CLK_SCLK_UART3 131
  17 #define CLK_SCLK_MMC0 132
  18 #define CLK_SCLK_MMC1 133
  19 #define CLK_SCLK_MMC2 134
  20
  21 /* gate clocks */
  22 #define CLK_UART0 257
  23 #define CLK_UART1 258
  24 #define CLK_UART2 259
  25 #define CLK_UART3 260
  26 #define CLK_MCT 315
  27 #define CLK_MMC0 351
  28 #define CLK_MMC1 352
  29 #define CLK_MMC2 353
  30
  31 #define CLK_NR_CLKS 512
  32
  33 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */