2 * arch/arm/mach-orion/pci.c
4 * PCI and PCIE functions for Marvell Orion System On Chip
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <asm/mach/pci.h>
18 /*****************************************************************************
19 * Orion has one PCIE controller and one PCI controller.
21 * Note1: The local PCIE bus number is '0'. The local PCI bus number
22 * follows the scanned PCIE bridged busses, if any.
24 * Note2: It is possible for PCI/PCIE agents to access many subsystem's
25 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
26 * device bus, Orion registers, etc. However this code only enable the
27 * access to DDR banks.
28 ****************************************************************************/
31 /*****************************************************************************
33 ****************************************************************************/
34 #define PCIE_CTRL ORION_PCIE_REG(0x1a00)
35 #define PCIE_STAT ORION_PCIE_REG(0x1a04)
36 #define PCIE_DEV_ID ORION_PCIE_REG(0x0000)
37 #define PCIE_CMD_STAT ORION_PCIE_REG(0x0004)
38 #define PCIE_DEV_REV ORION_PCIE_REG(0x0008)
39 #define PCIE_MASK ORION_PCIE_REG(0x1910)
40 #define PCIE_CONF_ADDR ORION_PCIE_REG(0x18f8)
41 #define PCIE_CONF_DATA ORION_PCIE_REG(0x18fc)
46 #define PCIE_STAT_LINK_DOWN 1
47 #define PCIE_STAT_BUS_OFFS 8
48 #define PCIE_STAT_BUS_MASK (0xff << PCIE_STAT_BUS_OFFS)
49 #define PCIE_STAT_DEV_OFFS 20
50 #define PCIE_STAT_DEV_MASK (0x1f << PCIE_STAT_DEV_OFFS)
55 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 24) | ((r) & 0xfc))
56 #define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8)
57 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
58 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
59 #define PCIE_CONF_ADDR_EN (1 << 31)
62 * PCIE config cycles are done by programming the PCIE_CONF_ADDR register
63 * and then reading the PCIE_CONF_DATA register. Need to make sure these
64 * transactions are atomic.
66 static DEFINE_SPINLOCK(orion_pcie_lock
);
68 void orion_pcie_id(u32
*dev
, u32
*rev
)
70 *dev
= orion_read(PCIE_DEV_ID
) >> 16;
71 *rev
= orion_read(PCIE_DEV_REV
) & 0xff;
74 u32
orion_pcie_local_bus_nr(void)
76 u32 stat
= orion_read(PCIE_STAT
);
77 return((stat
& PCIE_STAT_BUS_MASK
) >> PCIE_STAT_BUS_OFFS
);
80 static u32
orion_pcie_local_dev_nr(void)
82 u32 stat
= orion_read(PCIE_STAT
);
83 return((stat
& PCIE_STAT_DEV_MASK
) >> PCIE_STAT_DEV_OFFS
);
86 static u32
orion_pcie_no_link(void)
88 u32 stat
= orion_read(PCIE_STAT
);
89 return(stat
& PCIE_STAT_LINK_DOWN
);
92 static void orion_pcie_set_bus_nr(int nr
)
94 orion_clrbits(PCIE_STAT
, PCIE_STAT_BUS_MASK
);
95 orion_setbits(PCIE_STAT
, nr
<< PCIE_STAT_BUS_OFFS
);
98 static void orion_pcie_master_slave_enable(void)
100 orion_setbits(PCIE_CMD_STAT
, PCI_COMMAND_MASTER
|
105 static void orion_pcie_enable_interrupts(void)
108 * Enable interrupts lines
109 * INTA[24] INTB[25] INTC[26] INTD[27]
111 orion_setbits(PCIE_MASK
, 0xf<<24);
114 static int orion_pcie_valid_config(u32 bus
, u32 dev
)
117 * Don't go out when trying to access --
119 * 2. where there's no device connected (no link)
120 * 3. nonexisting devices on local bus
123 if ((orion_pcie_local_bus_nr() == bus
) &&
124 (orion_pcie_local_dev_nr() == dev
))
127 if (orion_pcie_no_link())
130 if (bus
== orion_pcie_local_bus_nr())
131 if (((orion_pcie_local_dev_nr() == 0) && (dev
!= 1)) ||
132 ((orion_pcie_local_dev_nr() != 0) && (dev
!= 0)))
138 static int orion_pcie_rd_conf(struct pci_bus
*bus
, u32 devfn
, int where
,
142 unsigned int dev
, rev
, pcie_addr
;
144 if (orion_pcie_valid_config(bus
->number
, PCI_SLOT(devfn
)) == 0) {
146 return PCIBIOS_DEVICE_NOT_FOUND
;
149 spin_lock_irqsave(&orion_pcie_lock
, flags
);
151 orion_write(PCIE_CONF_ADDR
, PCIE_CONF_BUS(bus
->number
) |
152 PCIE_CONF_DEV(PCI_SLOT(devfn
)) |
153 PCIE_CONF_FUNC(PCI_FUNC(devfn
)) |
154 PCIE_CONF_REG(where
) | PCIE_CONF_ADDR_EN
);
156 orion_pcie_id(&dev
, &rev
);
157 if (dev
== MV88F5181_DEV_ID
|| dev
== MV88F5182_DEV_ID
) {
158 /* extended register space */
159 pcie_addr
= ORION_PCIE_WA_VIRT_BASE
;
160 pcie_addr
|= PCIE_CONF_BUS(bus
->number
) |
161 PCIE_CONF_DEV(PCI_SLOT(devfn
)) |
162 PCIE_CONF_FUNC(PCI_FUNC(devfn
)) |
163 PCIE_CONF_REG(where
);
164 *val
= orion_read(pcie_addr
);
166 *val
= orion_read(PCIE_CONF_DATA
);
169 *val
= (*val
>> (8*(where
& 0x3))) & 0xff;
171 *val
= (*val
>> (8*(where
& 0x3))) & 0xffff;
173 spin_unlock_irqrestore(&orion_pcie_lock
, flags
);
175 return PCIBIOS_SUCCESSFUL
;
179 static int orion_pcie_wr_conf(struct pci_bus
*bus
, u32 devfn
, int where
,
185 if (orion_pcie_valid_config(bus
->number
, PCI_SLOT(devfn
)) == 0)
186 return PCIBIOS_DEVICE_NOT_FOUND
;
188 spin_lock_irqsave(&orion_pcie_lock
, flags
);
190 ret
= PCIBIOS_SUCCESSFUL
;
192 orion_write(PCIE_CONF_ADDR
, PCIE_CONF_BUS(bus
->number
) |
193 PCIE_CONF_DEV(PCI_SLOT(devfn
)) |
194 PCIE_CONF_FUNC(PCI_FUNC(devfn
)) |
195 PCIE_CONF_REG(where
) | PCIE_CONF_ADDR_EN
);
198 __raw_writel(val
, PCIE_CONF_DATA
);
199 } else if (size
== 2) {
200 __raw_writew(val
, PCIE_CONF_DATA
+ (where
& 0x3));
201 } else if (size
== 1) {
202 __raw_writeb(val
, PCIE_CONF_DATA
+ (where
& 0x3));
204 ret
= PCIBIOS_BAD_REGISTER_NUMBER
;
207 spin_unlock_irqrestore(&orion_pcie_lock
, flags
);
212 struct pci_ops orion_pcie_ops
= {
213 .read
= orion_pcie_rd_conf
,
214 .write
= orion_pcie_wr_conf
,
218 static int orion_pcie_setup(struct pci_sys_data
*sys
)
220 struct resource
*res
;
223 * Master + Slave enable
225 orion_pcie_master_slave_enable();
228 * Enable interrupts lines A-D
230 orion_pcie_enable_interrupts();
235 res
= kzalloc(sizeof(struct resource
) * 2, GFP_KERNEL
);
237 panic("orion_pci_setup unable to alloc resources");
242 res
[0].name
= "PCI-EX I/O Space";
243 res
[0].flags
= IORESOURCE_IO
;
244 res
[0].start
= ORION_PCIE_IO_BUS_BASE
;
245 res
[0].end
= res
[0].start
+ ORION_PCIE_IO_SIZE
- 1;
246 if (request_resource(&ioport_resource
, &res
[0]))
247 panic("Request PCIE IO resource failed\n");
248 sys
->resource
[0] = &res
[0];
253 res
[1].name
= "PCI-EX Memory Space";
254 res
[1].flags
= IORESOURCE_MEM
;
255 res
[1].start
= ORION_PCIE_MEM_PHYS_BASE
;
256 res
[1].end
= res
[1].start
+ ORION_PCIE_MEM_SIZE
- 1;
257 if (request_resource(&iomem_resource
, &res
[1]))
258 panic("Request PCIE Memory resource failed\n");
259 sys
->resource
[1] = &res
[1];
261 sys
->resource
[2] = NULL
;
267 /*****************************************************************************
269 ****************************************************************************/
270 #define PCI_MODE ORION_PCI_REG(0xd00)
271 #define PCI_CMD ORION_PCI_REG(0xc00)
272 #define PCI_P2P_CONF ORION_PCI_REG(0x1d14)
273 #define PCI_CONF_ADDR ORION_PCI_REG(0xc78)
274 #define PCI_CONF_DATA ORION_PCI_REG(0xc7c)
279 #define PCI_MODE_64BIT (1 << 2)
280 #define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
285 #define PCI_CMD_HOST_REORDER (1 << 29)
290 #define PCI_P2P_BUS_OFFS 16
291 #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
292 #define PCI_P2P_DEV_OFFS 24
293 #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
298 #define PCI_CONF_REG(reg) ((reg) & 0xfc)
299 #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
300 #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
301 #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
302 #define PCI_CONF_ADDR_EN (1 << 31)
305 * Internal configuration space
307 #define PCI_CONF_FUNC_STAT_CMD 0
308 #define PCI_CONF_REG_STAT_CMD 4
309 #define PCIX_STAT 0x64
310 #define PCIX_STAT_BUS_OFFS 8
311 #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
314 * PCI config cycles are done by programming the PCI_CONF_ADDR register
315 * and then reading the PCI_CONF_DATA register. Need to make sure these
316 * transactions are atomic.
318 static DEFINE_SPINLOCK(orion_pci_lock
);
320 u32
orion_pci_local_bus_nr(void)
322 u32 conf
= orion_read(PCI_P2P_CONF
);
323 return((conf
& PCI_P2P_BUS_MASK
) >> PCI_P2P_BUS_OFFS
);
326 u32
orion_pci_local_dev_nr(void)
328 u32 conf
= orion_read(PCI_P2P_CONF
);
329 return((conf
& PCI_P2P_DEV_MASK
) >> PCI_P2P_DEV_OFFS
);
332 int orion_pci_hw_rd_conf(u32 bus
, u32 dev
, u32 func
,
333 u32 where
, u32 size
, u32
*val
)
336 spin_lock_irqsave(&orion_pci_lock
, flags
);
338 orion_write(PCI_CONF_ADDR
, PCI_CONF_BUS(bus
) |
339 PCI_CONF_DEV(dev
) | PCI_CONF_REG(where
) |
340 PCI_CONF_FUNC(func
) | PCI_CONF_ADDR_EN
);
342 *val
= orion_read(PCI_CONF_DATA
);
345 *val
= (*val
>> (8*(where
& 0x3))) & 0xff;
347 *val
= (*val
>> (8*(where
& 0x3))) & 0xffff;
349 spin_unlock_irqrestore(&orion_pci_lock
, flags
);
351 return PCIBIOS_SUCCESSFUL
;
354 int orion_pci_hw_wr_conf(u32 bus
, u32 dev
, u32 func
,
355 u32 where
, u32 size
, u32 val
)
358 int ret
= PCIBIOS_SUCCESSFUL
;
360 spin_lock_irqsave(&orion_pci_lock
, flags
);
362 orion_write(PCI_CONF_ADDR
, PCI_CONF_BUS(bus
) |
363 PCI_CONF_DEV(dev
) | PCI_CONF_REG(where
) |
364 PCI_CONF_FUNC(func
) | PCI_CONF_ADDR_EN
);
367 __raw_writel(val
, PCI_CONF_DATA
);
368 } else if (size
== 2) {
369 __raw_writew(val
, PCI_CONF_DATA
+ (where
& 0x3));
370 } else if (size
== 1) {
371 __raw_writeb(val
, PCI_CONF_DATA
+ (where
& 0x3));
373 ret
= PCIBIOS_BAD_REGISTER_NUMBER
;
376 spin_unlock_irqrestore(&orion_pci_lock
, flags
);
381 static int orion_pci_rd_conf(struct pci_bus
*bus
, u32 devfn
,
382 int where
, int size
, u32
*val
)
385 * Don't go out for local device
387 if ((orion_pci_local_bus_nr() == bus
->number
) &&
388 (orion_pci_local_dev_nr() == PCI_SLOT(devfn
))) {
390 return PCIBIOS_DEVICE_NOT_FOUND
;
393 return orion_pci_hw_rd_conf(bus
->number
, PCI_SLOT(devfn
),
394 PCI_FUNC(devfn
), where
, size
, val
);
397 static int orion_pci_wr_conf(struct pci_bus
*bus
, u32 devfn
,
398 int where
, int size
, u32 val
)
401 * Don't go out for local device
403 if ((orion_pci_local_bus_nr() == bus
->number
) &&
404 (orion_pci_local_dev_nr() == PCI_SLOT(devfn
)))
405 return PCIBIOS_DEVICE_NOT_FOUND
;
407 return orion_pci_hw_wr_conf(bus
->number
, PCI_SLOT(devfn
),
408 PCI_FUNC(devfn
), where
, size
, val
);
411 struct pci_ops orion_pci_ops
= {
412 .read
= orion_pci_rd_conf
,
413 .write
= orion_pci_wr_conf
,
416 static void orion_pci_set_bus_nr(int nr
)
418 u32 p2p
= orion_read(PCI_P2P_CONF
);
420 if (orion_read(PCI_MODE
) & PCI_MODE_PCIX
) {
424 u32 pcix_status
, bus
, dev
;
425 bus
= (p2p
& PCI_P2P_BUS_MASK
) >> PCI_P2P_BUS_OFFS
;
426 dev
= (p2p
& PCI_P2P_DEV_MASK
) >> PCI_P2P_DEV_OFFS
;
427 orion_pci_hw_rd_conf(bus
, dev
, 0, PCIX_STAT
, 4, &pcix_status
);
428 pcix_status
&= ~PCIX_STAT_BUS_MASK
;
429 pcix_status
|= (nr
<< PCIX_STAT_BUS_OFFS
);
430 orion_pci_hw_wr_conf(bus
, dev
, 0, PCIX_STAT
, 4, pcix_status
);
433 * PCI Conventional mode
435 p2p
&= ~PCI_P2P_BUS_MASK
;
436 p2p
|= (nr
<< PCI_P2P_BUS_OFFS
);
437 orion_write(PCI_P2P_CONF
, p2p
);
441 static void orion_pci_master_slave_enable(void)
443 u32 bus_nr
, dev_nr
, func
, reg
, val
;
445 bus_nr
= orion_pci_local_bus_nr();
446 dev_nr
= orion_pci_local_dev_nr();
447 func
= PCI_CONF_FUNC_STAT_CMD
;
448 reg
= PCI_CONF_REG_STAT_CMD
;
449 orion_pci_hw_rd_conf(bus_nr
, dev_nr
, func
, reg
, 4, &val
);
450 val
|= (PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
451 orion_pci_hw_wr_conf(bus_nr
, dev_nr
, func
, reg
, 4, val
| 0x7);
454 static int orion_pci_setup(struct pci_sys_data
*sys
)
456 struct resource
*res
;
459 * Master + Slave enable
461 orion_pci_master_slave_enable();
466 orion_setbits(PCI_CMD
, PCI_CMD_HOST_REORDER
);
471 res
= kzalloc(sizeof(struct resource
) * 2, GFP_KERNEL
);
473 panic("orion_pci_setup unable to alloc resources");
478 res
[0].name
= "PCI I/O Space";
479 res
[0].flags
= IORESOURCE_IO
;
480 res
[0].start
= ORION_PCI_IO_BUS_BASE
;
481 res
[0].end
= res
[0].start
+ ORION_PCI_IO_SIZE
- 1;
482 if (request_resource(&ioport_resource
, &res
[0]))
483 panic("Request PCI IO resource failed\n");
484 sys
->resource
[0] = &res
[0];
489 res
[1].name
= "PCI Memory Space";
490 res
[1].flags
= IORESOURCE_MEM
;
491 res
[1].start
= ORION_PCI_MEM_PHYS_BASE
;
492 res
[1].end
= res
[1].start
+ ORION_PCI_MEM_SIZE
- 1;
493 if (request_resource(&iomem_resource
, &res
[1]))
494 panic("Request PCI Memory resource failed\n");
495 sys
->resource
[1] = &res
[1];
497 sys
->resource
[2] = NULL
;
504 /*****************************************************************************
506 ****************************************************************************/
507 int orion_pci_sys_setup(int nr
, struct pci_sys_data
*sys
)
515 orion_pcie_set_bus_nr(0);
516 ret
= orion_pcie_setup(sys
);
517 } else if (nr
== 1) {
521 ret
= orion_pci_setup(sys
);
527 struct pci_bus
*orion_pci_sys_scan_bus(int nr
, struct pci_sys_data
*sys
)
538 ops
= &orion_pcie_ops
;
539 bus
= pci_scan_bus(sys
->busnr
, ops
, sys
);
541 * Set local PCI bus number to follow PCIE bridges (if any)
543 pci_bus
= bus
->number
+ bus
->subordinate
- bus
->secondary
+ 1;
544 orion_pci_set_bus_nr(pci_bus
);
545 } else if (nr
== 1) {
549 ops
= &orion_pci_ops
;
550 bus
= pci_scan_bus(sys
->busnr
, ops
, sys
);