arch/ia64/pci/pci.c

   1 /*
   2  * pci.c - Low-Level PCI Access in IA-64
   3  *
   4  * Derived from bios32.c of i386 tree.
   5  *
   6  * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
   7  *      David Mosberger-Tang <davidm@hpl.hp.com>
   8  *      Bjorn Helgaas <bjorn.helgaas@hp.com>
   9  * Copyright (C) 2004 Silicon Graphics, Inc.
  10  *
  11  * Note: Above list of copyright holders is incomplete...
  12  */
  13
  14 #include <linux/acpi.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22
  23 #include <asm/machvec.h>
  24 #include <asm/page.h>
  25 #include <asm/system.h>
  26 #include <asm/io.h>
  27 #include <asm/sal.h>
  28 #include <asm/smp.h>
  29 #include <asm/irq.h>
  30 #include <asm/hw_irq.h>
  31
  32 /*
  33  * Low-level SAL-based PCI configuration access functions. Note that SAL
  34  * calls are already serialized (via sal_lock), so we don't need another
  35  * synchronization mechanism here.
  36  */
  37
  38 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg)           \
  39         (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
  40
  41 /* SAL 3.2 adds support for extended config space. */
  42
  43 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg)       \
  44         (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
  45
  46 int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
  47               int reg, int len, u32 *value)
  48 {
  49         u64 addr, data = 0;
  50         int mode, result;
  51
  52         if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  53                 return -EINVAL;
  54
  55         if ((seg | reg) <= 255) {
  56                 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  57                 mode = 0;
  58         } else {
  59                 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  60                 mode = 1;
  61         }
  62         result = ia64_sal_pci_config_read(addr, mode, len, &data);
  63         if (result != 0)
  64                 return -EINVAL;
  65
  66         *value = (u32) data;
  67         return 0;
  68 }
  69
  70 int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
  71                int reg, int len, u32 value)
  72 {
  73         u64 addr;
  74         int mode, result;
  75
  76         if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  77                 return -EINVAL;
  78
  79         if ((seg | reg) <= 255) {
  80                 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  81                 mode = 0;
  82         } else {
  83                 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  84                 mode = 1;
  85         }
  86         result = ia64_sal_pci_config_write(addr, mode, len, value);
  87         if (result != 0)
  88                 return -EINVAL;
  89         return 0;
  90 }
  91
  92 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
  93                                                         int size, u32 *value)
  94 {
  95         return raw_pci_read(pci_domain_nr(bus), bus->number,
  96                                  devfn, where, size, value);
  97 }
  98
  99 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
 100                                                         int size, u32 value)
 101 {
 102         return raw_pci_write(pci_domain_nr(bus), bus->number,
 103                                   devfn, where, size, value);
 104 }
 105
 106 struct pci_ops pci_root_ops = {
 107         .read = pci_read,
 108         .write = pci_write,
 109 };
 110
 111 /* Called by ACPI when it finds a new root bus.  */
 112
 113 static struct pci_controller * __devinit
 114 alloc_pci_controller (int seg)
 115 {
 116         struct pci_controller *controller;
 117
 118         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 119         if (!controller)
 120                 return NULL;
 121
 122         controller->segment = seg;
 123         controller->node = -1;
 124         return controller;
 125 }
 126
 127 struct pci_root_info {
 128         struct pci_controller *controller;
 129         char *name;
 130 };
 131
 132 static unsigned int
 133 new_space (u64 phys_base, int sparse)
 134 {
 135         u64 mmio_base;
 136         int i;
 137
 138         if (phys_base == 0)
 139                 return 0;       /* legacy I/O port space */
 140
 141         mmio_base = (u64) ioremap(phys_base, 0);
 142         for (i = 0; i < num_io_spaces; i++)
 143                 if (io_space[i].mmio_base == mmio_base &&
 144                     io_space[i].sparse == sparse)
 145                         return i;
 146
 147         if (num_io_spaces == MAX_IO_SPACES) {
 148                 printk(KERN_ERR "PCI: Too many IO port spaces "
 149                         "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
 150                 return ~0;
 151         }
 152
 153         i = num_io_spaces++;
 154         io_space[i].mmio_base = mmio_base;
 155         io_space[i].sparse = sparse;
 156
 157         return i;
 158 }
 159
 160 static u64 __devinit
 161 add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr)
 162 {
 163         struct resource *resource;
 164         char *name;
 165         u64 base, min, max, base_port;
 166         unsigned int sparse = 0, space_nr, len;
 167
 168         resource = kzalloc(sizeof(*resource), GFP_KERNEL);
 169         if (!resource) {
 170                 printk(KERN_ERR "PCI: No memory for %s I/O port space\n",
 171                         info->name);
 172                 goto out;
 173         }
 174
 175         len = strlen(info->name) + 32;
 176         name = kzalloc(len, GFP_KERNEL);
 177         if (!name) {
 178                 printk(KERN_ERR "PCI: No memory for %s I/O port space name\n",
 179                         info->name);
 180                 goto free_resource;
 181         }
 182
 183         min = addr->minimum;
 184         max = min + addr->address_length - 1;
 185         if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION)
 186                 sparse = 1;
 187
 188         space_nr = new_space(addr->translation_offset, sparse);
 189         if (space_nr == ~0)
 190                 goto free_name;
 191
 192         base = __pa(io_space[space_nr].mmio_base);
 193         base_port = IO_SPACE_BASE(space_nr);
 194         snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name,
 195                 base_port + min, base_port + max);
 196
 197         /*
 198          * The SDM guarantees the legacy 0-64K space is sparse, but if the
 199          * mapping is done by the processor (not the bridge), ACPI may not
 200          * mark it as sparse.
 201          */
 202         if (space_nr == 0)
 203                 sparse = 1;
 204
 205         resource->name  = name;
 206         resource->flags = IORESOURCE_MEM;
 207         resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
 208         resource->end   = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
 209         insert_resource(&iomem_resource, resource);
 210
 211         return base_port;
 212
 213 free_name:
 214         kfree(name);
 215 free_resource:
 216         kfree(resource);
 217 out:
 218         return ~0;
 219 }
 220
 221 static acpi_status __devinit resource_to_window(struct acpi_resource *resource,
 222         struct acpi_resource_address64 *addr)
 223 {
 224         acpi_status status;
 225
 226         /*
 227          * We're only interested in _CRS descriptors that are
 228          *      - address space descriptors for memory or I/O space
 229          *      - non-zero size
 230          *      - producers, i.e., the address space is routed downstream,
 231          *        not consumed by the bridge itself
 232          */
 233         status = acpi_resource_to_address64(resource, addr);
 234         if (ACPI_SUCCESS(status) &&
 235             (addr->resource_type == ACPI_MEMORY_RANGE ||
 236              addr->resource_type == ACPI_IO_RANGE) &&
 237             addr->address_length &&
 238             addr->producer_consumer == ACPI_PRODUCER)
 239                 return AE_OK;
 240
 241         return AE_ERROR;
 242 }
 243
 244 static acpi_status __devinit
 245 count_window (struct acpi_resource *resource, void *data)
 246 {
 247         unsigned int *windows = (unsigned int *) data;
 248         struct acpi_resource_address64 addr;
 249         acpi_status status;
 250
 251         status = resource_to_window(resource, &addr);
 252         if (ACPI_SUCCESS(status))
 253                 (*windows)++;
 254
 255         return AE_OK;
 256 }
 257
 258 static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
 259 {
 260         struct pci_root_info *info = data;
 261         struct pci_window *window;
 262         struct acpi_resource_address64 addr;
 263         acpi_status status;
 264         unsigned long flags, offset = 0;
 265         struct resource *root;
 266
 267         /* Return AE_OK for non-window resources to keep scanning for more */
 268         status = resource_to_window(res, &addr);
 269         if (!ACPI_SUCCESS(status))
 270                 return AE_OK;
 271
 272         if (addr.resource_type == ACPI_MEMORY_RANGE) {
 273                 flags = IORESOURCE_MEM;
 274                 root = &iomem_resource;
 275                 offset = addr.translation_offset;
 276         } else if (addr.resource_type == ACPI_IO_RANGE) {
 277                 flags = IORESOURCE_IO;
 278                 root = &ioport_resource;
 279                 offset = add_io_space(info, &addr);
 280                 if (offset == ~0)
 281                         return AE_OK;
 282         } else
 283                 return AE_OK;
 284
 285         window = &info->controller->window[info->controller->windows++];
 286         window->resource.name = info->name;
 287         window->resource.flags = flags;
 288         window->resource.start = addr.minimum + offset;
 289         window->resource.end = window->resource.start + addr.address_length - 1;
 290         window->resource.child = NULL;
 291         window->offset = offset;
 292
 293         if (insert_resource(root, &window->resource)) {
 294                 printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
 295                         window->resource.start, window->resource.end,
 296                         root->name, info->name);
 297         }
 298
 299         return AE_OK;
 300 }
 301
 302 static void __devinit
 303 pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
 304 {
 305         int i, j;
 306
 307         j = 0;
 308         for (i = 0; i < ctrl->windows; i++) {
 309                 struct resource *res = &ctrl->window[i].resource;
 310                 /* HP's firmware has a hack to work around a Windows bug.
 311                  * Ignore these tiny memory ranges */
 312                 if ((res->flags & IORESOURCE_MEM) &&
 313                     (res->end - res->start < 16))
 314                         continue;
 315                 if (j >= PCI_BUS_NUM_RESOURCES) {
 316                         printk("Ignoring range [%lx-%lx] (%lx)\n", res->start,
 317                                         res->end, res->flags);
 318                         continue;
 319                 }
 320                 bus->resource[j++] = res;
 321         }
 322 }
 323
 324 struct pci_bus * __devinit
 325 pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
 326 {
 327         struct pci_root_info info;
 328         struct pci_controller *controller;
 329         unsigned int windows = 0;
 330         struct pci_bus *pbus;
 331         char *name;
 332         int pxm;
 333
 334         controller = alloc_pci_controller(domain);
 335         if (!controller)
 336                 goto out1;
 337
 338         controller->acpi_handle = device->handle;
 339
 340         pxm = acpi_get_pxm(controller->acpi_handle);
 341 #ifdef CONFIG_NUMA
 342         if (pxm >= 0)
 343                 controller->node = pxm_to_node(pxm);
 344 #endif
 345
 346         acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
 347                         &windows);
 348         if (windows) {
 349                 controller->window =
 350                         kmalloc_node(sizeof(*controller->window) * windows,
 351                                      GFP_KERNEL, controller->node);
 352                 if (!controller->window)
 353                         goto out2;
 354         }
 355
 356         name = kmalloc(16, GFP_KERNEL);
 357         if (!name)
 358                 goto out3;
 359
 360         sprintf(name, "PCI Bus %04x:%02x", domain, bus);
 361         info.controller = controller;
 362         info.name = name;
 363         acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window,
 364                         &info);
 365         /*
 366          * See arch/x86/pci/acpi.c.
 367          * The desired pci bus might already be scanned in a quirk. We
 368          * should handle the case here, but it appears that IA64 hasn't
 369          * such quirk. So we just ignore the case now.
 370          */
 371         pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller);
 372         if (pbus)
 373                 pcibios_setup_root_windows(pbus, controller);
 374
 375         return pbus;
 376
 377 out3:
 378         kfree(controller->window);
 379 out2:
 380         kfree(controller);
 381 out1:
 382         return NULL;
 383 }
 384
 385 void pcibios_resource_to_bus(struct pci_dev *dev,
 386                 struct pci_bus_region *region, struct resource *res)
 387 {
 388         struct pci_controller *controller = PCI_CONTROLLER(dev);
 389         unsigned long offset = 0;
 390         int i;
 391
 392         for (i = 0; i < controller->windows; i++) {
 393                 struct pci_window *window = &controller->window[i];
 394                 if (!(window->resource.flags & res->flags))
 395                         continue;
 396                 if (window->resource.start > res->start)
 397                         continue;
 398                 if (window->resource.end < res->end)
 399                         continue;
 400                 offset = window->offset;
 401                 break;
 402         }
 403
 404         region->start = res->start - offset;
 405         region->end = res->end - offset;
 406 }
 407 EXPORT_SYMBOL(pcibios_resource_to_bus);
 408
 409 void pcibios_bus_to_resource(struct pci_dev *dev,
 410                 struct resource *res, struct pci_bus_region *region)
 411 {
 412         struct pci_controller *controller = PCI_CONTROLLER(dev);
 413         unsigned long offset = 0;
 414         int i;
 415
 416         for (i = 0; i < controller->windows; i++) {
 417                 struct pci_window *window = &controller->window[i];
 418                 if (!(window->resource.flags & res->flags))
 419                         continue;
 420                 if (window->resource.start - window->offset > region->start)
 421                         continue;
 422                 if (window->resource.end - window->offset < region->end)
 423                         continue;
 424                 offset = window->offset;
 425                 break;
 426         }
 427
 428         res->start = region->start + offset;
 429         res->end = region->end + offset;
 430 }
 431 EXPORT_SYMBOL(pcibios_bus_to_resource);
 432
 433 static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
 434 {
 435         unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
 436         struct resource *devr = &dev->resource[idx];
 437
 438         if (!dev->bus)
 439                 return 0;
 440         for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) {
 441                 struct resource *busr = dev->bus->resource[i];
 442
 443                 if (!busr || ((busr->flags ^ devr->flags) & type_mask))
 444                         continue;
 445                 if ((devr->start) && (devr->start >= busr->start) &&
 446                                 (devr->end <= busr->end))
 447                         return 1;
 448         }
 449         return 0;
 450 }
 451
 452 static void __devinit
 453 pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
 454 {
 455         struct pci_bus_region region;
 456         int i;
 457
 458         for (i = start; i < limit; i++) {
 459                 if (!dev->resource[i].flags)
 460                         continue;
 461                 region.start = dev->resource[i].start;
 462                 region.end = dev->resource[i].end;
 463                 pcibios_bus_to_resource(dev, &dev->resource[i], &region);
 464                 if ((is_valid_resource(dev, i)))
 465                         pci_claim_resource(dev, i);
 466         }
 467 }
 468
 469 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
 470 {
 471         pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES);
 472 }
 473 EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources);
 474
 475 static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev)
 476 {
 477         pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES);
 478 }
 479
 480 /*
 481  *  Called after each bus is probed, but before its children are examined.
 482  */
 483 void __devinit
 484 pcibios_fixup_bus (struct pci_bus *b)
 485 {
 486         struct pci_dev *dev;
 487
 488         if (b->self) {
 489                 pci_read_bridge_bases(b);
 490                 pcibios_fixup_bridge_resources(b->self);
 491         }
 492         list_for_each_entry(dev, &b->devices, bus_list)
 493                 pcibios_fixup_device_resources(dev);
 494         platform_pci_fixup_bus(b);
 495
 496         return;
 497 }
 498
 499 void __devinit
 500 pcibios_update_irq (struct pci_dev *dev, int irq)
 501 {
 502         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 503
 504         /* ??? FIXME -- record old value for shutdown.  */
 505 }
 506
 507 static inline int
 508 pcibios_enable_resources (struct pci_dev *dev, int mask)
 509 {
 510         u16 cmd, old_cmd;
 511         int idx;
 512         struct resource *r;
 513         unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM;
 514
 515         if (!dev)
 516                 return -EINVAL;
 517
 518         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 519         old_cmd = cmd;
 520         for (idx=0; idx<PCI_NUM_RESOURCES; idx++) {
 521                 /* Only set up the desired resources.  */
 522                 if (!(mask & (1 << idx)))
 523                         continue;
 524
 525                 r = &dev->resource[idx];
 526                 if (!(r->flags & type_mask))
 527                         continue;
 528                 if ((idx == PCI_ROM_RESOURCE) &&
 529                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
 530                         continue;
 531                 if (!r->start && r->end) {
 532                         printk(KERN_ERR
 533                                "PCI: Device %s not available because of resource collisions\n",
 534                                pci_name(dev));
 535                         return -EINVAL;
 536                 }
 537                 if (r->flags & IORESOURCE_IO)
 538                         cmd |= PCI_COMMAND_IO;
 539                 if (r->flags & IORESOURCE_MEM)
 540                         cmd |= PCI_COMMAND_MEMORY;
 541         }
 542         if (cmd != old_cmd) {
 543                 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
 544                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 545         }
 546         return 0;
 547 }
 548
 549 int
 550 pcibios_enable_device (struct pci_dev *dev, int mask)
 551 {
 552         int ret;
 553
 554         ret = pcibios_enable_resources(dev, mask);
 555         if (ret < 0)
 556                 return ret;
 557
 558         if (!dev->msi_enabled)
 559                 return acpi_pci_irq_enable(dev);
 560         return 0;
 561 }
 562
 563 void
 564 pcibios_disable_device (struct pci_dev *dev)
 565 {
 566         BUG_ON(atomic_read(&dev->enable_cnt));
 567         if (!dev->msi_enabled)
 568                 acpi_pci_irq_disable(dev);
 569 }
 570
 571 void
 572 pcibios_align_resource (void *data, struct resource *res,
 573                         resource_size_t size, resource_size_t align)
 574 {
 575 }
 576
 577 /*
 578  * PCI BIOS setup, always defaults to SAL interface
 579  */
 580 char * __devinit
 581 pcibios_setup (char *str)
 582 {
 583         return str;
 584 }
 585
 586 int
 587 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
 588                      enum pci_mmap_state mmap_state, int write_combine)
 589 {
 590         unsigned long size = vma->vm_end - vma->vm_start;
 591         pgprot_t prot;
 592
 593         /*
 594          * I/O space cannot be accessed via normal processor loads and
 595          * stores on this platform.
 596          */
 597         if (mmap_state == pci_mmap_io)
 598                 /*
 599                  * XXX we could relax this for I/O spaces for which ACPI
 600                  * indicates that the space is 1-to-1 mapped.  But at the
 601                  * moment, we don't support multiple PCI address spaces and
 602                  * the legacy I/O space is not 1-to-1 mapped, so this is moot.
 603                  */
 604                 return -EINVAL;
 605
 606         if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
 607                 return -EINVAL;
 608
 609         prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
 610                                     vma->vm_page_prot);
 611
 612         /*
 613          * If the user requested WC, the kernel uses UC or WC for this region,
 614          * and the chipset supports WC, we can use WC. Otherwise, we have to
 615          * use the same attribute the kernel uses.
 616          */
 617         if (write_combine &&
 618             ((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC ||
 619              (pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) &&
 620             efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))
 621                 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
 622         else
 623                 vma->vm_page_prot = prot;
 624
 625         if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 626                              vma->vm_end - vma->vm_start, vma->vm_page_prot))
 627                 return -EAGAIN;
 628
 629         return 0;
 630 }
 631
 632 /**
 633  * ia64_pci_get_legacy_mem - generic legacy mem routine
 634  * @bus: bus to get legacy memory base address for
 635  *
 636  * Find the base of legacy memory for @bus.  This is typically the first
 637  * megabyte of bus address space for @bus or is simply 0 on platforms whose
 638  * chipsets support legacy I/O and memory routing.  Returns the base address
 639  * or an error pointer if an error occurred.
 640  *
 641  * This is the ia64 generic version of this routine.  Other platforms
 642  * are free to override it with a machine vector.
 643  */
 644 char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
 645 {
 646         return (char *)__IA64_UNCACHED_OFFSET;
 647 }
 648
 649 /**
 650  * pci_mmap_legacy_page_range - map legacy memory space to userland
 651  * @bus: bus whose legacy space we're mapping
 652  * @vma: vma passed in by mmap
 653  *
 654  * Map legacy memory space for this device back to userspace using a machine
 655  * vector to get the base address.
 656  */
 657 int
 658 pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma)
 659 {
 660         unsigned long size = vma->vm_end - vma->vm_start;
 661         pgprot_t prot;
 662         char *addr;
 663
 664         /*
 665          * Avoid attribute aliasing.  See Documentation/ia64/aliasing.txt
 666          * for more details.
 667          */
 668         if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
 669                 return -EINVAL;
 670         prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
 671                                     vma->vm_page_prot);
 672
 673         addr = pci_get_legacy_mem(bus);
 674         if (IS_ERR(addr))
 675                 return PTR_ERR(addr);
 676
 677         vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
 678         vma->vm_page_prot = prot;
 679
 680         if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 681                             size, vma->vm_page_prot))
 682                 return -EAGAIN;
 683
 684         return 0;
 685 }
 686
 687 /**
 688  * ia64_pci_legacy_read - read from legacy I/O space
 689  * @bus: bus to read
 690  * @port: legacy port value
 691  * @val: caller allocated storage for returned value
 692  * @size: number of bytes to read
 693  *
 694  * Simply reads @size bytes from @port and puts the result in @val.
 695  *
 696  * Again, this (and the write routine) are generic versions that can be
 697  * overridden by the platform.  This is necessary on platforms that don't
 698  * support legacy I/O routing or that hard fail on legacy I/O timeouts.
 699  */
 700 int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
 701 {
 702         int ret = size;
 703
 704         switch (size) {
 705         case 1:
 706                 *val = inb(port);
 707                 break;
 708         case 2:
 709                 *val = inw(port);
 710                 break;
 711         case 4:
 712                 *val = inl(port);
 713                 break;
 714         default:
 715                 ret = -EINVAL;
 716                 break;
 717         }
 718
 719         return ret;
 720 }
 721
 722 /**
 723  * ia64_pci_legacy_write - perform a legacy I/O write
 724  * @bus: bus pointer
 725  * @port: port to write
 726  * @val: value to write
 727  * @size: number of bytes to write from @val
 728  *
 729  * Simply writes @size bytes of @val to @port.
 730  */
 731 int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
 732 {
 733         int ret = size;
 734
 735         switch (size) {
 736         case 1:
 737                 outb(val, port);
 738                 break;
 739         case 2:
 740                 outw(val, port);
 741                 break;
 742         case 4:
 743                 outl(val, port);
 744                 break;
 745         default:
 746                 ret = -EINVAL;
 747                 break;
 748         }
 749
 750         return ret;
 751 }
 752
 753 /* It's defined in drivers/pci/pci.c */
 754 extern u8 pci_cache_line_size;
 755
 756 /**
 757  * set_pci_cacheline_size - determine cacheline size for PCI devices
 758  *
 759  * We want to use the line-size of the outer-most cache.  We assume
 760  * that this line-size is the same for all CPUs.
 761  *
 762  * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
 763  */
 764 static void __init set_pci_cacheline_size(void)
 765 {
 766         u64 levels, unique_caches;
 767         s64 status;
 768         pal_cache_config_info_t cci;
 769
 770         status = ia64_pal_cache_summary(&levels, &unique_caches);
 771         if (status != 0) {
 772                 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed "
 773                         "(status=%ld)\n", __func__, status);
 774                 return;
 775         }
 776
 777         status = ia64_pal_cache_config_info(levels - 1,
 778                                 /* cache_type (data_or_unified)= */ 2, &cci);
 779         if (status != 0) {
 780                 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed "
 781                         "(status=%ld)\n", __func__, status);
 782                 return;
 783         }
 784         pci_cache_line_size = (1 << cci.pcci_line_size) / 4;
 785 }
 786
 787 static int __init pcibios_init(void)
 788 {
 789         set_pci_cacheline_size();
 790         return 0;
 791 }
 792
 793 subsys_initcall(pcibios_init);