arch/mips/au1000/common/setup.c

   1 /*
   2  * Copyright 2000 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc.
   4  *              ppopov@mvista.com or source@mvista.com
   5  *
   6  * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc.
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  *  You should have received a copy of the  GNU General Public License along
  25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26  *  675 Mass Ave, Cambridge, MA 02139, USA.
  27  */
  28 #include <linux/init.h>
  29 #include <linux/sched.h>
  30 #include <linux/ioport.h>
  31 #include <linux/mm.h>
  32 #include <linux/delay.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/module.h>
  35 #include <linux/pm.h>
  36
  37 #include <asm/cpu.h>
  38 #include <asm/bootinfo.h>
  39 #include <asm/irq.h>
  40 #include <asm/mipsregs.h>
  41 #include <asm/reboot.h>
  42 #include <asm/pgtable.h>
  43 #include <asm/time.h>
  44
  45 #include <au1000.h>
  46 #include <prom.h>
  47
  48 extern void __init board_setup(void);
  49 extern void au1000_restart(char *);
  50 extern void au1000_halt(void);
  51 extern void au1000_power_off(void);
  52 extern void au1x_time_init(void);
  53 extern void au1x_timer_setup(struct irqaction *irq);
  54 extern void set_cpuspec(void);
  55
  56 void __init plat_mem_setup(void)
  57 {
  58         struct  cpu_spec *sp;
  59         char *argptr;
  60         unsigned long prid, cpufreq, bclk = 1;
  61
  62         set_cpuspec();
  63         sp = cur_cpu_spec[0];
  64
  65         board_setup();  /* board specific setup */
  66
  67         prid = read_c0_prid();
  68         if (sp->cpu_pll_wo)
  69 #ifdef CONFIG_SOC_AU1000_FREQUENCY
  70                 cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000;
  71 #else
  72                 cpufreq = 396;
  73 #endif
  74         else
  75                 cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12;
  76         printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq);
  77
  78         bclk = sp->cpu_bclk;
  79         if (bclk)
  80         {
  81                 /* Enable BCLK switching */
  82                 bclk = au_readl(0xB190003C);
  83                 au_writel(bclk | 0x60, 0xB190003C);
  84                 printk("BCLK switching enabled!\n");
  85         }
  86
  87         if (sp->cpu_od) {
  88                 /* Various early Au1000 Errata corrected by this */
  89                 set_c0_config(1<<19); /* Set Config[OD] */
  90         }
  91         else {
  92                 /* Clear to obtain best system bus performance */
  93                 clear_c0_config(1<<19); /* Clear Config[OD] */
  94         }
  95
  96         argptr = prom_getcmdline();
  97
  98 #ifdef CONFIG_SERIAL_8250_CONSOLE
  99         if ((argptr = strstr(argptr, "console=")) == NULL) {
 100                 argptr = prom_getcmdline();
 101                 strcat(argptr, " console=ttyS0,115200");
 102         }
 103 #endif
 104
 105 #ifdef CONFIG_FB_AU1100
 106     if ((argptr = strstr(argptr, "video=")) == NULL) {
 107         argptr = prom_getcmdline();
 108         /* default panel */
 109         /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
 110     }
 111 #endif
 112
 113
 114 #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
 115         /* au1000 does not support vra, au1500 and au1100 do */
 116         strcat(argptr, " au1000_audio=vra");
 117         argptr = prom_getcmdline();
 118 #endif
 119         _machine_restart = au1000_restart;
 120         _machine_halt = au1000_halt;
 121         pm_power_off = au1000_power_off;
 122
 123         /* IO/MEM resources. */
 124         set_io_port_base(0);
 125         ioport_resource.start = IOPORT_RESOURCE_START;
 126         ioport_resource.end = IOPORT_RESOURCE_END;
 127         iomem_resource.start = IOMEM_RESOURCE_START;
 128         iomem_resource.end = IOMEM_RESOURCE_END;
 129
 130         while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
 131         au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
 132         au_sync();
 133         while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
 134         au_writel(0, SYS_TOYTRIM);
 135 }
 136
 137 #if defined(CONFIG_64BIT_PHYS_ADDR)
 138 /* This routine should be valid for all Au1x based boards */
 139 phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
 140 {
 141         /* Don't fixup 36 bit addresses */
 142         if ((phys_addr >> 32) != 0)
 143                 return phys_addr;
 144
 145 #ifdef CONFIG_PCI
 146         {
 147                 u32 start = (u32)Au1500_PCI_MEM_START;
 148                 u32 end   = (u32)Au1500_PCI_MEM_END;
 149
 150                 /* Check for PCI memory window */
 151                 if (phys_addr >= start && (phys_addr + size - 1) <= end)
 152                         return (phys_t)
 153                                ((phys_addr - start) + Au1500_PCI_MEM_START);
 154         }
 155 #endif
 156
 157         /* All Au1x SOCs have a pcmcia controller */
 158         /* We setup our 32 bit pseudo addresses to be equal to the
 159          * 36 bit addr >> 4, to make it easier to check the address
 160          * and fix it.
 161          * The Au1x socket 0 phys attribute address is 0xF 4000 0000.
 162          * The pseudo address we use is 0xF400 0000. Any address over
 163          * 0xF400 0000 is a pcmcia pseudo address.
 164          */
 165         if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) {
 166                 return (phys_t)(phys_addr << 4);
 167         }
 168
 169         /* default nop */
 170         return phys_addr;
 171 }
 172 EXPORT_SYMBOL(__fixup_bigphys_addr);
 173 #endif