arch/mips/au1000/common/time.c

   1 /*
   2  *
   3  * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com
   4  * Copied and modified Carsten Langgaard's time.c
   5  *
   6  * Carsten Langgaard, carstenl@mips.com
   7  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   8  *
   9  * ########################################################################
  10  *
  11  *  This program is free software; you can distribute it and/or modify it
  12  *  under the terms of the GNU General Public License (Version 2) as
  13  *  published by the Free Software Foundation.
  14  *
  15  *  This program is distributed in the hope it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  18  *  for more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License along
  21  *  with this program; if not, write to the Free Software Foundation, Inc.,
  22  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  23  *
  24  * ########################################################################
  25  *
  26  * Setting up the clock on the MIPS boards.
  27  *
  28  * Update.  Always configure the kernel with CONFIG_NEW_TIME_C.  This
  29  * will use the user interface gettimeofday() functions from the
  30  * arch/mips/kernel/time.c, and we provide the clock interrupt processing
  31  * and the timer offset compute functions.  If CONFIG_PM is selected,
  32  * we also ensure the 32KHz timer is available.   -- Dan
  33  */
  34
  35 #include <linux/types.h>
  36 #include <linux/init.h>
  37 #include <linux/kernel_stat.h>
  38 #include <linux/sched.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/hardirq.h>
  41
  42 #include <asm/compiler.h>
  43 #include <asm/mipsregs.h>
  44 #include <asm/time.h>
  45 #include <asm/div64.h>
  46 #include <asm/mach-au1x00/au1000.h>
  47
  48 #include <linux/mc146818rtc.h>
  49 #include <linux/timex.h>
  50
  51 static unsigned long r4k_offset; /* Amount to increment compare reg each time */
  52 static unsigned long r4k_cur;    /* What counter should be at next timer irq */
  53 int     no_au1xxx_32khz;
  54 extern int allow_au1k_wait; /* default off for CP0 Counter */
  55
  56 #ifdef CONFIG_PM
  57 #if HZ < 100 || HZ > 1000
  58 #error "unsupported HZ value! Must be in [100,1000]"
  59 #endif
  60 #define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */
  61 extern void startup_match20_interrupt(irq_handler_t handler);
  62 static unsigned long last_pc0, last_match20;
  63 #endif
  64
  65 static DEFINE_SPINLOCK(time_lock);
  66
  67 unsigned long wtimer;
  68
  69 #ifdef CONFIG_PM
  70 static irqreturn_t counter0_irq(int irq, void *dev_id)
  71 {
  72         unsigned long pc0;
  73         int time_elapsed;
  74         static int jiffie_drift = 0;
  75
  76         if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
  77                 /* should never happen! */
  78                 printk(KERN_WARNING "counter 0 w status error\n");
  79                 return IRQ_NONE;
  80         }
  81
  82         pc0 = au_readl(SYS_TOYREAD);
  83         if (pc0 < last_match20) {
  84                 /* counter overflowed */
  85                 time_elapsed = (0xffffffff - last_match20) + pc0;
  86         }
  87         else {
  88                 time_elapsed = pc0 - last_match20;
  89         }
  90
  91         while (time_elapsed > 0) {
  92                 do_timer(1);
  93 #ifndef CONFIG_SMP
  94                 update_process_times(user_mode(get_irq_regs()));
  95 #endif
  96                 time_elapsed -= MATCH20_INC;
  97                 last_match20 += MATCH20_INC;
  98                 jiffie_drift++;
  99         }
 100
 101         last_pc0 = pc0;
 102         au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
 103         au_sync();
 104
 105         /* our counter ticks at 10.009765625 ms/tick, we we're running
 106          * almost 10uS too slow per tick.
 107          */
 108
 109         if (jiffie_drift >= 999) {
 110                 jiffie_drift -= 999;
 111                 do_timer(1); /* increment jiffies by one */
 112 #ifndef CONFIG_SMP
 113                 update_process_times(user_mode(get_irq_regs()));
 114 #endif
 115         }
 116
 117         return IRQ_HANDLED;
 118 }
 119
 120 struct irqaction counter0_action = {
 121         .handler        = counter0_irq,
 122         .flags          = IRQF_DISABLED,
 123         .name           = "alchemy-toy",
 124         .dev_id         = NULL,
 125 };
 126
 127 /* When we wakeup from sleep, we have to "catch up" on all of the
 128  * timer ticks we have missed.
 129  */
 130 void
 131 wakeup_counter0_adjust(void)
 132 {
 133         unsigned long pc0;
 134         int time_elapsed;
 135
 136         pc0 = au_readl(SYS_TOYREAD);
 137         if (pc0 < last_match20) {
 138                 /* counter overflowed */
 139                 time_elapsed = (0xffffffff - last_match20) + pc0;
 140         }
 141         else {
 142                 time_elapsed = pc0 - last_match20;
 143         }
 144
 145         while (time_elapsed > 0) {
 146                 time_elapsed -= MATCH20_INC;
 147                 last_match20 += MATCH20_INC;
 148         }
 149
 150         last_pc0 = pc0;
 151         au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
 152         au_sync();
 153
 154 }
 155
 156 /* This is just for debugging to set the timer for a sleep delay.
 157 */
 158 void
 159 wakeup_counter0_set(int ticks)
 160 {
 161         unsigned long pc0;
 162
 163         pc0 = au_readl(SYS_TOYREAD);
 164         last_pc0 = pc0;
 165         au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2);
 166         au_sync();
 167 }
 168 #endif
 169
 170 /* I haven't found anyone that doesn't use a 12 MHz source clock,
 171  * but just in case.....
 172  */
 173 #define AU1000_SRC_CLK  12000000
 174
 175 /*
 176  * We read the real processor speed from the PLL.  This is important
 177  * because it is more accurate than computing it from the 32KHz
 178  * counter, if it exists.  If we don't have an accurate processor
 179  * speed, all of the peripherals that derive their clocks based on
 180  * this advertised speed will introduce error and sometimes not work
 181  * properly.  This function is futher convoluted to still allow configurations
 182  * to do that in case they have really, really old silicon with a
 183  * write-only PLL register, that we need the 32KHz when power management
 184  * "wait" is enabled, and we need to detect if the 32KHz isn't present
 185  * but requested......got it? :-)               -- Dan
 186  */
 187 unsigned long cal_r4koff(void)
 188 {
 189         unsigned long cpu_speed;
 190         unsigned long flags;
 191         unsigned long counter;
 192
 193         spin_lock_irqsave(&time_lock, flags);
 194
 195         /* Power management cares if we don't have a 32KHz counter.
 196         */
 197         no_au1xxx_32khz = 0;
 198         counter = au_readl(SYS_COUNTER_CNTRL);
 199         if (counter & SYS_CNTRL_E0) {
 200                 int trim_divide = 16;
 201
 202                 au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
 203
 204                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
 205                 /* RTC now ticks at 32.768/16 kHz */
 206                 au_writel(trim_divide-1, SYS_RTCTRIM);
 207                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
 208
 209                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
 210                 au_writel(0, SYS_TOYWRITE);
 211                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
 212         } else
 213                 no_au1xxx_32khz = 1;
 214
 215         /*
 216          * On early Au1000, sys_cpupll was write-only. Since these
 217          * silicon versions of Au1000 are not sold by AMD, we don't bend
 218          * over backwards trying to determine the frequency.
 219          */
 220         if (cur_cpu_spec[0]->cpu_pll_wo)
 221 #ifdef CONFIG_SOC_AU1000_FREQUENCY
 222                 cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
 223 #else
 224                 cpu_speed = 396000000;
 225 #endif
 226         else
 227                 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
 228         mips_hpt_frequency = cpu_speed;
 229         // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
 230         set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
 231         spin_unlock_irqrestore(&time_lock, flags);
 232         return (cpu_speed / HZ);
 233 }
 234
 235 void __init plat_time_init(void)
 236 {
 237         unsigned int est_freq;
 238
 239         printk("calculating r4koff... ");
 240         r4k_offset = cal_r4koff();
 241         printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
 242
 243         //est_freq = 2*r4k_offset*HZ;
 244         est_freq = r4k_offset*HZ;
 245         est_freq += 5000;    /* round */
 246         est_freq -= est_freq%10000;
 247         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 248                (est_freq%1000000)*100/1000000);
 249         set_au1x00_speed(est_freq);
 250         set_au1x00_lcd_clock(); // program the LCD clock
 251
 252         r4k_cur = (read_c0_count() + r4k_offset);
 253         write_c0_compare(r4k_cur);
 254
 255 #ifdef CONFIG_PM
 256         /*
 257          * setup counter 0, since it keeps ticking after a
 258          * 'wait' instruction has been executed. The CP0 timer and
 259          * counter 1 do NOT continue running after 'wait'
 260          *
 261          * It's too early to call request_irq() here, so we handle
 262          * counter 0 interrupt as a special irq and it doesn't show
 263          * up under /proc/interrupts.
 264          *
 265          * Check to ensure we really have a 32KHz oscillator before
 266          * we do this.
 267          */
 268         if (no_au1xxx_32khz) {
 269                 printk("WARNING: no 32KHz clock found.\n");
 270
 271                 /* Ensure we get CPO_COUNTER interrupts.  */
 272                 set_c0_status(IE_IRQ5);
 273         }
 274         else {
 275                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
 276                 au_writel(0, SYS_TOYWRITE);
 277                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
 278
 279                 au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
 280                 au_writel(~0, SYS_WAKESRC);
 281                 au_sync();
 282                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
 283
 284                 /* setup match20 to interrupt once every HZ */
 285                 last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
 286                 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
 287                 au_sync();
 288                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
 289                 setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action);
 290
 291                 /* We can use the real 'wait' instruction.
 292                 */
 293                 allow_au1k_wait = 1;
 294         }
 295
 296 #endif
 297 }