arch/mips/kernel/i8253.c

   1 /*
   2  * i8253.c  8253/PIT functions
   3  *
   4  */
   5 #include <linux/clockchips.h>
   6 #include <linux/init.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/jiffies.h>
   9 #include <linux/module.h>
  10 #include <linux/spinlock.h>
  11
  12 #include <asm/delay.h>
  13 #include <asm/i8253.h>
  14 #include <asm/io.h>
  15 #include <asm/time.h>
  16
  17 DEFINE_SPINLOCK(i8253_lock);
  18 EXPORT_SYMBOL(i8253_lock);
  19
  20 /*
  21  * Initialize the PIT timer.
  22  *
  23  * This is also called after resume to bring the PIT into operation again.
  24  */
  25 static void init_pit_timer(enum clock_event_mode mode,
  26                            struct clock_event_device *evt)
  27 {
  28         spin_lock(&i8253_lock);
  29
  30         switch(mode) {
  31         case CLOCK_EVT_MODE_PERIODIC:
  32                 /* binary, mode 2, LSB/MSB, ch 0 */
  33                 outb_p(0x34, PIT_MODE);
  34                 outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
  35                 outb(LATCH >> 8 , PIT_CH0);     /* MSB */
  36                 break;
  37
  38         case CLOCK_EVT_MODE_SHUTDOWN:
  39         case CLOCK_EVT_MODE_UNUSED:
  40                 if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
  41                     evt->mode == CLOCK_EVT_MODE_ONESHOT) {
  42                         outb_p(0x30, PIT_MODE);
  43                         outb_p(0, PIT_CH0);
  44                         outb_p(0, PIT_CH0);
  45                 }
  46                 break;
  47
  48         case CLOCK_EVT_MODE_ONESHOT:
  49                 /* One shot setup */
  50                 outb_p(0x38, PIT_MODE);
  51                 break;
  52
  53         case CLOCK_EVT_MODE_RESUME:
  54                 /* Nothing to do here */
  55                 break;
  56         }
  57         spin_unlock(&i8253_lock);
  58 }
  59
  60 /*
  61  * Program the next event in oneshot mode
  62  *
  63  * Delta is given in PIT ticks
  64  */
  65 static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
  66 {
  67         spin_lock(&i8253_lock);
  68         outb_p(delta & 0xff , PIT_CH0); /* LSB */
  69         outb(delta >> 8 , PIT_CH0);     /* MSB */
  70         spin_unlock(&i8253_lock);
  71
  72         return 0;
  73 }
  74
  75 /*
  76  * On UP the PIT can serve all of the possible timer functions. On SMP systems
  77  * it can be solely used for the global tick.
  78  *
  79  * The profiling and update capabilites are switched off once the local apic is
  80  * registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
  81  * !using_apic_timer decisions in do_timer_interrupt_hook()
  82  */
  83 struct clock_event_device pit_clockevent = {
  84         .name           = "pit",
  85         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  86         .set_mode       = init_pit_timer,
  87         .set_next_event = pit_next_event,
  88         .irq            = 0,
  89 };
  90
  91 static irqreturn_t timer_interrupt(int irq, void *dev_id)
  92 {
  93         pit_clockevent.event_handler(&pit_clockevent);
  94
  95         return IRQ_HANDLED;
  96 }
  97
  98 static struct irqaction irq0  = {
  99         .handler = timer_interrupt,
 100         .flags = IRQF_DISABLED | IRQF_NOBALANCING,
 101         .mask = CPU_MASK_NONE,
 102         .name = "timer"
 103 };
 104
 105 /*
 106  * Initialize the conversion factor and the min/max deltas of the clock event
 107  * structure and register the clock event source with the framework.
 108  */
 109 void __init setup_pit_timer(void)
 110 {
 111         struct clock_event_device *cd = &pit_clockevent;
 112         unsigned int cpu = smp_processor_id();
 113
 114         /*
 115          * Start pit with the boot cpu mask and make it global after the
 116          * IO_APIC has been initialized.
 117          */
 118         cd->cpumask = cpumask_of_cpu(cpu);
 119         clockevent_set_clock(cd, CLOCK_TICK_RATE);
 120         cd->max_delta_ns = clockevent_delta2ns(0x7FFF, cd);
 121         cd->min_delta_ns = clockevent_delta2ns(0xF, cd);
 122         clockevents_register_device(cd);
 123
 124         irq0.mask = cpumask_of_cpu(cpu);
 125         setup_irq(0, &irq0);
 126 }
 127
 128 /*
 129  * Since the PIT overflows every tick, its not very useful
 130  * to just read by itself. So use jiffies to emulate a free
 131  * running counter:
 132  */
 133 static cycle_t pit_read(void)
 134 {
 135         unsigned long flags;
 136         int count;
 137         u32 jifs;
 138         static int old_count;
 139         static u32 old_jifs;
 140
 141         spin_lock_irqsave(&i8253_lock, flags);
 142         /*
 143          * Although our caller may have the read side of xtime_lock,
 144          * this is now a seqlock, and we are cheating in this routine
 145          * by having side effects on state that we cannot undo if
 146          * there is a collision on the seqlock and our caller has to
 147          * retry.  (Namely, old_jifs and old_count.)  So we must treat
 148          * jiffies as volatile despite the lock.  We read jiffies
 149          * before latching the timer count to guarantee that although
 150          * the jiffies value might be older than the count (that is,
 151          * the counter may underflow between the last point where
 152          * jiffies was incremented and the point where we latch the
 153          * count), it cannot be newer.
 154          */
 155         jifs = jiffies;
 156         outb_p(0x00, PIT_MODE); /* latch the count ASAP */
 157         count = inb_p(PIT_CH0); /* read the latched count */
 158         count |= inb_p(PIT_CH0) << 8;
 159
 160         /* VIA686a test code... reset the latch if count > max + 1 */
 161         if (count > LATCH) {
 162                 outb_p(0x34, PIT_MODE);
 163                 outb_p(LATCH & 0xff, PIT_CH0);
 164                 outb(LATCH >> 8, PIT_CH0);
 165                 count = LATCH - 1;
 166         }
 167
 168         /*
 169          * It's possible for count to appear to go the wrong way for a
 170          * couple of reasons:
 171          *
 172          *  1. The timer counter underflows, but we haven't handled the
 173          *     resulting interrupt and incremented jiffies yet.
 174          *  2. Hardware problem with the timer, not giving us continuous time,
 175          *     the counter does small "jumps" upwards on some Pentium systems,
 176          *     (see c't 95/10 page 335 for Neptun bug.)
 177          *
 178          * Previous attempts to handle these cases intelligently were
 179          * buggy, so we just do the simple thing now.
 180          */
 181         if (count > old_count && jifs == old_jifs) {
 182                 count = old_count;
 183         }
 184         old_count = count;
 185         old_jifs = jifs;
 186
 187         spin_unlock_irqrestore(&i8253_lock, flags);
 188
 189         count = (LATCH - 1) - count;
 190
 191         return (cycle_t)(jifs * LATCH) + count;
 192 }
 193
 194 static struct clocksource clocksource_pit = {
 195         .name   = "pit",
 196         .rating = 110,
 197         .read   = pit_read,
 198         .mask   = CLOCKSOURCE_MASK(32),
 199         .mult   = 0,
 200         .shift  = 20,
 201 };
 202
 203 static int __init init_pit_clocksource(void)
 204 {
 205         if (num_possible_cpus() > 1) /* PIT does not scale! */
 206                 return 0;
 207
 208         clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20);
 209         return clocksource_register(&clocksource_pit);
 210 }
 211 arch_initcall(init_pit_clocksource);