arch/mips/sgi-ip27/ip27-nmi.c

   1 #include <linux/kallsyms.h>
   2 #include <linux/kernel.h>
   3 #include <linux/mmzone.h>
   4 #include <linux/nodemask.h>
   5 #include <linux/spinlock.h>
   6 #include <linux/smp.h>
   7 #include <asm/atomic.h>
   8 #include <asm/sn/types.h>
   9 #include <asm/sn/addrs.h>
  10 #include <asm/sn/nmi.h>
  11 #include <asm/sn/arch.h>
  12 #include <asm/sn/sn0/hub.h>
  13
  14 #if 0
  15 #define NODE_NUM_CPUS(n)        CNODE_NUM_CPUS(n)
  16 #else
  17 #define NODE_NUM_CPUS(n)        CPUS_PER_NODE
  18 #endif
  19
  20 #define CNODEID_NONE (cnodeid_t)-1
  21 #define enter_panic_mode()      spin_lock(&nmi_lock)
  22
  23 typedef unsigned long machreg_t;
  24
  25 DEFINE_SPINLOCK(nmi_lock);
  26
  27 /*
  28  * Lets see what else we need to do here. Set up sp, gp?
  29  */
  30 void nmi_dump(void)
  31 {
  32         void cont_nmi_dump(void);
  33
  34         cont_nmi_dump();
  35 }
  36
  37 void install_cpu_nmi_handler(int slice)
  38 {
  39         nmi_t *nmi_addr;
  40
  41         nmi_addr = (nmi_t *)NMI_ADDR(get_nasid(), slice);
  42         if (nmi_addr->call_addr)
  43                 return;
  44         nmi_addr->magic = NMI_MAGIC;
  45         nmi_addr->call_addr = (void *)nmi_dump;
  46         nmi_addr->call_addr_c =
  47                 (void *)(~((unsigned long)(nmi_addr->call_addr)));
  48         nmi_addr->call_parm = 0;
  49 }
  50
  51 /*
  52  * Copy the cpu registers which have been saved in the IP27prom format
  53  * into the eframe format for the node under consideration.
  54  */
  55
  56 void nmi_cpu_eframe_save(nasid_t nasid, int slice)
  57 {
  58         struct reg_struct *nr;
  59         int             i;
  60
  61         /* Get the pointer to the current cpu's register set. */
  62         nr = (struct reg_struct *)
  63                 (TO_UNCAC(TO_NODE(nasid, IP27_NMI_KREGS_OFFSET)) +
  64                 slice * IP27_NMI_KREGS_CPU_SIZE);
  65
  66         printk("NMI nasid %d: slice %d\n", nasid, slice);
  67
  68         /*
  69          * Saved main processor registers
  70          */
  71         for (i = 0; i < 32; ) {
  72                 if ((i % 4) == 0)
  73                         printk("$%2d   :", i);
  74                 printk(" %016lx", nr->gpr[i]);
  75
  76                 i++;
  77                 if ((i % 4) == 0)
  78                         printk("\n");
  79         }
  80
  81         printk("Hi    : (value lost)\n");
  82         printk("Lo    : (value lost)\n");
  83
  84         /*
  85          * Saved cp0 registers
  86          */
  87         printk("epc   : %016lx ", nr->epc);
  88         print_symbol("%s ", nr->epc);
  89         printk("%s\n", print_tainted());
  90         printk("ErrEPC: %016lx ", nr->error_epc);
  91         print_symbol("%s\n", nr->error_epc);
  92         printk("ra    : %016lx ", nr->gpr[31]);
  93         print_symbol("%s\n", nr->gpr[31]);
  94         printk("Status: %08lx         ", nr->sr);
  95
  96         if (nr->sr & ST0_KX)
  97                 printk("KX ");
  98         if (nr->sr & ST0_SX)
  99                 printk("SX      ");
 100         if (nr->sr & ST0_UX)
 101                 printk("UX ");
 102
 103         switch (nr->sr & ST0_KSU) {
 104         case KSU_USER:
 105                 printk("USER ");
 106                 break;
 107         case KSU_SUPERVISOR:
 108                 printk("SUPERVISOR ");
 109                 break;
 110         case KSU_KERNEL:
 111                 printk("KERNEL ");
 112                 break;
 113         default:
 114                 printk("BAD_MODE ");
 115                 break;
 116         }
 117
 118         if (nr->sr & ST0_ERL)
 119                 printk("ERL ");
 120         if (nr->sr & ST0_EXL)
 121                 printk("EXL ");
 122         if (nr->sr & ST0_IE)
 123                 printk("IE ");
 124         printk("\n");
 125
 126         printk("Cause : %08lx\n", nr->cause);
 127         printk("PrId  : %08x\n", read_c0_prid());
 128         printk("BadVA : %016lx\n", nr->badva);
 129         printk("CErr  : %016lx\n", nr->cache_err);
 130         printk("NMI_SR: %016lx\n", nr->nmi_sr);
 131
 132         printk("\n");
 133 }
 134
 135 void nmi_dump_hub_irq(nasid_t nasid, int slice)
 136 {
 137         hubreg_t mask0, mask1, pend0, pend1;
 138
 139         if (slice == 0) {                               /* Slice A */
 140                 mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_A);
 141                 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A);
 142         } else {                                        /* Slice B */
 143                 mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_B);
 144                 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B);
 145         }
 146
 147         pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0);
 148         pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1);
 149
 150         printk("PI_INT_MASK0: %16lx PI_INT_MASK1: %16lx\n", mask0, mask1);
 151         printk("PI_INT_PEND0: %16lx PI_INT_PEND1: %16lx\n", pend0, pend1);
 152         printk("\n\n");
 153 }
 154
 155 /*
 156  * Copy the cpu registers which have been saved in the IP27prom format
 157  * into the eframe format for the node under consideration.
 158  */
 159 void nmi_node_eframe_save(cnodeid_t  cnode)
 160 {
 161         nasid_t nasid;
 162         int slice;
 163
 164         /* Make sure that we have a valid node */
 165         if (cnode == CNODEID_NONE)
 166                 return;
 167
 168         nasid = COMPACT_TO_NASID_NODEID(cnode);
 169         if (nasid == INVALID_NASID)
 170                 return;
 171
 172         /* Save the registers into eframe for each cpu */
 173         for (slice = 0; slice < NODE_NUM_CPUS(slice); slice++) {
 174                 nmi_cpu_eframe_save(nasid, slice);
 175                 nmi_dump_hub_irq(nasid, slice);
 176         }
 177 }
 178
 179 /*
 180  * Save the nmi cpu registers for all cpus in the system.
 181  */
 182 void
 183 nmi_eframes_save(void)
 184 {
 185         cnodeid_t       cnode;
 186
 187         for_each_online_node(cnode)
 188                 nmi_node_eframe_save(cnode);
 189 }
 190
 191 void
 192 cont_nmi_dump(void)
 193 {
 194 #ifndef REAL_NMI_SIGNAL
 195         static atomic_t nmied_cpus = ATOMIC_INIT(0);
 196
 197         atomic_inc(&nmied_cpus);
 198 #endif
 199         /*
 200          * Use enter_panic_mode to allow only 1 cpu to proceed
 201          */
 202         enter_panic_mode();
 203
 204 #ifdef REAL_NMI_SIGNAL
 205         /*
 206          * Wait up to 15 seconds for the other cpus to respond to the NMI.
 207          * If a cpu has not responded after 10 sec, send it 1 additional NMI.
 208          * This is for 2 reasons:
 209          *      - sometimes a MMSC fail to NMI all cpus.
 210          *      - on 512p SN0 system, the MMSC will only send NMIs to
 211          *        half the cpus. Unfortunately, we don't know which cpus may be
 212          *        NMIed - it depends on how the site chooses to configure.
 213          *
 214          * Note: it has been measure that it takes the MMSC up to 2.3 secs to
 215          * send NMIs to all cpus on a 256p system.
 216          */
 217         for (i=0; i < 1500; i++) {
 218                 for_each_online_node(node)
 219                         if (NODEPDA(node)->dump_count == 0)
 220                                 break;
 221                 if (node == MAX_NUMNODES)
 222                         break;
 223                 if (i == 1000) {
 224                         for_each_online_node(node)
 225                                 if (NODEPDA(node)->dump_count == 0) {
 226                                         cpu = node_to_first_cpu(node);
 227                                         for (n=0; n < CNODE_NUM_CPUS(node); cpu++, n++) {
 228                                                 CPUMASK_SETB(nmied_cpus, cpu);
 229                                                 /*
 230                                                  * cputonasid, cputoslice
 231                                                  * needs kernel cpuid
 232                                                  */
 233                                                 SEND_NMI((cputonasid(cpu)), (cputoslice(cpu)));
 234                                         }
 235                                 }
 236
 237                 }
 238                 udelay(10000);
 239         }
 240 #else
 241         while (atomic_read(&nmied_cpus) != num_online_cpus());
 242 #endif
 243
 244         /*
 245          * Save the nmi cpu registers for all cpu in the eframe format.
 246          */
 247         nmi_eframes_save();
 248         LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET);
 249 }