2 * PCI Tower specific code
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/pci.h>
14 #include <linux/serial_8250.h>
18 #include <asm/irq_cpu.h>
21 #define PORT(_base,_irq) \
26 .iotype = UPIO_PORT, \
27 .flags = UPF_BOOT_AUTOCONF, \
30 static struct plat_serial8250_port pcit_data
[] = {
36 static struct platform_device pcit_serial8250_device
= {
38 .id
= PLAT8250_DEV_PLATFORM
,
40 .platform_data
= pcit_data
,
44 static struct plat_serial8250_port pcit_cplus_data
[] = {
52 static struct platform_device pcit_cplus_serial8250_device
= {
54 .id
= PLAT8250_DEV_PLATFORM
,
56 .platform_data
= pcit_cplus_data
,
60 static struct resource pcit_cmos_rsrc
[] = {
64 .flags
= IORESOURCE_IO
69 .flags
= IORESOURCE_IRQ
73 static struct platform_device pcit_cmos_device
= {
75 .num_resources
= ARRAY_SIZE(pcit_cmos_rsrc
),
76 .resource
= pcit_cmos_rsrc
79 static struct platform_device pcit_pcspeaker_pdev
= {
84 static struct resource sni_io_resource
= {
85 .start
= 0x00000000UL
,
88 .flags
= IORESOURCE_IO
,
91 static struct resource pcit_io_resources
[] = {
96 .flags
= IORESOURCE_BUSY
101 .flags
= IORESOURCE_BUSY
106 .flags
= IORESOURCE_BUSY
110 .name
= "dma page reg",
111 .flags
= IORESOURCE_BUSY
116 .flags
= IORESOURCE_BUSY
120 .name
= "PCI config addr",
121 .flags
= IORESOURCE_BUSY
125 .name
= "PCI config data",
126 .flags
= IORESOURCE_BUSY
130 static struct resource sni_mem_resource
= {
131 .start
= 0x18000000UL
,
133 .name
= "PCIT PCI MEM",
134 .flags
= IORESOURCE_MEM
137 static void __init
sni_pcit_resource_init(void)
141 /* request I/O space for devices used on all i[345]86 PCs */
142 for (i
= 0; i
< ARRAY_SIZE(pcit_io_resources
); i
++)
143 request_resource(&sni_io_resource
, pcit_io_resources
+ i
);
147 extern struct pci_ops sni_pcit_ops
;
149 static struct pci_controller sni_pcit_controller
= {
150 .pci_ops
= &sni_pcit_ops
,
151 .mem_resource
= &sni_mem_resource
,
152 .mem_offset
= 0x00000000UL
,
153 .io_resource
= &sni_io_resource
,
154 .io_offset
= 0x00000000UL
,
155 .io_map_base
= SNI_PORT_BASE
158 static void enable_pcit_irq(unsigned int irq
)
160 u32 mask
= 1 << (irq
- SNI_PCIT_INT_START
+ 24);
162 *(volatile u32
*)SNI_PCIT_INT_REG
|= mask
;
165 void disable_pcit_irq(unsigned int irq
)
167 u32 mask
= 1 << (irq
- SNI_PCIT_INT_START
+ 24);
169 *(volatile u32
*)SNI_PCIT_INT_REG
&= ~mask
;
172 void end_pcit_irq(unsigned int irq
)
174 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
|IRQ_INPROGRESS
)))
175 enable_pcit_irq(irq
);
178 static struct irq_chip pcit_irq_type
= {
180 .ack
= disable_pcit_irq
,
181 .mask
= disable_pcit_irq
,
182 .mask_ack
= disable_pcit_irq
,
183 .unmask
= enable_pcit_irq
,
187 static void pcit_hwint1(void)
189 u32 pending
= *(volatile u32
*)SNI_PCIT_INT_REG
;
192 clear_c0_status(IE_IRQ1
);
193 irq
= ffs((pending
>> 16) & 0x7f);
196 do_IRQ(irq
+ SNI_PCIT_INT_START
- 1);
197 set_c0_status(IE_IRQ1
);
200 static void pcit_hwint0(void)
202 u32 pending
= *(volatile u32
*)SNI_PCIT_INT_REG
;
205 clear_c0_status(IE_IRQ0
);
206 irq
= ffs((pending
>> 16) & 0x3f);
209 do_IRQ(irq
+ SNI_PCIT_INT_START
- 1);
210 set_c0_status(IE_IRQ0
);
213 static void sni_pcit_hwint(void)
215 u32 pending
= read_c0_cause() & read_c0_status();
217 if (pending
& C_IRQ1
)
219 else if (pending
& C_IRQ2
)
220 do_IRQ(MIPS_CPU_IRQ_BASE
+ 4);
221 else if (pending
& C_IRQ3
)
222 do_IRQ(MIPS_CPU_IRQ_BASE
+ 5);
223 else if (pending
& C_IRQ5
)
224 do_IRQ(MIPS_CPU_IRQ_BASE
+ 7);
227 static void sni_pcit_hwint_cplus(void)
229 u32 pending
= read_c0_cause() & read_c0_status();
231 if (pending
& C_IRQ0
)
233 else if (pending
& C_IRQ1
)
234 do_IRQ(MIPS_CPU_IRQ_BASE
+ 3);
235 else if (pending
& C_IRQ2
)
236 do_IRQ(MIPS_CPU_IRQ_BASE
+ 4);
237 else if (pending
& C_IRQ3
)
238 do_IRQ(MIPS_CPU_IRQ_BASE
+ 5);
239 else if (pending
& C_IRQ5
)
240 do_IRQ(MIPS_CPU_IRQ_BASE
+ 7);
243 void __init
sni_pcit_irq_init(void)
248 for (i
= SNI_PCIT_INT_START
; i
<= SNI_PCIT_INT_END
; i
++)
249 set_irq_chip(i
, &pcit_irq_type
);
250 *(volatile u32
*)SNI_PCIT_INT_REG
= 0;
251 sni_hwint
= sni_pcit_hwint
;
252 change_c0_status(ST0_IM
, IE_IRQ1
);
253 setup_irq(SNI_PCIT_INT_START
+ 6, &sni_isa_irq
);
256 void __init
sni_pcit_cplus_irq_init(void)
261 for (i
= SNI_PCIT_INT_START
; i
<= SNI_PCIT_INT_END
; i
++)
262 set_irq_chip(i
, &pcit_irq_type
);
263 *(volatile u32
*)SNI_PCIT_INT_REG
= 0x40000000;
264 sni_hwint
= sni_pcit_hwint_cplus
;
265 change_c0_status(ST0_IM
, IE_IRQ0
);
266 setup_irq(MIPS_CPU_IRQ_BASE
+ 3, &sni_isa_irq
);
269 void __init
sni_pcit_init(void)
271 ioport_resource
.end
= sni_io_resource
.end
;
273 PCIBIOS_MIN_IO
= 0x9000;
274 register_pci_controller(&sni_pcit_controller
);
276 sni_pcit_resource_init();
279 static int __init
snirm_pcit_setup_devinit(void)
281 switch (sni_brd_type
) {
282 case SNI_BRD_PCI_TOWER
:
283 platform_device_register(&pcit_serial8250_device
);
284 platform_device_register(&pcit_cmos_device
);
285 platform_device_register(&pcit_pcspeaker_pdev
);
288 case SNI_BRD_PCI_TOWER_CPLUS
:
289 platform_device_register(&pcit_cplus_serial8250_device
);
290 platform_device_register(&pcit_cmos_device
);
291 platform_device_register(&pcit_pcspeaker_pdev
);
297 device_initcall(snirm_pcit_setup_devinit
);