1 #ifndef __ASM_ARCH_REGS_SSP_H
2 #define __ASM_ARCH_REGS_SSP_H
5 * SSP Serial Port Registers
6 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
7 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
10 #define SSCR0 (0x00) /* SSP Control Register 0 */
11 #define SSCR1 (0x04) /* SSP Control Register 1 */
12 #define SSSR (0x08) /* SSP Status Register */
13 #define SSITR (0x0C) /* SSP Interrupt Test Register */
14 #define SSDR (0x10) /* SSP Data Write/Data Read Register */
16 #define SSTO (0x28) /* SSP Time Out Register */
17 #define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
18 #define SSTSA (0x30) /* SSP Tx Timeslot Active */
19 #define SSRSA (0x34) /* SSP Rx Timeslot Active */
20 #define SSTSS (0x38) /* SSP Timeslot Status */
21 #define SSACD (0x3C) /* SSP Audio Clock Divider */
23 /* Common PXA2xx bits first */
24 #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
25 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
26 #define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
27 #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
28 #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
29 #define SSCR0_National (0x2 << 4) /* National Microwire */
30 #define SSCR0_ECS (1 << 6) /* External clock select */
31 #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
32 #if defined(CONFIG_PXA25x)
33 #define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
34 #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
35 #elif defined(CONFIG_PXA27x)
36 #define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
37 #define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
38 #define SSCR0_EDSS (1 << 20) /* Extended data size select */
39 #define SSCR0_NCS (1 << 21) /* Network clock select */
40 #define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
41 #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
42 #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
43 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
44 #define SSCR0_ADC (1 << 30) /* Audio clock select */
45 #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
48 #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
49 #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
50 #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
51 #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
52 #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
53 #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
54 #define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
55 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
56 #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
57 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
59 #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
60 #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
61 #define SSSR_BSY (1 << 4) /* SSP Busy */
62 #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
63 #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
64 #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
66 #define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
67 #define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
68 #define SSCR0_NCS (1 << 21) /* Network Clock Select */
69 #define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
71 /* extra bits in PXA255, PXA26x and PXA27x SSP ports */
72 #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
73 #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
74 #define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
75 #define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
76 #define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
77 #define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
78 #define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
79 #define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
80 #define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
81 #define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
82 #define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
83 #define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
84 #define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
85 #define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
86 #define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
87 #define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
88 #define SSCR1_IFS (1 << 16) /* Invert Frame Signal */
89 #define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
90 #define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
92 #define SSSR_BCE (1 << 23) /* Bit Count Error */
93 #define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
94 #define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
95 #define SSSR_EOC (1 << 20) /* End Of Chain */
96 #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
97 #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
99 #define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
100 #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
101 #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
102 #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
103 #define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
104 #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
105 #define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
106 #define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
107 #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
109 #define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
110 #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
111 #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
113 #endif /* __ASM_ARCH_REGS_SSP_H */
