include/asm-arm/arch-realview/board-eb.h

   1 /*
   2  * include/asm-arm/arch-realview/board-eb.h
   3  *
   4  * Copyright (C) 2007 ARM Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  18  * MA 02110-1301, USA.
  19  */
  20
  21 #ifndef __ASM_ARCH_BOARD_EB_H
  22 #define __ASM_ARCH_BOARD_EB_H
  23
  24 #include <asm/arch/platform.h>
  25
  26 /*
  27  * RealView EB + ARM11MPCore peripheral addresses
  28  */
  29 #ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
  30 #define REALVIEW_EB11MP_SCU_BASE        0x10100000      /* SCU registers */
  31 #define REALVIEW_EB11MP_GIC_CPU_BASE    0x10100100      /* Generic interrupt controller CPU interface */
  32 #define REALVIEW_EB11MP_TWD_BASE        0x10100700
  33 #define REALVIEW_EB11MP_TWD_SIZE        0x00000100
  34 #define REALVIEW_EB11MP_GIC_DIST_BASE   0x10101000      /* Generic interrupt controller distributor */
  35 #define REALVIEW_EB11MP_L220_BASE       0x10102000      /* L220 registers */
  36 #define REALVIEW_EB11MP_SYS_PLD_CTRL1   0xD8            /* Register offset for MPCore sysctl */
  37 #else
  38 #define REALVIEW_EB11MP_SCU_BASE        0x1F000000      /* SCU registers */
  39 #define REALVIEW_EB11MP_GIC_CPU_BASE    0x1F000100      /* Generic interrupt controller CPU interface */
  40 #define REALVIEW_EB11MP_TWD_BASE        0x1F000700
  41 #define REALVIEW_EB11MP_TWD_SIZE        0x00000100
  42 #define REALVIEW_EB11MP_GIC_DIST_BASE   0x1F001000      /* Generic interrupt controller distributor */
  43 #define REALVIEW_EB11MP_L220_BASE       0x1F002000      /* L220 registers */
  44 #define REALVIEW_EB11MP_SYS_PLD_CTRL1   0x74            /* Register offset for MPCore sysctl */
  45 #endif
  46
  47 #define IRQ_EB_GIC_START        32
  48
  49 /*
  50  * RealView EB interrupt sources
  51  */
  52 #define IRQ_EB_WDOG             (IRQ_EB_GIC_START + 0)          /* Watchdog timer */
  53 #define IRQ_EB_SOFT             (IRQ_EB_GIC_START + 1)          /* Software interrupt */
  54 #define IRQ_EB_COMMRx           (IRQ_EB_GIC_START + 2)          /* Debug Comm Rx interrupt */
  55 #define IRQ_EB_COMMTx           (IRQ_EB_GIC_START + 3)          /* Debug Comm Tx interrupt */
  56 #define IRQ_EB_TIMER0_1         (IRQ_EB_GIC_START + 4)          /* Timer 0 and 1 */
  57 #define IRQ_EB_TIMER2_3         (IRQ_EB_GIC_START + 5)          /* Timer 2 and 3 */
  58 #define IRQ_EB_GPIO0            (IRQ_EB_GIC_START + 6)          /* GPIO 0 */
  59 #define IRQ_EB_GPIO1            (IRQ_EB_GIC_START + 7)          /* GPIO 1 */
  60 #define IRQ_EB_GPIO2            (IRQ_EB_GIC_START + 8)          /* GPIO 2 */
  61                                                                 /* 9 reserved */
  62 #define IRQ_EB_RTC              (IRQ_EB_GIC_START + 10)         /* Real Time Clock */
  63 #define IRQ_EB_SSP              (IRQ_EB_GIC_START + 11)         /* Synchronous Serial Port */
  64 #define IRQ_EB_UART0            (IRQ_EB_GIC_START + 12)         /* UART 0 on development chip */
  65 #define IRQ_EB_UART1            (IRQ_EB_GIC_START + 13)         /* UART 1 on development chip */
  66 #define IRQ_EB_UART2            (IRQ_EB_GIC_START + 14)         /* UART 2 on development chip */
  67 #define IRQ_EB_UART3            (IRQ_EB_GIC_START + 15)         /* UART 3 on development chip */
  68 #define IRQ_EB_SCI              (IRQ_EB_GIC_START + 16)         /* Smart Card Interface */
  69 #define IRQ_EB_MMCI0A           (IRQ_EB_GIC_START + 17)         /* Multimedia Card 0A */
  70 #define IRQ_EB_MMCI0B           (IRQ_EB_GIC_START + 18)         /* Multimedia Card 0B */
  71 #define IRQ_EB_AACI             (IRQ_EB_GIC_START + 19)         /* Audio Codec */
  72 #define IRQ_EB_KMI0             (IRQ_EB_GIC_START + 20)         /* Keyboard/Mouse port 0 */
  73 #define IRQ_EB_KMI1             (IRQ_EB_GIC_START + 21)         /* Keyboard/Mouse port 1 */
  74 #define IRQ_EB_CHARLCD          (IRQ_EB_GIC_START + 22)         /* Character LCD */
  75 #define IRQ_EB_CLCD             (IRQ_EB_GIC_START + 23)         /* CLCD controller */
  76 #define IRQ_EB_DMA              (IRQ_EB_GIC_START + 24)         /* DMA controller */
  77 #define IRQ_EB_PWRFAIL          (IRQ_EB_GIC_START + 25)         /* Power failure */
  78 #define IRQ_EB_PISMO            (IRQ_EB_GIC_START + 26)         /* PISMO interface */
  79 #define IRQ_EB_DoC              (IRQ_EB_GIC_START + 27)         /* Disk on Chip memory controller */
  80 #define IRQ_EB_ETH              (IRQ_EB_GIC_START + 28)         /* Ethernet controller */
  81 #define IRQ_EB_USB              (IRQ_EB_GIC_START + 29)         /* USB controller */
  82 #define IRQ_EB_TSPEN            (IRQ_EB_GIC_START + 30)         /* Touchscreen pen */
  83 #define IRQ_EB_TSKPAD           (IRQ_EB_GIC_START + 31)         /* Touchscreen keypad */
  84
  85 /*
  86  * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
  87  */
  88 #define IRQ_EB11MP_AACI         (IRQ_EB_GIC_START + 0)
  89 #define IRQ_EB11MP_TIMER0_1     (IRQ_EB_GIC_START + 1)
  90 #define IRQ_EB11MP_TIMER2_3     (IRQ_EB_GIC_START + 2)
  91 #define IRQ_EB11MP_USB          (IRQ_EB_GIC_START + 3)
  92 #define IRQ_EB11MP_UART0        (IRQ_EB_GIC_START + 4)
  93 #define IRQ_EB11MP_UART1        (IRQ_EB_GIC_START + 5)
  94 #define IRQ_EB11MP_RTC          (IRQ_EB_GIC_START + 6)
  95 #define IRQ_EB11MP_KMI0         (IRQ_EB_GIC_START + 7)
  96 #define IRQ_EB11MP_KMI1         (IRQ_EB_GIC_START + 8)
  97 #define IRQ_EB11MP_ETH          (IRQ_EB_GIC_START + 9)
  98 #define IRQ_EB11MP_EB_IRQ1      (IRQ_EB_GIC_START + 10)         /* main GIC */
  99 #define IRQ_EB11MP_EB_IRQ2      (IRQ_EB_GIC_START + 11)         /* tile GIC */
 100 #define IRQ_EB11MP_EB_FIQ1      (IRQ_EB_GIC_START + 12)         /* main GIC */
 101 #define IRQ_EB11MP_EB_FIQ2      (IRQ_EB_GIC_START + 13)         /* tile GIC */
 102 #define IRQ_EB11MP_MMCI0A       (IRQ_EB_GIC_START + 14)
 103 #define IRQ_EB11MP_MMCI0B       (IRQ_EB_GIC_START + 15)
 104
 105 #define IRQ_EB11MP_PMU_CPU0     (IRQ_EB_GIC_START + 17)
 106 #define IRQ_EB11MP_PMU_CPU1     (IRQ_EB_GIC_START + 18)
 107 #define IRQ_EB11MP_PMU_CPU2     (IRQ_EB_GIC_START + 19)
 108 #define IRQ_EB11MP_PMU_CPU3     (IRQ_EB_GIC_START + 20)
 109 #define IRQ_EB11MP_PMU_SCU0     (IRQ_EB_GIC_START + 21)
 110 #define IRQ_EB11MP_PMU_SCU1     (IRQ_EB_GIC_START + 22)
 111 #define IRQ_EB11MP_PMU_SCU2     (IRQ_EB_GIC_START + 23)
 112 #define IRQ_EB11MP_PMU_SCU3     (IRQ_EB_GIC_START + 24)
 113 #define IRQ_EB11MP_PMU_SCU4     (IRQ_EB_GIC_START + 25)
 114 #define IRQ_EB11MP_PMU_SCU5     (IRQ_EB_GIC_START + 26)
 115 #define IRQ_EB11MP_PMU_SCU6     (IRQ_EB_GIC_START + 27)
 116 #define IRQ_EB11MP_PMU_SCU7     (IRQ_EB_GIC_START + 28)
 117
 118 #define IRQ_EB11MP_L220_EVENT   (IRQ_EB_GIC_START + 29)
 119 #define IRQ_EB11MP_L220_SLAVE   (IRQ_EB_GIC_START + 30)
 120 #define IRQ_EB11MP_L220_DECODE  (IRQ_EB_GIC_START + 31)
 121
 122 #define IRQ_EB11MP_UART2        -1
 123 #define IRQ_EB11MP_UART3        -1
 124 #define IRQ_EB11MP_CLCD         -1
 125 #define IRQ_EB11MP_DMA          -1
 126 #define IRQ_EB11MP_WDOG         -1
 127 #define IRQ_EB11MP_GPIO0        -1
 128 #define IRQ_EB11MP_GPIO1        -1
 129 #define IRQ_EB11MP_GPIO2        -1
 130 #define IRQ_EB11MP_SCI          -1
 131 #define IRQ_EB11MP_SSP          -1
 132
 133 #define NR_GIC_EB11MP           2
 134
 135 /*
 136  * Only define NR_IRQS if less than NR_IRQS_EB
 137  */
 138 #define NR_IRQS_EB              (IRQ_EB_GIC_START + 96)
 139
 140 #if defined(CONFIG_MACH_REALVIEW_EB) \
 141         && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
 142 #undef NR_IRQS
 143 #define NR_IRQS                 NR_IRQS_EB
 144 #endif
 145
 146 #if defined(CONFIG_REALVIEW_EB_ARM11MP) \
 147         && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP))
 148 #undef MAX_GIC_NR
 149 #define MAX_GIC_NR              NR_GIC_EB11MP
 150 #endif
 151
 152 /*
 153  * Core tile identification (REALVIEW_SYS_PROCID)
 154  */
 155 #define REALVIEW_EB_PROC_MASK           0xFF000000
 156 #define REALVIEW_EB_PROC_ARM7TDMI       0x00000000
 157 #define REALVIEW_EB_PROC_ARM9           0x02000000
 158 #define REALVIEW_EB_PROC_ARM11          0x04000000
 159 #define REALVIEW_EB_PROC_ARM11MP        0x06000000
 160
 161 #define check_eb_proc(proc_type)                                                \
 162         ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK)     \
 163          == proc_type)
 164
 165 #ifdef CONFIG_REALVIEW_EB_ARM11MP
 166 #define core_tile_eb11mp()      check_eb_proc(REALVIEW_EB_PROC_ARM11MP)
 167 #else
 168 #define core_tile_eb11mp()      0
 169 #endif
 170
 171 #endif  /* __ASM_ARCH_BOARD_EB_H */