| blob | 8d3228dc17784b7cd2c44a2158616c5b80c8e511 |
1 /*
2 * linux/include/asm-arm/hardware/clps7111.h
3 *
4 * This file contains the hardware definitions of the CLPS7111 internal
5 * registers.
6 *
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23 #ifndef __ASM_HARDWARE_CLPS7111_H
24 #define __ASM_HARDWARE_CLPS7111_H
26 #define CLPS7111_PHYS_BASE (0x80000000)
28 #ifndef __ASSEMBLY__
29 #define clps_readb(off) __raw_readb(CLPS7111_BASE + (off))
30 #define clps_readw(off) __raw_readw(CLPS7111_BASE + (off))
31 #define clps_readl(off) __raw_readl(CLPS7111_BASE + (off))
32 #define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off))
33 #define clps_writew(val,off) __raw_writew(val, CLPS7111_BASE + (off))
34 #define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off))
35 #endif
37 #define PADR (0x0000)
38 #define PBDR (0x0001)
39 #define PDDR (0x0003)
40 #define PADDR (0x0040)
41 #define PBDDR (0x0041)
42 #define PDDDR (0x0043)
43 #define PEDR (0x0080)
44 #define PEDDR (0x00c0)
45 #define SYSCON1 (0x0100)
46 #define SYSFLG1 (0x0140)
47 #define MEMCFG1 (0x0180)
48 #define MEMCFG2 (0x01c0)
49 #define DRFPR (0x0200)
50 #define INTSR1 (0x0240)
51 #define INTMR1 (0x0280)
52 #define LCDCON (0x02c0)
53 #define TC1D (0x0300)
54 #define TC2D (0x0340)
55 #define RTCDR (0x0380)
56 #define RTCMR (0x03c0)
57 #define PMPCON (0x0400)
58 #define CODR (0x0440)
59 #define UARTDR1 (0x0480)
60 #define UBRLCR1 (0x04c0)
61 #define SYNCIO (0x0500)
62 #define PALLSW (0x0540)
63 #define PALMSW (0x0580)
64 #define STFCLR (0x05c0)
65 #define BLEOI (0x0600)
66 #define MCEOI (0x0640)
67 #define TEOI (0x0680)
68 #define TC1EOI (0x06c0)
69 #define TC2EOI (0x0700)
70 #define RTCEOI (0x0740)
71 #define UMSEOI (0x0780)
72 #define COEOI (0x07c0)
73 #define HALT (0x0800)
74 #define STDBY (0x0840)
76 #define FBADDR (0x1000)
77 #define SYSCON2 (0x1100)
78 #define SYSFLG2 (0x1140)
79 #define INTSR2 (0x1240)
80 #define INTMR2 (0x1280)
81 #define UARTDR2 (0x1480)
82 #define UBRLCR2 (0x14c0)
83 #define SS2DR (0x1500)
84 #define SRXEOF (0x1600)
85 #define SS2POP (0x16c0)
86 #define KBDEOI (0x1700)
88 /* common bits: SYSCON1 / SYSCON2 */
89 #define SYSCON_UARTEN (1 << 8)
91 #define SYSCON1_KBDSCAN(x) ((x) & 15)
92 #define SYSCON1_KBDSCANMASK (15)
93 #define SYSCON1_TC1M (1 << 4)
94 #define SYSCON1_TC1S (1 << 5)
95 #define SYSCON1_TC2M (1 << 6)
96 #define SYSCON1_TC2S (1 << 7)
97 #define SYSCON1_UART1EN SYSCON_UARTEN
98 #define SYSCON1_BZTOG (1 << 9)
99 #define SYSCON1_BZMOD (1 << 10)
100 #define SYSCON1_DBGEN (1 << 11)
101 #define SYSCON1_LCDEN (1 << 12)
102 #define SYSCON1_CDENTX (1 << 13)
103 #define SYSCON1_CDENRX (1 << 14)
104 #define SYSCON1_SIREN (1 << 15)
105 #define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
106 #define SYSCON1_ADCKSEL_MASK (3 << 16)
107 #define SYSCON1_EXCKEN (1 << 18)
108 #define SYSCON1_WAKEDIS (1 << 19)
109 #define SYSCON1_IRTXM (1 << 20)
111 /* common bits: SYSFLG1 / SYSFLG2 */
112 #define SYSFLG_UBUSY (1 << 11)
113 #define SYSFLG_URXFE (1 << 22)
114 #define SYSFLG_UTXFF (1 << 23)
116 #define SYSFLG1_MCDR (1 << 0)
117 #define SYSFLG1_DCDET (1 << 1)
118 #define SYSFLG1_WUDR (1 << 2)
119 #define SYSFLG1_WUON (1 << 3)
120 #define SYSFLG1_CTS (1 << 8)
121 #define SYSFLG1_DSR (1 << 9)
122 #define SYSFLG1_DCD (1 << 10)
123 #define SYSFLG1_UBUSY SYSFLG_UBUSY
124 #define SYSFLG1_NBFLG (1 << 12)
125 #define SYSFLG1_RSTFLG (1 << 13)
126 #define SYSFLG1_PFFLG (1 << 14)
127 #define SYSFLG1_CLDFLG (1 << 15)
128 #define SYSFLG1_URXFE SYSFLG_URXFE
129 #define SYSFLG1_UTXFF SYSFLG_UTXFF
130 #define SYSFLG1_CRXFE (1 << 24)
131 #define SYSFLG1_CTXFF (1 << 25)
132 #define SYSFLG1_SSIBUSY (1 << 26)
133 #define SYSFLG1_ID (1 << 29)
135 #define SYSFLG2_SSRXOF (1 << 0)
136 #define SYSFLG2_RESVAL (1 << 1)
137 #define SYSFLG2_RESFRM (1 << 2)
138 #define SYSFLG2_SS2RXFE (1 << 3)
139 #define SYSFLG2_SS2TXFF (1 << 4)
140 #define SYSFLG2_SS2TXUF (1 << 5)
141 #define SYSFLG2_CKMODE (1 << 6)
142 #define SYSFLG2_UBUSY SYSFLG_UBUSY
143 #define SYSFLG2_URXFE SYSFLG_URXFE
144 #define SYSFLG2_UTXFF SYSFLG_UTXFF
146 #define LCDCON_GSEN (1 << 30)
147 #define LCDCON_GSMD (1 << 31)
149 #define SYSCON2_SERSEL (1 << 0)
150 #define SYSCON2_KBD6 (1 << 1)
151 #define SYSCON2_DRAMZ (1 << 2)
152 #define SYSCON2_KBWEN (1 << 3)
153 #define SYSCON2_SS2TXEN (1 << 4)
154 #define SYSCON2_PCCARD1 (1 << 5)
155 #define SYSCON2_PCCARD2 (1 << 6)
156 #define SYSCON2_SS2RXEN (1 << 7)
157 #define SYSCON2_UART2EN SYSCON_UARTEN
158 #define SYSCON2_SS2MAEN (1 << 9)
159 #define SYSCON2_OSTB (1 << 12)
160 #define SYSCON2_CLKENSL (1 << 13)
161 #define SYSCON2_BUZFREQ (1 << 14)
163 /* common bits: UARTDR1 / UARTDR2 */
164 #define UARTDR_FRMERR (1 << 8)
165 #define UARTDR_PARERR (1 << 9)
166 #define UARTDR_OVERR (1 << 10)
168 /* common bits: UBRLCR1 / UBRLCR2 */
169 #define UBRLCR_BAUD_MASK ((1 << 12) - 1)
170 #define UBRLCR_BREAK (1 << 12)
171 #define UBRLCR_PRTEN (1 << 13)
172 #define UBRLCR_EVENPRT (1 << 14)
173 #define UBRLCR_XSTOP (1 << 15)
174 #define UBRLCR_FIFOEN (1 << 16)
175 #define UBRLCR_WRDLEN5 (0 << 17)
176 #define UBRLCR_WRDLEN6 (1 << 17)
177 #define UBRLCR_WRDLEN7 (2 << 17)
178 #define UBRLCR_WRDLEN8 (3 << 17)
179 #define UBRLCR_WRDLEN_MASK (3 << 17)
181 #define SYNCIO_SMCKEN (1 << 13)
182 #define SYNCIO_TXFRMEN (1 << 14)