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target/cxgbit: Use T6 specific macros to get ETH/IP hdr len
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
blob56f917ec8621e8d5d4a9410975ec454aa802414a
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
14 *
15 * XXX these should be marked initdata for multi-OMAP kernels
16 */
17
18 #include <linux/i2c-omap.h>
19 #include <linux/power/smartreflex.h>
20 #include <linux/platform_data/gpio-omap.h>
21 #include <linux/platform_data/hsmmc-omap.h>
22
23 #include <linux/omap-dma.h>
24 #include "l3_3xxx.h"
25 #include "l4_3xxx.h"
26 #include <linux/platform_data/asoc-ti-mcbsp.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <plat/dmtimer.h>
29
30 #include "soc.h"
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
33 #include "prm-regbits-34xx.h"
34 #include "cm-regbits-34xx.h"
35
36 #include "i2c.h"
37 #include "wd_timer.h"
38 #include "serial.h"
39
40 /*
41 * OMAP3xxx hardware module integration data
42 *
43 * All of the data in this section should be autogeneratable from the
44 * TI hardware database or other technical documentation. Data that
45 * is driver-specific or driver-kernel integration-specific belongs
46 * elsewhere.
47 */
48
49 #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
50
51 /*
52 * IP blocks
53 */
54
55 /* L3 */
56
57 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
58 .name = "l3_main",
59 .class = &l3_hwmod_class,
60 .flags = HWMOD_NO_IDLEST,
61 };
62
63 /* L4 CORE */
64 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
65 .name = "l4_core",
66 .class = &l4_hwmod_class,
67 .flags = HWMOD_NO_IDLEST,
68 };
69
70 /* L4 PER */
71 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
72 .name = "l4_per",
73 .class = &l4_hwmod_class,
74 .flags = HWMOD_NO_IDLEST,
75 };
76
77 /* L4 WKUP */
78 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
79 .name = "l4_wkup",
80 .class = &l4_hwmod_class,
81 .flags = HWMOD_NO_IDLEST,
82 };
83
84 /* L4 SEC */
85 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
86 .name = "l4_sec",
87 .class = &l4_hwmod_class,
88 .flags = HWMOD_NO_IDLEST,
89 };
90
91 /* MPU */
92
93 static struct omap_hwmod omap3xxx_mpu_hwmod = {
94 .name = "mpu",
95 .class = &mpu_hwmod_class,
96 .main_clk = "arm_fck",
97 };
98
99 /* IVA2 (IVA2) */
100 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
101 { .name = "logic", .rst_shift = 0, .st_shift = 8 },
102 { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
103 { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
104 };
105
106 static struct omap_hwmod omap3xxx_iva_hwmod = {
107 .name = "iva",
108 .class = &iva_hwmod_class,
109 .clkdm_name = "iva2_clkdm",
110 .rst_lines = omap3xxx_iva_resets,
111 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
112 .main_clk = "iva2_ck",
113 .prcm = {
114 .omap2 = {
115 .module_offs = OMAP3430_IVA2_MOD,
116 .prcm_reg_id = 1,
117 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
118 .idlest_reg_id = 1,
119 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
120 },
121 },
122 };
123
124 /*
125 * 'debugss' class
126 * debug and emulation sub system
127 */
128
129 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
130 .name = "debugss",
131 };
132
133 /* debugss */
134 static struct omap_hwmod omap3xxx_debugss_hwmod = {
135 .name = "debugss",
136 .class = &omap3xxx_debugss_hwmod_class,
137 .clkdm_name = "emu_clkdm",
138 .main_clk = "emu_src_ck",
139 .flags = HWMOD_NO_IDLEST,
140 };
141
142 /* timer class */
143 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
144 .rev_offs = 0x0000,
145 .sysc_offs = 0x0010,
146 .syss_offs = 0x0014,
147 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
148 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
149 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
150 SYSS_HAS_RESET_STATUS),
151 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
152 .clockact = CLOCKACT_TEST_ICLK,
153 .sysc_fields = &omap_hwmod_sysc_type1,
154 };
155
156 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
157 .name = "timer",
158 .sysc = &omap3xxx_timer_sysc,
159 };
160
161 /* secure timers dev attribute */
162 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
163 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
164 };
165
166 /* always-on timers dev attribute */
167 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
168 .timer_capability = OMAP_TIMER_ALWON,
169 };
170
171 /* pwm timers dev attribute */
172 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
173 .timer_capability = OMAP_TIMER_HAS_PWM,
174 };
175
176 /* timers with DSP interrupt dev attribute */
177 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
178 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
179 };
180
181 /* pwm timers with DSP interrupt dev attribute */
182 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
183 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
184 };
185
186 /* timer1 */
187 static struct omap_hwmod omap3xxx_timer1_hwmod = {
188 .name = "timer1",
189 .main_clk = "gpt1_fck",
190 .prcm = {
191 .omap2 = {
192 .prcm_reg_id = 1,
193 .module_bit = OMAP3430_EN_GPT1_SHIFT,
194 .module_offs = WKUP_MOD,
195 .idlest_reg_id = 1,
196 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
197 },
198 },
199 .dev_attr = &capability_alwon_dev_attr,
200 .class = &omap3xxx_timer_hwmod_class,
201 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
202 };
203
204 /* timer2 */
205 static struct omap_hwmod omap3xxx_timer2_hwmod = {
206 .name = "timer2",
207 .main_clk = "gpt2_fck",
208 .prcm = {
209 .omap2 = {
210 .prcm_reg_id = 1,
211 .module_bit = OMAP3430_EN_GPT2_SHIFT,
212 .module_offs = OMAP3430_PER_MOD,
213 .idlest_reg_id = 1,
214 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
215 },
216 },
217 .class = &omap3xxx_timer_hwmod_class,
218 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
219 };
220
221 /* timer3 */
222 static struct omap_hwmod omap3xxx_timer3_hwmod = {
223 .name = "timer3",
224 .main_clk = "gpt3_fck",
225 .prcm = {
226 .omap2 = {
227 .prcm_reg_id = 1,
228 .module_bit = OMAP3430_EN_GPT3_SHIFT,
229 .module_offs = OMAP3430_PER_MOD,
230 .idlest_reg_id = 1,
231 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
232 },
233 },
234 .class = &omap3xxx_timer_hwmod_class,
235 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
236 };
237
238 /* timer4 */
239 static struct omap_hwmod omap3xxx_timer4_hwmod = {
240 .name = "timer4",
241 .main_clk = "gpt4_fck",
242 .prcm = {
243 .omap2 = {
244 .prcm_reg_id = 1,
245 .module_bit = OMAP3430_EN_GPT4_SHIFT,
246 .module_offs = OMAP3430_PER_MOD,
247 .idlest_reg_id = 1,
248 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
249 },
250 },
251 .class = &omap3xxx_timer_hwmod_class,
252 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
253 };
254
255 /* timer5 */
256 static struct omap_hwmod omap3xxx_timer5_hwmod = {
257 .name = "timer5",
258 .main_clk = "gpt5_fck",
259 .prcm = {
260 .omap2 = {
261 .prcm_reg_id = 1,
262 .module_bit = OMAP3430_EN_GPT5_SHIFT,
263 .module_offs = OMAP3430_PER_MOD,
264 .idlest_reg_id = 1,
265 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
266 },
267 },
268 .dev_attr = &capability_dsp_dev_attr,
269 .class = &omap3xxx_timer_hwmod_class,
270 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
271 };
272
273 /* timer6 */
274 static struct omap_hwmod omap3xxx_timer6_hwmod = {
275 .name = "timer6",
276 .main_clk = "gpt6_fck",
277 .prcm = {
278 .omap2 = {
279 .prcm_reg_id = 1,
280 .module_bit = OMAP3430_EN_GPT6_SHIFT,
281 .module_offs = OMAP3430_PER_MOD,
282 .idlest_reg_id = 1,
283 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
284 },
285 },
286 .dev_attr = &capability_dsp_dev_attr,
287 .class = &omap3xxx_timer_hwmod_class,
288 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
289 };
290
291 /* timer7 */
292 static struct omap_hwmod omap3xxx_timer7_hwmod = {
293 .name = "timer7",
294 .main_clk = "gpt7_fck",
295 .prcm = {
296 .omap2 = {
297 .prcm_reg_id = 1,
298 .module_bit = OMAP3430_EN_GPT7_SHIFT,
299 .module_offs = OMAP3430_PER_MOD,
300 .idlest_reg_id = 1,
301 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
302 },
303 },
304 .dev_attr = &capability_dsp_dev_attr,
305 .class = &omap3xxx_timer_hwmod_class,
306 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
307 };
308
309 /* timer8 */
310 static struct omap_hwmod omap3xxx_timer8_hwmod = {
311 .name = "timer8",
312 .main_clk = "gpt8_fck",
313 .prcm = {
314 .omap2 = {
315 .prcm_reg_id = 1,
316 .module_bit = OMAP3430_EN_GPT8_SHIFT,
317 .module_offs = OMAP3430_PER_MOD,
318 .idlest_reg_id = 1,
319 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
320 },
321 },
322 .dev_attr = &capability_dsp_pwm_dev_attr,
323 .class = &omap3xxx_timer_hwmod_class,
324 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
325 };
326
327 /* timer9 */
328 static struct omap_hwmod omap3xxx_timer9_hwmod = {
329 .name = "timer9",
330 .main_clk = "gpt9_fck",
331 .prcm = {
332 .omap2 = {
333 .prcm_reg_id = 1,
334 .module_bit = OMAP3430_EN_GPT9_SHIFT,
335 .module_offs = OMAP3430_PER_MOD,
336 .idlest_reg_id = 1,
337 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
338 },
339 },
340 .dev_attr = &capability_pwm_dev_attr,
341 .class = &omap3xxx_timer_hwmod_class,
342 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
343 };
344
345 /* timer10 */
346 static struct omap_hwmod omap3xxx_timer10_hwmod = {
347 .name = "timer10",
348 .main_clk = "gpt10_fck",
349 .prcm = {
350 .omap2 = {
351 .prcm_reg_id = 1,
352 .module_bit = OMAP3430_EN_GPT10_SHIFT,
353 .module_offs = CORE_MOD,
354 .idlest_reg_id = 1,
355 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
356 },
357 },
358 .dev_attr = &capability_pwm_dev_attr,
359 .class = &omap3xxx_timer_hwmod_class,
360 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
361 };
362
363 /* timer11 */
364 static struct omap_hwmod omap3xxx_timer11_hwmod = {
365 .name = "timer11",
366 .main_clk = "gpt11_fck",
367 .prcm = {
368 .omap2 = {
369 .prcm_reg_id = 1,
370 .module_bit = OMAP3430_EN_GPT11_SHIFT,
371 .module_offs = CORE_MOD,
372 .idlest_reg_id = 1,
373 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
374 },
375 },
376 .dev_attr = &capability_pwm_dev_attr,
377 .class = &omap3xxx_timer_hwmod_class,
378 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
379 };
380
381 /* timer12 */
382
383 static struct omap_hwmod omap3xxx_timer12_hwmod = {
384 .name = "timer12",
385 .main_clk = "gpt12_fck",
386 .prcm = {
387 .omap2 = {
388 .prcm_reg_id = 1,
389 .module_bit = OMAP3430_EN_GPT12_SHIFT,
390 .module_offs = WKUP_MOD,
391 .idlest_reg_id = 1,
392 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
393 },
394 },
395 .dev_attr = &capability_secure_dev_attr,
396 .class = &omap3xxx_timer_hwmod_class,
397 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
398 };
399
400 /*
401 * 'wd_timer' class
402 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
403 * overflow condition
404 */
405
406 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
407 .rev_offs = 0x0000,
408 .sysc_offs = 0x0010,
409 .syss_offs = 0x0014,
410 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
411 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
412 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
413 SYSS_HAS_RESET_STATUS),
414 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
415 .sysc_fields = &omap_hwmod_sysc_type1,
416 };
417
418 /* I2C common */
419 static struct omap_hwmod_class_sysconfig i2c_sysc = {
420 .rev_offs = 0x00,
421 .sysc_offs = 0x20,
422 .syss_offs = 0x10,
423 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
424 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
425 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
426 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
427 .clockact = CLOCKACT_TEST_ICLK,
428 .sysc_fields = &omap_hwmod_sysc_type1,
429 };
430
431 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
432 .name = "wd_timer",
433 .sysc = &omap3xxx_wd_timer_sysc,
434 .pre_shutdown = &omap2_wd_timer_disable,
435 .reset = &omap2_wd_timer_reset,
436 };
437
438 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
439 .name = "wd_timer2",
440 .class = &omap3xxx_wd_timer_hwmod_class,
441 .main_clk = "wdt2_fck",
442 .prcm = {
443 .omap2 = {
444 .prcm_reg_id = 1,
445 .module_bit = OMAP3430_EN_WDT2_SHIFT,
446 .module_offs = WKUP_MOD,
447 .idlest_reg_id = 1,
448 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
449 },
450 },
451 /*
452 * XXX: Use software supervised mode, HW supervised smartidle seems to
453 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
454 */
455 .flags = HWMOD_SWSUP_SIDLE,
456 };
457
458 /* UART1 */
459 static struct omap_hwmod omap3xxx_uart1_hwmod = {
460 .name = "uart1",
461 .main_clk = "uart1_fck",
462 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
463 .prcm = {
464 .omap2 = {
465 .module_offs = CORE_MOD,
466 .prcm_reg_id = 1,
467 .module_bit = OMAP3430_EN_UART1_SHIFT,
468 .idlest_reg_id = 1,
469 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
470 },
471 },
472 .class = &omap2_uart_class,
473 };
474
475 /* UART2 */
476 static struct omap_hwmod omap3xxx_uart2_hwmod = {
477 .name = "uart2",
478 .main_clk = "uart2_fck",
479 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
480 .prcm = {
481 .omap2 = {
482 .module_offs = CORE_MOD,
483 .prcm_reg_id = 1,
484 .module_bit = OMAP3430_EN_UART2_SHIFT,
485 .idlest_reg_id = 1,
486 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
487 },
488 },
489 .class = &omap2_uart_class,
490 };
491
492 /* UART3 */
493 static struct omap_hwmod omap3xxx_uart3_hwmod = {
494 .name = "uart3",
495 .main_clk = "uart3_fck",
496 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
497 HWMOD_SWSUP_SIDLE,
498 .prcm = {
499 .omap2 = {
500 .module_offs = OMAP3430_PER_MOD,
501 .prcm_reg_id = 1,
502 .module_bit = OMAP3430_EN_UART3_SHIFT,
503 .idlest_reg_id = 1,
504 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
505 },
506 },
507 .class = &omap2_uart_class,
508 };
509
510 /* UART4 */
511
512
513 static struct omap_hwmod omap36xx_uart4_hwmod = {
514 .name = "uart4",
515 .main_clk = "uart4_fck",
516 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
517 .prcm = {
518 .omap2 = {
519 .module_offs = OMAP3430_PER_MOD,
520 .prcm_reg_id = 1,
521 .module_bit = OMAP3630_EN_UART4_SHIFT,
522 .idlest_reg_id = 1,
523 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
524 },
525 },
526 .class = &omap2_uart_class,
527 };
528
529
530
531 /*
532 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
533 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
534 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
535 * should not be needed. The functional clock structure of the AM35xx
536 * UART4 is extremely unclear and opaque; it is unclear what the role
537 * of uart1/2_fck is for the UART4. Any clarification from either
538 * empirical testing or the AM3505/3517 hardware designers would be
539 * most welcome.
540 */
541 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
542 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
543 };
544
545 static struct omap_hwmod am35xx_uart4_hwmod = {
546 .name = "uart4",
547 .main_clk = "uart4_fck",
548 .prcm = {
549 .omap2 = {
550 .module_offs = CORE_MOD,
551 .prcm_reg_id = 1,
552 .module_bit = AM35XX_EN_UART4_SHIFT,
553 .idlest_reg_id = 1,
554 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
555 },
556 },
557 .opt_clks = am35xx_uart4_opt_clks,
558 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
559 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
560 .class = &omap2_uart_class,
561 };
562
563 static struct omap_hwmod_class i2c_class = {
564 .name = "i2c",
565 .sysc = &i2c_sysc,
566 .rev = OMAP_I2C_IP_VERSION_1,
567 .reset = &omap_i2c_reset,
568 };
569
570 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
571 { .name = "dispc", .dma_req = 5 },
572 { .name = "dsi1", .dma_req = 74 },
573 { .dma_req = -1, },
574 };
575
576 /* dss */
577 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
578 /*
579 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
580 * driver does not use these clocks.
581 */
582 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
583 { .role = "tv_clk", .clk = "dss_tv_fck" },
584 /* required only on OMAP3430 */
585 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
586 };
587
588 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
589 .name = "dss_core",
590 .class = &omap2_dss_hwmod_class,
591 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
592 .sdma_reqs = omap3xxx_dss_sdma_chs,
593 .prcm = {
594 .omap2 = {
595 .prcm_reg_id = 1,
596 .module_bit = OMAP3430_EN_DSS1_SHIFT,
597 .module_offs = OMAP3430_DSS_MOD,
598 .idlest_reg_id = 1,
599 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
600 },
601 },
602 .opt_clks = dss_opt_clks,
603 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
604 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
605 };
606
607 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
608 .name = "dss_core",
609 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
610 .class = &omap2_dss_hwmod_class,
611 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
612 .sdma_reqs = omap3xxx_dss_sdma_chs,
613 .prcm = {
614 .omap2 = {
615 .prcm_reg_id = 1,
616 .module_bit = OMAP3430_EN_DSS1_SHIFT,
617 .module_offs = OMAP3430_DSS_MOD,
618 .idlest_reg_id = 1,
619 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
620 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
621 },
622 },
623 .opt_clks = dss_opt_clks,
624 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
625 };
626
627 /*
628 * 'dispc' class
629 * display controller
630 */
631
632 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
633 .rev_offs = 0x0000,
634 .sysc_offs = 0x0010,
635 .syss_offs = 0x0014,
636 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
637 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
638 SYSC_HAS_ENAWAKEUP),
639 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
640 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
641 .sysc_fields = &omap_hwmod_sysc_type1,
642 };
643
644 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
645 .name = "dispc",
646 .sysc = &omap3_dispc_sysc,
647 };
648
649 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
650 .name = "dss_dispc",
651 .class = &omap3_dispc_hwmod_class,
652 .mpu_irqs = omap2_dispc_irqs,
653 .main_clk = "dss1_alwon_fck",
654 .prcm = {
655 .omap2 = {
656 .prcm_reg_id = 1,
657 .module_bit = OMAP3430_EN_DSS1_SHIFT,
658 .module_offs = OMAP3430_DSS_MOD,
659 },
660 },
661 .flags = HWMOD_NO_IDLEST,
662 .dev_attr = &omap2_3_dss_dispc_dev_attr,
663 };
664
665 /*
666 * 'dsi' class
667 * display serial interface controller
668 */
669
670 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
671 .rev_offs = 0x0000,
672 .sysc_offs = 0x0010,
673 .syss_offs = 0x0014,
674 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
675 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
676 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
677 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
678 .sysc_fields = &omap_hwmod_sysc_type1,
679 };
680
681 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
682 .name = "dsi",
683 .sysc = &omap3xxx_dsi_sysc,
684 };
685
686 /* dss_dsi1 */
687 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
688 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
689 };
690
691 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
692 .name = "dss_dsi1",
693 .class = &omap3xxx_dsi_hwmod_class,
694 .main_clk = "dss1_alwon_fck",
695 .prcm = {
696 .omap2 = {
697 .prcm_reg_id = 1,
698 .module_bit = OMAP3430_EN_DSS1_SHIFT,
699 .module_offs = OMAP3430_DSS_MOD,
700 },
701 },
702 .opt_clks = dss_dsi1_opt_clks,
703 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
704 .flags = HWMOD_NO_IDLEST,
705 };
706
707 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
708 { .role = "ick", .clk = "dss_ick" },
709 };
710
711 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
712 .name = "dss_rfbi",
713 .class = &omap2_rfbi_hwmod_class,
714 .main_clk = "dss1_alwon_fck",
715 .prcm = {
716 .omap2 = {
717 .prcm_reg_id = 1,
718 .module_bit = OMAP3430_EN_DSS1_SHIFT,
719 .module_offs = OMAP3430_DSS_MOD,
720 },
721 },
722 .opt_clks = dss_rfbi_opt_clks,
723 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
724 .flags = HWMOD_NO_IDLEST,
725 };
726
727 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
728 /* required only on OMAP3430 */
729 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
730 };
731
732 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
733 .name = "dss_venc",
734 .class = &omap2_venc_hwmod_class,
735 .main_clk = "dss_tv_fck",
736 .prcm = {
737 .omap2 = {
738 .prcm_reg_id = 1,
739 .module_bit = OMAP3430_EN_DSS1_SHIFT,
740 .module_offs = OMAP3430_DSS_MOD,
741 },
742 },
743 .opt_clks = dss_venc_opt_clks,
744 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
745 .flags = HWMOD_NO_IDLEST,
746 };
747
748 /* I2C1 */
749 static struct omap_i2c_dev_attr i2c1_dev_attr = {
750 .fifo_depth = 8, /* bytes */
751 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
752 };
753
754 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
755 .name = "i2c1",
756 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
757 .main_clk = "i2c1_fck",
758 .prcm = {
759 .omap2 = {
760 .module_offs = CORE_MOD,
761 .prcm_reg_id = 1,
762 .module_bit = OMAP3430_EN_I2C1_SHIFT,
763 .idlest_reg_id = 1,
764 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
765 },
766 },
767 .class = &i2c_class,
768 .dev_attr = &i2c1_dev_attr,
769 };
770
771 /* I2C2 */
772 static struct omap_i2c_dev_attr i2c2_dev_attr = {
773 .fifo_depth = 8, /* bytes */
774 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
775 };
776
777 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
778 .name = "i2c2",
779 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
780 .main_clk = "i2c2_fck",
781 .prcm = {
782 .omap2 = {
783 .module_offs = CORE_MOD,
784 .prcm_reg_id = 1,
785 .module_bit = OMAP3430_EN_I2C2_SHIFT,
786 .idlest_reg_id = 1,
787 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
788 },
789 },
790 .class = &i2c_class,
791 .dev_attr = &i2c2_dev_attr,
792 };
793
794 /* I2C3 */
795 static struct omap_i2c_dev_attr i2c3_dev_attr = {
796 .fifo_depth = 64, /* bytes */
797 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
798 };
799
800
801
802 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
803 .name = "i2c3",
804 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
805 .main_clk = "i2c3_fck",
806 .prcm = {
807 .omap2 = {
808 .module_offs = CORE_MOD,
809 .prcm_reg_id = 1,
810 .module_bit = OMAP3430_EN_I2C3_SHIFT,
811 .idlest_reg_id = 1,
812 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
813 },
814 },
815 .class = &i2c_class,
816 .dev_attr = &i2c3_dev_attr,
817 };
818
819 /*
820 * 'gpio' class
821 * general purpose io module
822 */
823
824 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
825 .rev_offs = 0x0000,
826 .sysc_offs = 0x0010,
827 .syss_offs = 0x0014,
828 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
829 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
830 SYSS_HAS_RESET_STATUS),
831 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
832 .sysc_fields = &omap_hwmod_sysc_type1,
833 };
834
835 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
836 .name = "gpio",
837 .sysc = &omap3xxx_gpio_sysc,
838 .rev = 1,
839 };
840
841 /* gpio_dev_attr */
842 static struct omap_gpio_dev_attr gpio_dev_attr = {
843 .bank_width = 32,
844 .dbck_flag = true,
845 };
846
847 /* gpio1 */
848 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
849 { .role = "dbclk", .clk = "gpio1_dbck", },
850 };
851
852 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
853 .name = "gpio1",
854 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
855 .main_clk = "gpio1_ick",
856 .opt_clks = gpio1_opt_clks,
857 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
858 .prcm = {
859 .omap2 = {
860 .prcm_reg_id = 1,
861 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
862 .module_offs = WKUP_MOD,
863 .idlest_reg_id = 1,
864 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
865 },
866 },
867 .class = &omap3xxx_gpio_hwmod_class,
868 .dev_attr = &gpio_dev_attr,
869 };
870
871 /* gpio2 */
872 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
873 { .role = "dbclk", .clk = "gpio2_dbck", },
874 };
875
876 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
877 .name = "gpio2",
878 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
879 .main_clk = "gpio2_ick",
880 .opt_clks = gpio2_opt_clks,
881 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
882 .prcm = {
883 .omap2 = {
884 .prcm_reg_id = 1,
885 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
886 .module_offs = OMAP3430_PER_MOD,
887 .idlest_reg_id = 1,
888 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
889 },
890 },
891 .class = &omap3xxx_gpio_hwmod_class,
892 .dev_attr = &gpio_dev_attr,
893 };
894
895 /* gpio3 */
896 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
897 { .role = "dbclk", .clk = "gpio3_dbck", },
898 };
899
900 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
901 .name = "gpio3",
902 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
903 .main_clk = "gpio3_ick",
904 .opt_clks = gpio3_opt_clks,
905 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
906 .prcm = {
907 .omap2 = {
908 .prcm_reg_id = 1,
909 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
910 .module_offs = OMAP3430_PER_MOD,
911 .idlest_reg_id = 1,
912 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
913 },
914 },
915 .class = &omap3xxx_gpio_hwmod_class,
916 .dev_attr = &gpio_dev_attr,
917 };
918
919 /* gpio4 */
920 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
921 { .role = "dbclk", .clk = "gpio4_dbck", },
922 };
923
924 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
925 .name = "gpio4",
926 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
927 .main_clk = "gpio4_ick",
928 .opt_clks = gpio4_opt_clks,
929 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
930 .prcm = {
931 .omap2 = {
932 .prcm_reg_id = 1,
933 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
934 .module_offs = OMAP3430_PER_MOD,
935 .idlest_reg_id = 1,
936 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
937 },
938 },
939 .class = &omap3xxx_gpio_hwmod_class,
940 .dev_attr = &gpio_dev_attr,
941 };
942
943 /* gpio5 */
944
945 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
946 { .role = "dbclk", .clk = "gpio5_dbck", },
947 };
948
949 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
950 .name = "gpio5",
951 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
952 .main_clk = "gpio5_ick",
953 .opt_clks = gpio5_opt_clks,
954 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
955 .prcm = {
956 .omap2 = {
957 .prcm_reg_id = 1,
958 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
959 .module_offs = OMAP3430_PER_MOD,
960 .idlest_reg_id = 1,
961 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
962 },
963 },
964 .class = &omap3xxx_gpio_hwmod_class,
965 .dev_attr = &gpio_dev_attr,
966 };
967
968 /* gpio6 */
969
970 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
971 { .role = "dbclk", .clk = "gpio6_dbck", },
972 };
973
974 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
975 .name = "gpio6",
976 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
977 .main_clk = "gpio6_ick",
978 .opt_clks = gpio6_opt_clks,
979 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
980 .prcm = {
981 .omap2 = {
982 .prcm_reg_id = 1,
983 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
984 .module_offs = OMAP3430_PER_MOD,
985 .idlest_reg_id = 1,
986 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
987 },
988 },
989 .class = &omap3xxx_gpio_hwmod_class,
990 .dev_attr = &gpio_dev_attr,
991 };
992
993 /* dma attributes */
994 static struct omap_dma_dev_attr dma_dev_attr = {
995 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
996 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
997 .lch_count = 32,
998 };
999
1000 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1001 .rev_offs = 0x0000,
1002 .sysc_offs = 0x002c,
1003 .syss_offs = 0x0028,
1004 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1005 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1006 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1007 SYSS_HAS_RESET_STATUS),
1008 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1009 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1010 .sysc_fields = &omap_hwmod_sysc_type1,
1011 };
1012
1013 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1014 .name = "dma",
1015 .sysc = &omap3xxx_dma_sysc,
1016 };
1017
1018 /* dma_system */
1019 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1020 .name = "dma",
1021 .class = &omap3xxx_dma_hwmod_class,
1022 .mpu_irqs = omap2_dma_system_irqs,
1023 .main_clk = "core_l3_ick",
1024 .prcm = {
1025 .omap2 = {
1026 .module_offs = CORE_MOD,
1027 .prcm_reg_id = 1,
1028 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1029 .idlest_reg_id = 1,
1030 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1031 },
1032 },
1033 .dev_attr = &dma_dev_attr,
1034 .flags = HWMOD_NO_IDLEST,
1035 };
1036
1037 /*
1038 * 'mcbsp' class
1039 * multi channel buffered serial port controller
1040 */
1041
1042 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1043 .sysc_offs = 0x008c,
1044 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1045 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1046 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1047 .sysc_fields = &omap_hwmod_sysc_type1,
1048 .clockact = 0x2,
1049 };
1050
1051 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1052 .name = "mcbsp",
1053 .sysc = &omap3xxx_mcbsp_sysc,
1054 .rev = MCBSP_CONFIG_TYPE3,
1055 };
1056
1057 /* McBSP functional clock mapping */
1058 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1059 { .role = "pad_fck", .clk = "mcbsp_clks" },
1060 { .role = "prcm_fck", .clk = "core_96m_fck" },
1061 };
1062
1063 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1064 { .role = "pad_fck", .clk = "mcbsp_clks" },
1065 { .role = "prcm_fck", .clk = "per_96m_fck" },
1066 };
1067
1068 /* mcbsp1 */
1069
1070 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1071 .name = "mcbsp1",
1072 .class = &omap3xxx_mcbsp_hwmod_class,
1073 .main_clk = "mcbsp1_fck",
1074 .prcm = {
1075 .omap2 = {
1076 .prcm_reg_id = 1,
1077 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1078 .module_offs = CORE_MOD,
1079 .idlest_reg_id = 1,
1080 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1081 },
1082 },
1083 .opt_clks = mcbsp15_opt_clks,
1084 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1085 };
1086
1087 /* mcbsp2 */
1088
1089 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1090 .sidetone = "mcbsp2_sidetone",
1091 };
1092
1093 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1094 .name = "mcbsp2",
1095 .class = &omap3xxx_mcbsp_hwmod_class,
1096 .main_clk = "mcbsp2_fck",
1097 .prcm = {
1098 .omap2 = {
1099 .prcm_reg_id = 1,
1100 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1101 .module_offs = OMAP3430_PER_MOD,
1102 .idlest_reg_id = 1,
1103 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1104 },
1105 },
1106 .opt_clks = mcbsp234_opt_clks,
1107 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1108 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1109 };
1110
1111 /* mcbsp3 */
1112
1113 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1114 .sidetone = "mcbsp3_sidetone",
1115 };
1116
1117 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1118 .name = "mcbsp3",
1119 .class = &omap3xxx_mcbsp_hwmod_class,
1120 .main_clk = "mcbsp3_fck",
1121 .prcm = {
1122 .omap2 = {
1123 .prcm_reg_id = 1,
1124 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1125 .module_offs = OMAP3430_PER_MOD,
1126 .idlest_reg_id = 1,
1127 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1128 },
1129 },
1130 .opt_clks = mcbsp234_opt_clks,
1131 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1132 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1133 };
1134
1135 /* mcbsp4 */
1136
1137
1138 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1139 .name = "mcbsp4",
1140 .class = &omap3xxx_mcbsp_hwmod_class,
1141 .main_clk = "mcbsp4_fck",
1142 .prcm = {
1143 .omap2 = {
1144 .prcm_reg_id = 1,
1145 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1146 .module_offs = OMAP3430_PER_MOD,
1147 .idlest_reg_id = 1,
1148 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1149 },
1150 },
1151 .opt_clks = mcbsp234_opt_clks,
1152 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1153 };
1154
1155 /* mcbsp5 */
1156
1157
1158 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1159 .name = "mcbsp5",
1160 .class = &omap3xxx_mcbsp_hwmod_class,
1161 .main_clk = "mcbsp5_fck",
1162 .prcm = {
1163 .omap2 = {
1164 .prcm_reg_id = 1,
1165 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1166 .module_offs = CORE_MOD,
1167 .idlest_reg_id = 1,
1168 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1169 },
1170 },
1171 .opt_clks = mcbsp15_opt_clks,
1172 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1173 };
1174
1175 /* 'mcbsp sidetone' class */
1176 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1177 .sysc_offs = 0x0010,
1178 .sysc_flags = SYSC_HAS_AUTOIDLE,
1179 .sysc_fields = &omap_hwmod_sysc_type1,
1180 };
1181
1182 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1183 .name = "mcbsp_sidetone",
1184 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1185 };
1186
1187 /* mcbsp2_sidetone */
1188
1189 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1190 .name = "mcbsp2_sidetone",
1191 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1192 .main_clk = "mcbsp2_ick",
1193 .flags = HWMOD_NO_IDLEST,
1194 };
1195
1196 /* mcbsp3_sidetone */
1197
1198 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1199 .name = "mcbsp3_sidetone",
1200 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1201 .main_clk = "mcbsp3_ick",
1202 .flags = HWMOD_NO_IDLEST,
1203 };
1204
1205 /* SR common */
1206 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1207 .clkact_shift = 20,
1208 };
1209
1210 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1211 .sysc_offs = 0x24,
1212 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1213 .clockact = CLOCKACT_TEST_ICLK,
1214 .sysc_fields = &omap34xx_sr_sysc_fields,
1215 };
1216
1217 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1218 .name = "smartreflex",
1219 .sysc = &omap34xx_sr_sysc,
1220 .rev = 1,
1221 };
1222
1223 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1224 .sidle_shift = 24,
1225 .enwkup_shift = 26,
1226 };
1227
1228 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1229 .sysc_offs = 0x38,
1230 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1231 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1232 SYSC_NO_CACHE),
1233 .sysc_fields = &omap36xx_sr_sysc_fields,
1234 };
1235
1236 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1237 .name = "smartreflex",
1238 .sysc = &omap36xx_sr_sysc,
1239 .rev = 2,
1240 };
1241
1242 /* SR1 */
1243 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1244 .sensor_voltdm_name = "mpu_iva",
1245 };
1246
1247
1248 static struct omap_hwmod omap34xx_sr1_hwmod = {
1249 .name = "smartreflex_mpu_iva",
1250 .class = &omap34xx_smartreflex_hwmod_class,
1251 .main_clk = "sr1_fck",
1252 .prcm = {
1253 .omap2 = {
1254 .prcm_reg_id = 1,
1255 .module_bit = OMAP3430_EN_SR1_SHIFT,
1256 .module_offs = WKUP_MOD,
1257 .idlest_reg_id = 1,
1258 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1259 },
1260 },
1261 .dev_attr = &sr1_dev_attr,
1262 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1263 };
1264
1265 static struct omap_hwmod omap36xx_sr1_hwmod = {
1266 .name = "smartreflex_mpu_iva",
1267 .class = &omap36xx_smartreflex_hwmod_class,
1268 .main_clk = "sr1_fck",
1269 .prcm = {
1270 .omap2 = {
1271 .prcm_reg_id = 1,
1272 .module_bit = OMAP3430_EN_SR1_SHIFT,
1273 .module_offs = WKUP_MOD,
1274 .idlest_reg_id = 1,
1275 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1276 },
1277 },
1278 .dev_attr = &sr1_dev_attr,
1279 };
1280
1281 /* SR2 */
1282 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1283 .sensor_voltdm_name = "core",
1284 };
1285
1286
1287 static struct omap_hwmod omap34xx_sr2_hwmod = {
1288 .name = "smartreflex_core",
1289 .class = &omap34xx_smartreflex_hwmod_class,
1290 .main_clk = "sr2_fck",
1291 .prcm = {
1292 .omap2 = {
1293 .prcm_reg_id = 1,
1294 .module_bit = OMAP3430_EN_SR2_SHIFT,
1295 .module_offs = WKUP_MOD,
1296 .idlest_reg_id = 1,
1297 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1298 },
1299 },
1300 .dev_attr = &sr2_dev_attr,
1301 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1302 };
1303
1304 static struct omap_hwmod omap36xx_sr2_hwmod = {
1305 .name = "smartreflex_core",
1306 .class = &omap36xx_smartreflex_hwmod_class,
1307 .main_clk = "sr2_fck",
1308 .prcm = {
1309 .omap2 = {
1310 .prcm_reg_id = 1,
1311 .module_bit = OMAP3430_EN_SR2_SHIFT,
1312 .module_offs = WKUP_MOD,
1313 .idlest_reg_id = 1,
1314 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1315 },
1316 },
1317 .dev_attr = &sr2_dev_attr,
1318 };
1319
1320 /*
1321 * 'mailbox' class
1322 * mailbox module allowing communication between the on-chip processors
1323 * using a queued mailbox-interrupt mechanism.
1324 */
1325
1326 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1327 .rev_offs = 0x000,
1328 .sysc_offs = 0x010,
1329 .syss_offs = 0x014,
1330 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1331 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1332 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1333 .sysc_fields = &omap_hwmod_sysc_type1,
1334 };
1335
1336 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1337 .name = "mailbox",
1338 .sysc = &omap3xxx_mailbox_sysc,
1339 };
1340
1341 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1342 .name = "mailbox",
1343 .class = &omap3xxx_mailbox_hwmod_class,
1344 .main_clk = "mailboxes_ick",
1345 .prcm = {
1346 .omap2 = {
1347 .prcm_reg_id = 1,
1348 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1349 .module_offs = CORE_MOD,
1350 .idlest_reg_id = 1,
1351 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1352 },
1353 },
1354 };
1355
1356 /*
1357 * 'mcspi' class
1358 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1359 * bus
1360 */
1361
1362 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1363 .rev_offs = 0x0000,
1364 .sysc_offs = 0x0010,
1365 .syss_offs = 0x0014,
1366 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1367 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1368 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1369 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1370 .sysc_fields = &omap_hwmod_sysc_type1,
1371 };
1372
1373 static struct omap_hwmod_class omap34xx_mcspi_class = {
1374 .name = "mcspi",
1375 .sysc = &omap34xx_mcspi_sysc,
1376 .rev = OMAP3_MCSPI_REV,
1377 };
1378
1379 /* mcspi1 */
1380 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1381 .num_chipselect = 4,
1382 };
1383
1384 static struct omap_hwmod omap34xx_mcspi1 = {
1385 .name = "mcspi1",
1386 .main_clk = "mcspi1_fck",
1387 .prcm = {
1388 .omap2 = {
1389 .module_offs = CORE_MOD,
1390 .prcm_reg_id = 1,
1391 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1392 .idlest_reg_id = 1,
1393 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1394 },
1395 },
1396 .class = &omap34xx_mcspi_class,
1397 .dev_attr = &omap_mcspi1_dev_attr,
1398 };
1399
1400 /* mcspi2 */
1401 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1402 .num_chipselect = 2,
1403 };
1404
1405 static struct omap_hwmod omap34xx_mcspi2 = {
1406 .name = "mcspi2",
1407 .main_clk = "mcspi2_fck",
1408 .prcm = {
1409 .omap2 = {
1410 .module_offs = CORE_MOD,
1411 .prcm_reg_id = 1,
1412 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1413 .idlest_reg_id = 1,
1414 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1415 },
1416 },
1417 .class = &omap34xx_mcspi_class,
1418 .dev_attr = &omap_mcspi2_dev_attr,
1419 };
1420
1421 /* mcspi3 */
1422
1423
1424 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1425 .num_chipselect = 2,
1426 };
1427
1428 static struct omap_hwmod omap34xx_mcspi3 = {
1429 .name = "mcspi3",
1430 .main_clk = "mcspi3_fck",
1431 .prcm = {
1432 .omap2 = {
1433 .module_offs = CORE_MOD,
1434 .prcm_reg_id = 1,
1435 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1436 .idlest_reg_id = 1,
1437 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1438 },
1439 },
1440 .class = &omap34xx_mcspi_class,
1441 .dev_attr = &omap_mcspi3_dev_attr,
1442 };
1443
1444 /* mcspi4 */
1445
1446
1447 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1448 .num_chipselect = 1,
1449 };
1450
1451 static struct omap_hwmod omap34xx_mcspi4 = {
1452 .name = "mcspi4",
1453 .main_clk = "mcspi4_fck",
1454 .prcm = {
1455 .omap2 = {
1456 .module_offs = CORE_MOD,
1457 .prcm_reg_id = 1,
1458 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1459 .idlest_reg_id = 1,
1460 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1461 },
1462 },
1463 .class = &omap34xx_mcspi_class,
1464 .dev_attr = &omap_mcspi4_dev_attr,
1465 };
1466
1467 /* usbhsotg */
1468 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1469 .rev_offs = 0x0400,
1470 .sysc_offs = 0x0404,
1471 .syss_offs = 0x0408,
1472 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1473 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1474 SYSC_HAS_AUTOIDLE),
1475 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1476 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1477 .sysc_fields = &omap_hwmod_sysc_type1,
1478 };
1479
1480 static struct omap_hwmod_class usbotg_class = {
1481 .name = "usbotg",
1482 .sysc = &omap3xxx_usbhsotg_sysc,
1483 };
1484
1485 /* usb_otg_hs */
1486
1487 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1488 .name = "usb_otg_hs",
1489 .main_clk = "hsotgusb_ick",
1490 .prcm = {
1491 .omap2 = {
1492 .prcm_reg_id = 1,
1493 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1494 .module_offs = CORE_MOD,
1495 .idlest_reg_id = 1,
1496 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1497 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT,
1498 },
1499 },
1500 .class = &usbotg_class,
1501
1502 /*
1503 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1504 * broken when autoidle is enabled
1505 * workaround is to disable the autoidle bit at module level.
1506 *
1507 * Enabling the device in any other MIDLEMODE setting but force-idle
1508 * causes core_pwrdm not enter idle states at least on OMAP3630.
1509 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1510 * signal when MIDLEMODE is set to force-idle.
1511 */
1512 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1513 HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1514 };
1515
1516 /* usb_otg_hs */
1517
1518 static struct omap_hwmod_class am35xx_usbotg_class = {
1519 .name = "am35xx_usbotg",
1520 };
1521
1522 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1523 .name = "am35x_otg_hs",
1524 .main_clk = "hsotgusb_fck",
1525 .class = &am35xx_usbotg_class,
1526 .flags = HWMOD_NO_IDLEST,
1527 };
1528
1529 /* MMC/SD/SDIO common */
1530 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1531 .rev_offs = 0x1fc,
1532 .sysc_offs = 0x10,
1533 .syss_offs = 0x14,
1534 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1535 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1536 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1537 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1538 .sysc_fields = &omap_hwmod_sysc_type1,
1539 };
1540
1541 static struct omap_hwmod_class omap34xx_mmc_class = {
1542 .name = "mmc",
1543 .sysc = &omap34xx_mmc_sysc,
1544 };
1545
1546 /* MMC/SD/SDIO1 */
1547
1548
1549
1550 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1551 { .role = "dbck", .clk = "omap_32k_fck", },
1552 };
1553
1554 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1555 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1556 };
1557
1558 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1559 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1560 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1561 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1562 };
1563
1564 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1565 .name = "mmc1",
1566 .opt_clks = omap34xx_mmc1_opt_clks,
1567 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1568 .main_clk = "mmchs1_fck",
1569 .prcm = {
1570 .omap2 = {
1571 .module_offs = CORE_MOD,
1572 .prcm_reg_id = 1,
1573 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1574 .idlest_reg_id = 1,
1575 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1576 },
1577 },
1578 .dev_attr = &mmc1_pre_es3_dev_attr,
1579 .class = &omap34xx_mmc_class,
1580 };
1581
1582 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1583 .name = "mmc1",
1584 .opt_clks = omap34xx_mmc1_opt_clks,
1585 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1586 .main_clk = "mmchs1_fck",
1587 .prcm = {
1588 .omap2 = {
1589 .module_offs = CORE_MOD,
1590 .prcm_reg_id = 1,
1591 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1592 .idlest_reg_id = 1,
1593 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1594 },
1595 },
1596 .dev_attr = &mmc1_dev_attr,
1597 .class = &omap34xx_mmc_class,
1598 };
1599
1600 /* MMC/SD/SDIO2 */
1601
1602
1603
1604 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1605 { .role = "dbck", .clk = "omap_32k_fck", },
1606 };
1607
1608 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1609 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1610 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1611 };
1612
1613 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1614 .name = "mmc2",
1615 .opt_clks = omap34xx_mmc2_opt_clks,
1616 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1617 .main_clk = "mmchs2_fck",
1618 .prcm = {
1619 .omap2 = {
1620 .module_offs = CORE_MOD,
1621 .prcm_reg_id = 1,
1622 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1623 .idlest_reg_id = 1,
1624 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1625 },
1626 },
1627 .dev_attr = &mmc2_pre_es3_dev_attr,
1628 .class = &omap34xx_mmc_class,
1629 };
1630
1631 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1632 .name = "mmc2",
1633 .opt_clks = omap34xx_mmc2_opt_clks,
1634 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1635 .main_clk = "mmchs2_fck",
1636 .prcm = {
1637 .omap2 = {
1638 .module_offs = CORE_MOD,
1639 .prcm_reg_id = 1,
1640 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1641 .idlest_reg_id = 1,
1642 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1643 },
1644 },
1645 .class = &omap34xx_mmc_class,
1646 };
1647
1648 /* MMC/SD/SDIO3 */
1649
1650
1651
1652 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1653 { .role = "dbck", .clk = "omap_32k_fck", },
1654 };
1655
1656 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1657 .name = "mmc3",
1658 .opt_clks = omap34xx_mmc3_opt_clks,
1659 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1660 .main_clk = "mmchs3_fck",
1661 .prcm = {
1662 .omap2 = {
1663 .prcm_reg_id = 1,
1664 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1665 .idlest_reg_id = 1,
1666 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1667 },
1668 },
1669 .class = &omap34xx_mmc_class,
1670 };
1671
1672 /*
1673 * 'usb_host_hs' class
1674 * high-speed multi-port usb host controller
1675 */
1676
1677 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1678 .rev_offs = 0x0000,
1679 .sysc_offs = 0x0010,
1680 .syss_offs = 0x0014,
1681 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1682 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1683 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1684 SYSS_HAS_RESET_STATUS),
1685 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1686 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1687 .sysc_fields = &omap_hwmod_sysc_type1,
1688 };
1689
1690 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1691 .name = "usb_host_hs",
1692 .sysc = &omap3xxx_usb_host_hs_sysc,
1693 };
1694
1695
1696 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1697 .name = "usb_host_hs",
1698 .class = &omap3xxx_usb_host_hs_hwmod_class,
1699 .clkdm_name = "usbhost_clkdm",
1700 .main_clk = "usbhost_48m_fck",
1701 .prcm = {
1702 .omap2 = {
1703 .module_offs = OMAP3430ES2_USBHOST_MOD,
1704 .prcm_reg_id = 1,
1705 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1706 .idlest_reg_id = 1,
1707 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1708 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1709 },
1710 },
1711
1712 /*
1713 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1714 * id: i660
1715 *
1716 * Description:
1717 * In the following configuration :
1718 * - USBHOST module is set to smart-idle mode
1719 * - PRCM asserts idle_req to the USBHOST module ( This typically
1720 * happens when the system is going to a low power mode : all ports
1721 * have been suspended, the master part of the USBHOST module has
1722 * entered the standby state, and SW has cut the functional clocks)
1723 * - an USBHOST interrupt occurs before the module is able to answer
1724 * idle_ack, typically a remote wakeup IRQ.
1725 * Then the USB HOST module will enter a deadlock situation where it
1726 * is no more accessible nor functional.
1727 *
1728 * Workaround:
1729 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1730 */
1731
1732 /*
1733 * Errata: USB host EHCI may stall when entering smart-standby mode
1734 * Id: i571
1735 *
1736 * Description:
1737 * When the USBHOST module is set to smart-standby mode, and when it is
1738 * ready to enter the standby state (i.e. all ports are suspended and
1739 * all attached devices are in suspend mode), then it can wrongly assert
1740 * the Mstandby signal too early while there are still some residual OCP
1741 * transactions ongoing. If this condition occurs, the internal state
1742 * machine may go to an undefined state and the USB link may be stuck
1743 * upon the next resume.
1744 *
1745 * Workaround:
1746 * Don't use smart standby; use only force standby,
1747 * hence HWMOD_SWSUP_MSTANDBY
1748 */
1749
1750 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1751 };
1752
1753 /*
1754 * 'usb_tll_hs' class
1755 * usb_tll_hs module is the adapter on the usb_host_hs ports
1756 */
1757 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1758 .rev_offs = 0x0000,
1759 .sysc_offs = 0x0010,
1760 .syss_offs = 0x0014,
1761 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1762 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1763 SYSC_HAS_AUTOIDLE),
1764 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1765 .sysc_fields = &omap_hwmod_sysc_type1,
1766 };
1767
1768 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1769 .name = "usb_tll_hs",
1770 .sysc = &omap3xxx_usb_tll_hs_sysc,
1771 };
1772
1773
1774 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1775 .name = "usb_tll_hs",
1776 .class = &omap3xxx_usb_tll_hs_hwmod_class,
1777 .clkdm_name = "core_l4_clkdm",
1778 .main_clk = "usbtll_fck",
1779 .prcm = {
1780 .omap2 = {
1781 .module_offs = CORE_MOD,
1782 .prcm_reg_id = 3,
1783 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1784 .idlest_reg_id = 3,
1785 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1786 },
1787 },
1788 };
1789
1790 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1791 .name = "hdq1w",
1792 .main_clk = "hdq_fck",
1793 .prcm = {
1794 .omap2 = {
1795 .module_offs = CORE_MOD,
1796 .prcm_reg_id = 1,
1797 .module_bit = OMAP3430_EN_HDQ_SHIFT,
1798 .idlest_reg_id = 1,
1799 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1800 },
1801 },
1802 .class = &omap2_hdq1w_class,
1803 };
1804
1805 /* SAD2D */
1806 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
1807 { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
1808 { .name = "rst_modem_sw", .rst_shift = 1 },
1809 };
1810
1811 static struct omap_hwmod_class omap3xxx_sad2d_class = {
1812 .name = "sad2d",
1813 };
1814
1815 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
1816 .name = "sad2d",
1817 .rst_lines = omap3xxx_sad2d_resets,
1818 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets),
1819 .main_clk = "sad2d_ick",
1820 .prcm = {
1821 .omap2 = {
1822 .module_offs = CORE_MOD,
1823 .prcm_reg_id = 1,
1824 .module_bit = OMAP3430_EN_SAD2D_SHIFT,
1825 .idlest_reg_id = 1,
1826 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
1827 },
1828 },
1829 .class = &omap3xxx_sad2d_class,
1830 };
1831
1832 /*
1833 * '32K sync counter' class
1834 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
1835 */
1836 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
1837 .rev_offs = 0x0000,
1838 .sysc_offs = 0x0004,
1839 .sysc_flags = SYSC_HAS_SIDLEMODE,
1840 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
1841 .sysc_fields = &omap_hwmod_sysc_type1,
1842 };
1843
1844 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
1845 .name = "counter",
1846 .sysc = &omap3xxx_counter_sysc,
1847 };
1848
1849 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
1850 .name = "counter_32k",
1851 .class = &omap3xxx_counter_hwmod_class,
1852 .clkdm_name = "wkup_clkdm",
1853 .flags = HWMOD_SWSUP_SIDLE,
1854 .main_clk = "wkup_32k_fck",
1855 .prcm = {
1856 .omap2 = {
1857 .module_offs = WKUP_MOD,
1858 .prcm_reg_id = 1,
1859 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
1860 .idlest_reg_id = 1,
1861 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
1862 },
1863 },
1864 };
1865
1866 /*
1867 * 'gpmc' class
1868 * general purpose memory controller
1869 */
1870
1871 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
1872 .rev_offs = 0x0000,
1873 .sysc_offs = 0x0010,
1874 .syss_offs = 0x0014,
1875 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1876 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1877 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1878 .sysc_fields = &omap_hwmod_sysc_type1,
1879 };
1880
1881 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
1882 .name = "gpmc",
1883 .sysc = &omap3xxx_gpmc_sysc,
1884 };
1885
1886 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
1887 .name = "gpmc",
1888 .class = &omap3xxx_gpmc_hwmod_class,
1889 .clkdm_name = "core_l3_clkdm",
1890 .main_clk = "gpmc_fck",
1891 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1892 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1893 };
1894
1895 /*
1896 * interfaces
1897 */
1898
1899 /* L3 -> L4_CORE interface */
1900 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
1901 .master = &omap3xxx_l3_main_hwmod,
1902 .slave = &omap3xxx_l4_core_hwmod,
1903 .user = OCP_USER_MPU | OCP_USER_SDMA,
1904 };
1905
1906 /* L3 -> L4_PER interface */
1907 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
1908 .master = &omap3xxx_l3_main_hwmod,
1909 .slave = &omap3xxx_l4_per_hwmod,
1910 .user = OCP_USER_MPU | OCP_USER_SDMA,
1911 };
1912
1913
1914 /* MPU -> L3 interface */
1915 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
1916 .master = &omap3xxx_mpu_hwmod,
1917 .slave = &omap3xxx_l3_main_hwmod,
1918 .user = OCP_USER_MPU,
1919 };
1920
1921
1922 /* l3 -> debugss */
1923 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
1924 .master = &omap3xxx_l3_main_hwmod,
1925 .slave = &omap3xxx_debugss_hwmod,
1926 .user = OCP_USER_MPU,
1927 };
1928
1929 /* DSS -> l3 */
1930 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
1931 .master = &omap3430es1_dss_core_hwmod,
1932 .slave = &omap3xxx_l3_main_hwmod,
1933 .user = OCP_USER_MPU | OCP_USER_SDMA,
1934 };
1935
1936 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
1937 .master = &omap3xxx_dss_core_hwmod,
1938 .slave = &omap3xxx_l3_main_hwmod,
1939 .fw = {
1940 .omap2 = {
1941 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
1942 .flags = OMAP_FIREWALL_L3,
1943 },
1944 },
1945 .user = OCP_USER_MPU | OCP_USER_SDMA,
1946 };
1947
1948 /* l3_core -> usbhsotg interface */
1949 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
1950 .master = &omap3xxx_usbhsotg_hwmod,
1951 .slave = &omap3xxx_l3_main_hwmod,
1952 .clk = "core_l3_ick",
1953 .user = OCP_USER_MPU,
1954 };
1955
1956 /* l3_core -> am35xx_usbhsotg interface */
1957 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
1958 .master = &am35xx_usbhsotg_hwmod,
1959 .slave = &omap3xxx_l3_main_hwmod,
1960 .clk = "hsotgusb_ick",
1961 .user = OCP_USER_MPU,
1962 };
1963
1964 /* l3_core -> sad2d interface */
1965 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
1966 .master = &omap3xxx_sad2d_hwmod,
1967 .slave = &omap3xxx_l3_main_hwmod,
1968 .clk = "core_l3_ick",
1969 .user = OCP_USER_MPU,
1970 };
1971
1972 /* L4_CORE -> L4_WKUP interface */
1973 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
1974 .master = &omap3xxx_l4_core_hwmod,
1975 .slave = &omap3xxx_l4_wkup_hwmod,
1976 .user = OCP_USER_MPU | OCP_USER_SDMA,
1977 };
1978
1979 /* L4 CORE -> MMC1 interface */
1980 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
1981 .master = &omap3xxx_l4_core_hwmod,
1982 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
1983 .clk = "mmchs1_ick",
1984 .user = OCP_USER_MPU | OCP_USER_SDMA,
1985 .flags = OMAP_FIREWALL_L4,
1986 };
1987
1988 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
1989 .master = &omap3xxx_l4_core_hwmod,
1990 .slave = &omap3xxx_es3plus_mmc1_hwmod,
1991 .clk = "mmchs1_ick",
1992 .user = OCP_USER_MPU | OCP_USER_SDMA,
1993 .flags = OMAP_FIREWALL_L4,
1994 };
1995
1996 /* L4 CORE -> MMC2 interface */
1997 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
1998 .master = &omap3xxx_l4_core_hwmod,
1999 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2000 .clk = "mmchs2_ick",
2001 .user = OCP_USER_MPU | OCP_USER_SDMA,
2002 .flags = OMAP_FIREWALL_L4,
2003 };
2004
2005 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2006 .master = &omap3xxx_l4_core_hwmod,
2007 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2008 .clk = "mmchs2_ick",
2009 .user = OCP_USER_MPU | OCP_USER_SDMA,
2010 .flags = OMAP_FIREWALL_L4,
2011 };
2012
2013 /* L4 CORE -> MMC3 interface */
2014
2015 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2016 .master = &omap3xxx_l4_core_hwmod,
2017 .slave = &omap3xxx_mmc3_hwmod,
2018 .clk = "mmchs3_ick",
2019 .user = OCP_USER_MPU | OCP_USER_SDMA,
2020 .flags = OMAP_FIREWALL_L4,
2021 };
2022
2023 /* L4 CORE -> UART1 interface */
2024
2025 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2026 .master = &omap3xxx_l4_core_hwmod,
2027 .slave = &omap3xxx_uart1_hwmod,
2028 .clk = "uart1_ick",
2029 .user = OCP_USER_MPU | OCP_USER_SDMA,
2030 };
2031
2032 /* L4 CORE -> UART2 interface */
2033
2034 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2035 .master = &omap3xxx_l4_core_hwmod,
2036 .slave = &omap3xxx_uart2_hwmod,
2037 .clk = "uart2_ick",
2038 .user = OCP_USER_MPU | OCP_USER_SDMA,
2039 };
2040
2041 /* L4 PER -> UART3 interface */
2042
2043 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2044 .master = &omap3xxx_l4_per_hwmod,
2045 .slave = &omap3xxx_uart3_hwmod,
2046 .clk = "uart3_ick",
2047 .user = OCP_USER_MPU | OCP_USER_SDMA,
2048 };
2049
2050 /* L4 PER -> UART4 interface */
2051
2052 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2053 .master = &omap3xxx_l4_per_hwmod,
2054 .slave = &omap36xx_uart4_hwmod,
2055 .clk = "uart4_ick",
2056 .user = OCP_USER_MPU | OCP_USER_SDMA,
2057 };
2058
2059 /* AM35xx: L4 CORE -> UART4 interface */
2060
2061 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2062 .master = &omap3xxx_l4_core_hwmod,
2063 .slave = &am35xx_uart4_hwmod,
2064 .clk = "uart4_ick",
2065 .user = OCP_USER_MPU | OCP_USER_SDMA,
2066 };
2067
2068 /* L4 CORE -> I2C1 interface */
2069 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2070 .master = &omap3xxx_l4_core_hwmod,
2071 .slave = &omap3xxx_i2c1_hwmod,
2072 .clk = "i2c1_ick",
2073 .fw = {
2074 .omap2 = {
2075 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2076 .l4_prot_group = 7,
2077 .flags = OMAP_FIREWALL_L4,
2078 },
2079 },
2080 .user = OCP_USER_MPU | OCP_USER_SDMA,
2081 };
2082
2083 /* L4 CORE -> I2C2 interface */
2084 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2085 .master = &omap3xxx_l4_core_hwmod,
2086 .slave = &omap3xxx_i2c2_hwmod,
2087 .clk = "i2c2_ick",
2088 .fw = {
2089 .omap2 = {
2090 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2091 .l4_prot_group = 7,
2092 .flags = OMAP_FIREWALL_L4,
2093 },
2094 },
2095 .user = OCP_USER_MPU | OCP_USER_SDMA,
2096 };
2097
2098 /* L4 CORE -> I2C3 interface */
2099
2100 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2101 .master = &omap3xxx_l4_core_hwmod,
2102 .slave = &omap3xxx_i2c3_hwmod,
2103 .clk = "i2c3_ick",
2104 .fw = {
2105 .omap2 = {
2106 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2107 .l4_prot_group = 7,
2108 .flags = OMAP_FIREWALL_L4,
2109 },
2110 },
2111 .user = OCP_USER_MPU | OCP_USER_SDMA,
2112 };
2113
2114 /* L4 CORE -> SR1 interface */
2115
2116 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2117 .master = &omap3xxx_l4_core_hwmod,
2118 .slave = &omap34xx_sr1_hwmod,
2119 .clk = "sr_l4_ick",
2120 .user = OCP_USER_MPU,
2121 };
2122
2123 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2124 .master = &omap3xxx_l4_core_hwmod,
2125 .slave = &omap36xx_sr1_hwmod,
2126 .clk = "sr_l4_ick",
2127 .user = OCP_USER_MPU,
2128 };
2129
2130 /* L4 CORE -> SR1 interface */
2131
2132 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2133 .master = &omap3xxx_l4_core_hwmod,
2134 .slave = &omap34xx_sr2_hwmod,
2135 .clk = "sr_l4_ick",
2136 .user = OCP_USER_MPU,
2137 };
2138
2139 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2140 .master = &omap3xxx_l4_core_hwmod,
2141 .slave = &omap36xx_sr2_hwmod,
2142 .clk = "sr_l4_ick",
2143 .user = OCP_USER_MPU,
2144 };
2145
2146
2147 /* l4_core -> usbhsotg */
2148 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2149 .master = &omap3xxx_l4_core_hwmod,
2150 .slave = &omap3xxx_usbhsotg_hwmod,
2151 .clk = "l4_ick",
2152 .user = OCP_USER_MPU,
2153 };
2154
2155
2156 /* l4_core -> usbhsotg */
2157 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2158 .master = &omap3xxx_l4_core_hwmod,
2159 .slave = &am35xx_usbhsotg_hwmod,
2160 .clk = "hsotgusb_ick",
2161 .user = OCP_USER_MPU,
2162 };
2163
2164 /* L4_WKUP -> L4_SEC interface */
2165 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2166 .master = &omap3xxx_l4_wkup_hwmod,
2167 .slave = &omap3xxx_l4_sec_hwmod,
2168 .user = OCP_USER_MPU | OCP_USER_SDMA,
2169 };
2170
2171 /* IVA2 <- L3 interface */
2172 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2173 .master = &omap3xxx_l3_main_hwmod,
2174 .slave = &omap3xxx_iva_hwmod,
2175 .clk = "core_l3_ick",
2176 .user = OCP_USER_MPU | OCP_USER_SDMA,
2177 };
2178
2179
2180 /* l4_wkup -> timer1 */
2181 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2182 .master = &omap3xxx_l4_wkup_hwmod,
2183 .slave = &omap3xxx_timer1_hwmod,
2184 .clk = "gpt1_ick",
2185 .user = OCP_USER_MPU | OCP_USER_SDMA,
2186 };
2187
2188
2189 /* l4_per -> timer2 */
2190 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2191 .master = &omap3xxx_l4_per_hwmod,
2192 .slave = &omap3xxx_timer2_hwmod,
2193 .clk = "gpt2_ick",
2194 .user = OCP_USER_MPU | OCP_USER_SDMA,
2195 };
2196
2197
2198 /* l4_per -> timer3 */
2199 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2200 .master = &omap3xxx_l4_per_hwmod,
2201 .slave = &omap3xxx_timer3_hwmod,
2202 .clk = "gpt3_ick",
2203 .user = OCP_USER_MPU | OCP_USER_SDMA,
2204 };
2205
2206
2207 /* l4_per -> timer4 */
2208 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2209 .master = &omap3xxx_l4_per_hwmod,
2210 .slave = &omap3xxx_timer4_hwmod,
2211 .clk = "gpt4_ick",
2212 .user = OCP_USER_MPU | OCP_USER_SDMA,
2213 };
2214
2215
2216 /* l4_per -> timer5 */
2217 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2218 .master = &omap3xxx_l4_per_hwmod,
2219 .slave = &omap3xxx_timer5_hwmod,
2220 .clk = "gpt5_ick",
2221 .user = OCP_USER_MPU | OCP_USER_SDMA,
2222 };
2223
2224
2225 /* l4_per -> timer6 */
2226 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2227 .master = &omap3xxx_l4_per_hwmod,
2228 .slave = &omap3xxx_timer6_hwmod,
2229 .clk = "gpt6_ick",
2230 .user = OCP_USER_MPU | OCP_USER_SDMA,
2231 };
2232
2233
2234 /* l4_per -> timer7 */
2235 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2236 .master = &omap3xxx_l4_per_hwmod,
2237 .slave = &omap3xxx_timer7_hwmod,
2238 .clk = "gpt7_ick",
2239 .user = OCP_USER_MPU | OCP_USER_SDMA,
2240 };
2241
2242
2243 /* l4_per -> timer8 */
2244 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2245 .master = &omap3xxx_l4_per_hwmod,
2246 .slave = &omap3xxx_timer8_hwmod,
2247 .clk = "gpt8_ick",
2248 .user = OCP_USER_MPU | OCP_USER_SDMA,
2249 };
2250
2251
2252 /* l4_per -> timer9 */
2253 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2254 .master = &omap3xxx_l4_per_hwmod,
2255 .slave = &omap3xxx_timer9_hwmod,
2256 .clk = "gpt9_ick",
2257 .user = OCP_USER_MPU | OCP_USER_SDMA,
2258 };
2259
2260 /* l4_core -> timer10 */
2261 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2262 .master = &omap3xxx_l4_core_hwmod,
2263 .slave = &omap3xxx_timer10_hwmod,
2264 .clk = "gpt10_ick",
2265 .user = OCP_USER_MPU | OCP_USER_SDMA,
2266 };
2267
2268 /* l4_core -> timer11 */
2269 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2270 .master = &omap3xxx_l4_core_hwmod,
2271 .slave = &omap3xxx_timer11_hwmod,
2272 .clk = "gpt11_ick",
2273 .user = OCP_USER_MPU | OCP_USER_SDMA,
2274 };
2275
2276
2277 /* l4_core -> timer12 */
2278 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2279 .master = &omap3xxx_l4_sec_hwmod,
2280 .slave = &omap3xxx_timer12_hwmod,
2281 .clk = "gpt12_ick",
2282 .user = OCP_USER_MPU | OCP_USER_SDMA,
2283 };
2284
2285 /* l4_wkup -> wd_timer2 */
2286
2287 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2288 .master = &omap3xxx_l4_wkup_hwmod,
2289 .slave = &omap3xxx_wd_timer2_hwmod,
2290 .clk = "wdt2_ick",
2291 .user = OCP_USER_MPU | OCP_USER_SDMA,
2292 };
2293
2294 /* l4_core -> dss */
2295 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2296 .master = &omap3xxx_l4_core_hwmod,
2297 .slave = &omap3430es1_dss_core_hwmod,
2298 .clk = "dss_ick",
2299 .fw = {
2300 .omap2 = {
2301 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2302 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2303 .flags = OMAP_FIREWALL_L4,
2304 },
2305 },
2306 .user = OCP_USER_MPU | OCP_USER_SDMA,
2307 };
2308
2309 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2310 .master = &omap3xxx_l4_core_hwmod,
2311 .slave = &omap3xxx_dss_core_hwmod,
2312 .clk = "dss_ick",
2313 .fw = {
2314 .omap2 = {
2315 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2316 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2317 .flags = OMAP_FIREWALL_L4,
2318 },
2319 },
2320 .user = OCP_USER_MPU | OCP_USER_SDMA,
2321 };
2322
2323 /* l4_core -> dss_dispc */
2324 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2325 .master = &omap3xxx_l4_core_hwmod,
2326 .slave = &omap3xxx_dss_dispc_hwmod,
2327 .clk = "dss_ick",
2328 .fw = {
2329 .omap2 = {
2330 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2331 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2332 .flags = OMAP_FIREWALL_L4,
2333 },
2334 },
2335 .user = OCP_USER_MPU | OCP_USER_SDMA,
2336 };
2337
2338 /* l4_core -> dss_dsi1 */
2339 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2340 .master = &omap3xxx_l4_core_hwmod,
2341 .slave = &omap3xxx_dss_dsi1_hwmod,
2342 .clk = "dss_ick",
2343 .fw = {
2344 .omap2 = {
2345 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2346 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2347 .flags = OMAP_FIREWALL_L4,
2348 },
2349 },
2350 .user = OCP_USER_MPU | OCP_USER_SDMA,
2351 };
2352
2353 /* l4_core -> dss_rfbi */
2354 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2355 .master = &omap3xxx_l4_core_hwmod,
2356 .slave = &omap3xxx_dss_rfbi_hwmod,
2357 .clk = "dss_ick",
2358 .fw = {
2359 .omap2 = {
2360 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2361 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2362 .flags = OMAP_FIREWALL_L4,
2363 },
2364 },
2365 .user = OCP_USER_MPU | OCP_USER_SDMA,
2366 };
2367
2368 /* l4_core -> dss_venc */
2369 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2370 .master = &omap3xxx_l4_core_hwmod,
2371 .slave = &omap3xxx_dss_venc_hwmod,
2372 .clk = "dss_ick",
2373 .fw = {
2374 .omap2 = {
2375 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2376 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2377 .flags = OMAP_FIREWALL_L4,
2378 },
2379 },
2380 .flags = OCPIF_SWSUP_IDLE,
2381 .user = OCP_USER_MPU | OCP_USER_SDMA,
2382 };
2383
2384 /* l4_wkup -> gpio1 */
2385
2386 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2387 .master = &omap3xxx_l4_wkup_hwmod,
2388 .slave = &omap3xxx_gpio1_hwmod,
2389 .user = OCP_USER_MPU | OCP_USER_SDMA,
2390 };
2391
2392 /* l4_per -> gpio2 */
2393
2394 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2395 .master = &omap3xxx_l4_per_hwmod,
2396 .slave = &omap3xxx_gpio2_hwmod,
2397 .user = OCP_USER_MPU | OCP_USER_SDMA,
2398 };
2399
2400 /* l4_per -> gpio3 */
2401
2402 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2403 .master = &omap3xxx_l4_per_hwmod,
2404 .slave = &omap3xxx_gpio3_hwmod,
2405 .user = OCP_USER_MPU | OCP_USER_SDMA,
2406 };
2407
2408 /*
2409 * 'mmu' class
2410 * The memory management unit performs virtual to physical address translation
2411 * for its requestors.
2412 */
2413
2414 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2415 .rev_offs = 0x000,
2416 .sysc_offs = 0x010,
2417 .syss_offs = 0x014,
2418 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2419 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2420 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2421 .sysc_fields = &omap_hwmod_sysc_type1,
2422 };
2423
2424 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2425 .name = "mmu",
2426 .sysc = &mmu_sysc,
2427 };
2428
2429 /* mmu isp */
2430 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2431
2432 /* l4_core -> mmu isp */
2433 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
2434 .master = &omap3xxx_l4_core_hwmod,
2435 .slave = &omap3xxx_mmu_isp_hwmod,
2436 .user = OCP_USER_MPU | OCP_USER_SDMA,
2437 };
2438
2439 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
2440 .name = "mmu_isp",
2441 .class = &omap3xxx_mmu_hwmod_class,
2442 .main_clk = "cam_ick",
2443 .flags = HWMOD_NO_IDLEST,
2444 };
2445
2446 /* mmu iva */
2447
2448 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
2449
2450 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
2451 { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
2452 };
2453
2454 /* l3_main -> iva mmu */
2455 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
2456 .master = &omap3xxx_l3_main_hwmod,
2457 .slave = &omap3xxx_mmu_iva_hwmod,
2458 .user = OCP_USER_MPU | OCP_USER_SDMA,
2459 };
2460
2461 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
2462 .name = "mmu_iva",
2463 .class = &omap3xxx_mmu_hwmod_class,
2464 .clkdm_name = "iva2_clkdm",
2465 .rst_lines = omap3xxx_mmu_iva_resets,
2466 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
2467 .main_clk = "iva2_ck",
2468 .prcm = {
2469 .omap2 = {
2470 .module_offs = OMAP3430_IVA2_MOD,
2471 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
2472 .idlest_reg_id = 1,
2473 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
2474 },
2475 },
2476 .flags = HWMOD_NO_IDLEST,
2477 };
2478
2479 /* l4_per -> gpio4 */
2480
2481 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2482 .master = &omap3xxx_l4_per_hwmod,
2483 .slave = &omap3xxx_gpio4_hwmod,
2484 .user = OCP_USER_MPU | OCP_USER_SDMA,
2485 };
2486
2487 /* l4_per -> gpio5 */
2488
2489 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2490 .master = &omap3xxx_l4_per_hwmod,
2491 .slave = &omap3xxx_gpio5_hwmod,
2492 .user = OCP_USER_MPU | OCP_USER_SDMA,
2493 };
2494
2495 /* l4_per -> gpio6 */
2496
2497 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2498 .master = &omap3xxx_l4_per_hwmod,
2499 .slave = &omap3xxx_gpio6_hwmod,
2500 .user = OCP_USER_MPU | OCP_USER_SDMA,
2501 };
2502
2503 /* dma_system -> L3 */
2504 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2505 .master = &omap3xxx_dma_system_hwmod,
2506 .slave = &omap3xxx_l3_main_hwmod,
2507 .clk = "core_l3_ick",
2508 .user = OCP_USER_MPU | OCP_USER_SDMA,
2509 };
2510
2511 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2512 {
2513 .pa_start = 0x48056000,
2514 .pa_end = 0x48056fff,
2515 .flags = ADDR_TYPE_RT,
2516 },
2517 { },
2518 };
2519
2520 /* l4_cfg -> dma_system */
2521 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2522 .master = &omap3xxx_l4_core_hwmod,
2523 .slave = &omap3xxx_dma_system_hwmod,
2524 .clk = "core_l4_ick",
2525 .addr = omap3xxx_dma_system_addrs,
2526 .user = OCP_USER_MPU | OCP_USER_SDMA,
2527 };
2528
2529
2530 /* l4_core -> mcbsp1 */
2531 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2532 .master = &omap3xxx_l4_core_hwmod,
2533 .slave = &omap3xxx_mcbsp1_hwmod,
2534 .clk = "mcbsp1_ick",
2535 .user = OCP_USER_MPU | OCP_USER_SDMA,
2536 };
2537
2538
2539 /* l4_per -> mcbsp2 */
2540 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2541 .master = &omap3xxx_l4_per_hwmod,
2542 .slave = &omap3xxx_mcbsp2_hwmod,
2543 .clk = "mcbsp2_ick",
2544 .user = OCP_USER_MPU | OCP_USER_SDMA,
2545 };
2546
2547
2548 /* l4_per -> mcbsp3 */
2549 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2550 .master = &omap3xxx_l4_per_hwmod,
2551 .slave = &omap3xxx_mcbsp3_hwmod,
2552 .clk = "mcbsp3_ick",
2553 .user = OCP_USER_MPU | OCP_USER_SDMA,
2554 };
2555
2556
2557 /* l4_per -> mcbsp4 */
2558 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2559 .master = &omap3xxx_l4_per_hwmod,
2560 .slave = &omap3xxx_mcbsp4_hwmod,
2561 .clk = "mcbsp4_ick",
2562 .user = OCP_USER_MPU | OCP_USER_SDMA,
2563 };
2564
2565
2566 /* l4_core -> mcbsp5 */
2567 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2568 .master = &omap3xxx_l4_core_hwmod,
2569 .slave = &omap3xxx_mcbsp5_hwmod,
2570 .clk = "mcbsp5_ick",
2571 .user = OCP_USER_MPU | OCP_USER_SDMA,
2572 };
2573
2574
2575 /* l4_per -> mcbsp2_sidetone */
2576 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2577 .master = &omap3xxx_l4_per_hwmod,
2578 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2579 .clk = "mcbsp2_ick",
2580 .user = OCP_USER_MPU,
2581 };
2582
2583
2584 /* l4_per -> mcbsp3_sidetone */
2585 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2586 .master = &omap3xxx_l4_per_hwmod,
2587 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2588 .clk = "mcbsp3_ick",
2589 .user = OCP_USER_MPU,
2590 };
2591
2592 /* l4_core -> mailbox */
2593 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2594 .master = &omap3xxx_l4_core_hwmod,
2595 .slave = &omap3xxx_mailbox_hwmod,
2596 .user = OCP_USER_MPU | OCP_USER_SDMA,
2597 };
2598
2599 /* l4 core -> mcspi1 interface */
2600 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2601 .master = &omap3xxx_l4_core_hwmod,
2602 .slave = &omap34xx_mcspi1,
2603 .clk = "mcspi1_ick",
2604 .user = OCP_USER_MPU | OCP_USER_SDMA,
2605 };
2606
2607 /* l4 core -> mcspi2 interface */
2608 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2609 .master = &omap3xxx_l4_core_hwmod,
2610 .slave = &omap34xx_mcspi2,
2611 .clk = "mcspi2_ick",
2612 .user = OCP_USER_MPU | OCP_USER_SDMA,
2613 };
2614
2615 /* l4 core -> mcspi3 interface */
2616 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2617 .master = &omap3xxx_l4_core_hwmod,
2618 .slave = &omap34xx_mcspi3,
2619 .clk = "mcspi3_ick",
2620 .user = OCP_USER_MPU | OCP_USER_SDMA,
2621 };
2622
2623 /* l4 core -> mcspi4 interface */
2624
2625 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2626 .master = &omap3xxx_l4_core_hwmod,
2627 .slave = &omap34xx_mcspi4,
2628 .clk = "mcspi4_ick",
2629 .user = OCP_USER_MPU | OCP_USER_SDMA,
2630 };
2631
2632 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
2633 .master = &omap3xxx_usb_host_hs_hwmod,
2634 .slave = &omap3xxx_l3_main_hwmod,
2635 .clk = "core_l3_ick",
2636 .user = OCP_USER_MPU,
2637 };
2638
2639
2640 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
2641 .master = &omap3xxx_l4_core_hwmod,
2642 .slave = &omap3xxx_usb_host_hs_hwmod,
2643 .clk = "usbhost_ick",
2644 .user = OCP_USER_MPU | OCP_USER_SDMA,
2645 };
2646
2647
2648 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
2649 .master = &omap3xxx_l4_core_hwmod,
2650 .slave = &omap3xxx_usb_tll_hs_hwmod,
2651 .clk = "usbtll_ick",
2652 .user = OCP_USER_MPU | OCP_USER_SDMA,
2653 };
2654
2655 /* l4_core -> hdq1w interface */
2656 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
2657 .master = &omap3xxx_l4_core_hwmod,
2658 .slave = &omap3xxx_hdq1w_hwmod,
2659 .clk = "hdq_ick",
2660 .user = OCP_USER_MPU | OCP_USER_SDMA,
2661 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
2662 };
2663
2664 /* l4_wkup -> 32ksync_counter */
2665
2666
2667 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
2668 .master = &omap3xxx_l4_wkup_hwmod,
2669 .slave = &omap3xxx_counter_32k_hwmod,
2670 .clk = "omap_32ksync_ick",
2671 .user = OCP_USER_MPU | OCP_USER_SDMA,
2672 };
2673
2674 /* am35xx has Davinci MDIO & EMAC */
2675 static struct omap_hwmod_class am35xx_mdio_class = {
2676 .name = "davinci_mdio",
2677 };
2678
2679 static struct omap_hwmod am35xx_mdio_hwmod = {
2680 .name = "davinci_mdio",
2681 .class = &am35xx_mdio_class,
2682 .flags = HWMOD_NO_IDLEST,
2683 };
2684
2685 /*
2686 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2687 * but this will probably require some additional hwmod core support,
2688 * so is left as a future to-do item.
2689 */
2690 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
2691 .master = &am35xx_mdio_hwmod,
2692 .slave = &omap3xxx_l3_main_hwmod,
2693 .clk = "emac_fck",
2694 .user = OCP_USER_MPU,
2695 };
2696
2697 /* l4_core -> davinci mdio */
2698 /*
2699 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2700 * but this will probably require some additional hwmod core support,
2701 * so is left as a future to-do item.
2702 */
2703 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
2704 .master = &omap3xxx_l4_core_hwmod,
2705 .slave = &am35xx_mdio_hwmod,
2706 .clk = "emac_fck",
2707 .user = OCP_USER_MPU,
2708 };
2709
2710 static struct omap_hwmod_class am35xx_emac_class = {
2711 .name = "davinci_emac",
2712 };
2713
2714 static struct omap_hwmod am35xx_emac_hwmod = {
2715 .name = "davinci_emac",
2716 .class = &am35xx_emac_class,
2717 /*
2718 * According to Mark Greer, the MPU will not return from WFI
2719 * when the EMAC signals an interrupt.
2720 * http://www.spinics.net/lists/arm-kernel/msg174734.html
2721 */
2722 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
2723 };
2724
2725 /* l3_core -> davinci emac interface */
2726 /*
2727 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2728 * but this will probably require some additional hwmod core support,
2729 * so is left as a future to-do item.
2730 */
2731 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
2732 .master = &am35xx_emac_hwmod,
2733 .slave = &omap3xxx_l3_main_hwmod,
2734 .clk = "emac_ick",
2735 .user = OCP_USER_MPU,
2736 };
2737
2738 /* l4_core -> davinci emac */
2739 /*
2740 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2741 * but this will probably require some additional hwmod core support,
2742 * so is left as a future to-do item.
2743 */
2744 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
2745 .master = &omap3xxx_l4_core_hwmod,
2746 .slave = &am35xx_emac_hwmod,
2747 .clk = "emac_ick",
2748 .user = OCP_USER_MPU,
2749 };
2750
2751 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
2752 .master = &omap3xxx_l3_main_hwmod,
2753 .slave = &omap3xxx_gpmc_hwmod,
2754 .clk = "core_l3_ick",
2755 .user = OCP_USER_MPU | OCP_USER_SDMA,
2756 };
2757
2758 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
2759 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
2760 .sidle_shift = 4,
2761 .srst_shift = 1,
2762 .autoidle_shift = 0,
2763 };
2764
2765 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
2766 .rev_offs = 0x5c,
2767 .sysc_offs = 0x60,
2768 .syss_offs = 0x64,
2769 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2770 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2771 .sysc_fields = &omap3_sham_sysc_fields,
2772 };
2773
2774 static struct omap_hwmod_class omap3xxx_sham_class = {
2775 .name = "sham",
2776 .sysc = &omap3_sham_sysc,
2777 };
2778
2779
2780
2781 static struct omap_hwmod omap3xxx_sham_hwmod = {
2782 .name = "sham",
2783 .main_clk = "sha12_ick",
2784 .prcm = {
2785 .omap2 = {
2786 .module_offs = CORE_MOD,
2787 .prcm_reg_id = 1,
2788 .module_bit = OMAP3430_EN_SHA12_SHIFT,
2789 .idlest_reg_id = 1,
2790 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
2791 },
2792 },
2793 .class = &omap3xxx_sham_class,
2794 };
2795
2796
2797 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
2798 .master = &omap3xxx_l4_core_hwmod,
2799 .slave = &omap3xxx_sham_hwmod,
2800 .clk = "sha12_ick",
2801 .user = OCP_USER_MPU | OCP_USER_SDMA,
2802 };
2803
2804 /* l4_core -> AES */
2805 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
2806 .sidle_shift = 6,
2807 .srst_shift = 1,
2808 .autoidle_shift = 0,
2809 };
2810
2811 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
2812 .rev_offs = 0x44,
2813 .sysc_offs = 0x48,
2814 .syss_offs = 0x4c,
2815 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2816 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2817 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2818 .sysc_fields = &omap3xxx_aes_sysc_fields,
2819 };
2820
2821 static struct omap_hwmod_class omap3xxx_aes_class = {
2822 .name = "aes",
2823 .sysc = &omap3_aes_sysc,
2824 };
2825
2826
2827 static struct omap_hwmod omap3xxx_aes_hwmod = {
2828 .name = "aes",
2829 .main_clk = "aes2_ick",
2830 .prcm = {
2831 .omap2 = {
2832 .module_offs = CORE_MOD,
2833 .prcm_reg_id = 1,
2834 .module_bit = OMAP3430_EN_AES2_SHIFT,
2835 .idlest_reg_id = 1,
2836 .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
2837 },
2838 },
2839 .class = &omap3xxx_aes_class,
2840 };
2841
2842
2843 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
2844 .master = &omap3xxx_l4_core_hwmod,
2845 .slave = &omap3xxx_aes_hwmod,
2846 .clk = "aes2_ick",
2847 .user = OCP_USER_MPU | OCP_USER_SDMA,
2848 };
2849
2850 /*
2851 * 'ssi' class
2852 * synchronous serial interface (multichannel and full-duplex serial if)
2853 */
2854
2855 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
2856 .rev_offs = 0x0000,
2857 .sysc_offs = 0x0010,
2858 .syss_offs = 0x0014,
2859 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
2860 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2861 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2862 .sysc_fields = &omap_hwmod_sysc_type1,
2863 };
2864
2865 static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = {
2866 .name = "ssi",
2867 .sysc = &omap34xx_ssi_sysc,
2868 };
2869
2870 static struct omap_hwmod omap3xxx_ssi_hwmod = {
2871 .name = "ssi",
2872 .class = &omap3xxx_ssi_hwmod_class,
2873 .clkdm_name = "core_l4_clkdm",
2874 .main_clk = "ssi_ssr_fck",
2875 .prcm = {
2876 .omap2 = {
2877 .prcm_reg_id = 1,
2878 .module_bit = OMAP3430_EN_SSI_SHIFT,
2879 .module_offs = CORE_MOD,
2880 .idlest_reg_id = 1,
2881 .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2882 },
2883 },
2884 };
2885
2886 /* L4 CORE -> SSI */
2887 static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = {
2888 .master = &omap3xxx_l4_core_hwmod,
2889 .slave = &omap3xxx_ssi_hwmod,
2890 .clk = "ssi_ick",
2891 .user = OCP_USER_MPU | OCP_USER_SDMA,
2892 };
2893
2894 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
2895 &omap3xxx_l3_main__l4_core,
2896 &omap3xxx_l3_main__l4_per,
2897 &omap3xxx_mpu__l3_main,
2898 &omap3xxx_l3_main__l4_debugss,
2899 &omap3xxx_l4_core__l4_wkup,
2900 &omap3xxx_l4_core__mmc3,
2901 &omap3_l4_core__uart1,
2902 &omap3_l4_core__uart2,
2903 &omap3_l4_per__uart3,
2904 &omap3_l4_core__i2c1,
2905 &omap3_l4_core__i2c2,
2906 &omap3_l4_core__i2c3,
2907 &omap3xxx_l4_wkup__l4_sec,
2908 &omap3xxx_l4_wkup__timer1,
2909 &omap3xxx_l4_per__timer2,
2910 &omap3xxx_l4_per__timer3,
2911 &omap3xxx_l4_per__timer4,
2912 &omap3xxx_l4_per__timer5,
2913 &omap3xxx_l4_per__timer6,
2914 &omap3xxx_l4_per__timer7,
2915 &omap3xxx_l4_per__timer8,
2916 &omap3xxx_l4_per__timer9,
2917 &omap3xxx_l4_core__timer10,
2918 &omap3xxx_l4_core__timer11,
2919 &omap3xxx_l4_wkup__wd_timer2,
2920 &omap3xxx_l4_wkup__gpio1,
2921 &omap3xxx_l4_per__gpio2,
2922 &omap3xxx_l4_per__gpio3,
2923 &omap3xxx_l4_per__gpio4,
2924 &omap3xxx_l4_per__gpio5,
2925 &omap3xxx_l4_per__gpio6,
2926 &omap3xxx_dma_system__l3,
2927 &omap3xxx_l4_core__dma_system,
2928 &omap3xxx_l4_core__mcbsp1,
2929 &omap3xxx_l4_per__mcbsp2,
2930 &omap3xxx_l4_per__mcbsp3,
2931 &omap3xxx_l4_per__mcbsp4,
2932 &omap3xxx_l4_core__mcbsp5,
2933 &omap3xxx_l4_per__mcbsp2_sidetone,
2934 &omap3xxx_l4_per__mcbsp3_sidetone,
2935 &omap34xx_l4_core__mcspi1,
2936 &omap34xx_l4_core__mcspi2,
2937 &omap34xx_l4_core__mcspi3,
2938 &omap34xx_l4_core__mcspi4,
2939 &omap3xxx_l4_wkup__counter_32k,
2940 &omap3xxx_l3_main__gpmc,
2941 NULL,
2942 };
2943
2944 /* GP-only hwmod links */
2945 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
2946 &omap3xxx_l4_sec__timer12,
2947 NULL,
2948 };
2949
2950 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
2951 &omap3xxx_l4_sec__timer12,
2952 NULL,
2953 };
2954
2955 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
2956 &omap3xxx_l4_sec__timer12,
2957 NULL,
2958 };
2959
2960 /* crypto hwmod links */
2961 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
2962 &omap3xxx_l4_core__sham,
2963 NULL,
2964 };
2965
2966 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
2967 &omap3xxx_l4_core__aes,
2968 NULL,
2969 };
2970
2971 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
2972 &omap3xxx_l4_core__sham,
2973 NULL
2974 };
2975
2976 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
2977 &omap3xxx_l4_core__aes,
2978 NULL
2979 };
2980
2981 /*
2982 * Apparently the SHA/MD5 and AES accelerator IP blocks are
2983 * only present on some AM35xx chips, and no one knows which
2984 * ones. See
2985 * http://www.spinics.net/lists/arm-kernel/msg215466.html So
2986 * if you need these IP blocks on an AM35xx, try uncommenting
2987 * the following lines.
2988 */
2989 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
2990 /* &omap3xxx_l4_core__sham, */
2991 NULL
2992 };
2993
2994 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
2995 /* &omap3xxx_l4_core__aes, */
2996 NULL,
2997 };
2998
2999 /* 3430ES1-only hwmod links */
3000 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3001 &omap3430es1_dss__l3,
3002 &omap3430es1_l4_core__dss,
3003 NULL,
3004 };
3005
3006 /* 3430ES2+-only hwmod links */
3007 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3008 &omap3xxx_dss__l3,
3009 &omap3xxx_l4_core__dss,
3010 &omap3xxx_usbhsotg__l3,
3011 &omap3xxx_l4_core__usbhsotg,
3012 &omap3xxx_usb_host_hs__l3_main_2,
3013 &omap3xxx_l4_core__usb_host_hs,
3014 &omap3xxx_l4_core__usb_tll_hs,
3015 NULL,
3016 };
3017
3018 /* <= 3430ES3-only hwmod links */
3019 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3020 &omap3xxx_l4_core__pre_es3_mmc1,
3021 &omap3xxx_l4_core__pre_es3_mmc2,
3022 NULL,
3023 };
3024
3025 /* 3430ES3+-only hwmod links */
3026 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3027 &omap3xxx_l4_core__es3plus_mmc1,
3028 &omap3xxx_l4_core__es3plus_mmc2,
3029 NULL,
3030 };
3031
3032 /* 34xx-only hwmod links (all ES revisions) */
3033 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3034 &omap3xxx_l3__iva,
3035 &omap34xx_l4_core__sr1,
3036 &omap34xx_l4_core__sr2,
3037 &omap3xxx_l4_core__mailbox,
3038 &omap3xxx_l4_core__hdq1w,
3039 &omap3xxx_sad2d__l3,
3040 &omap3xxx_l4_core__mmu_isp,
3041 &omap3xxx_l3_main__mmu_iva,
3042 &omap3xxx_l4_core__ssi,
3043 NULL,
3044 };
3045
3046 /* 36xx-only hwmod links (all ES revisions) */
3047 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3048 &omap3xxx_l3__iva,
3049 &omap36xx_l4_per__uart4,
3050 &omap3xxx_dss__l3,
3051 &omap3xxx_l4_core__dss,
3052 &omap36xx_l4_core__sr1,
3053 &omap36xx_l4_core__sr2,
3054 &omap3xxx_usbhsotg__l3,
3055 &omap3xxx_l4_core__usbhsotg,
3056 &omap3xxx_l4_core__mailbox,
3057 &omap3xxx_usb_host_hs__l3_main_2,
3058 &omap3xxx_l4_core__usb_host_hs,
3059 &omap3xxx_l4_core__usb_tll_hs,
3060 &omap3xxx_l4_core__es3plus_mmc1,
3061 &omap3xxx_l4_core__es3plus_mmc2,
3062 &omap3xxx_l4_core__hdq1w,
3063 &omap3xxx_sad2d__l3,
3064 &omap3xxx_l4_core__mmu_isp,
3065 &omap3xxx_l3_main__mmu_iva,
3066 &omap3xxx_l4_core__ssi,
3067 NULL,
3068 };
3069
3070 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3071 &omap3xxx_dss__l3,
3072 &omap3xxx_l4_core__dss,
3073 &am35xx_usbhsotg__l3,
3074 &am35xx_l4_core__usbhsotg,
3075 &am35xx_l4_core__uart4,
3076 &omap3xxx_usb_host_hs__l3_main_2,
3077 &omap3xxx_l4_core__usb_host_hs,
3078 &omap3xxx_l4_core__usb_tll_hs,
3079 &omap3xxx_l4_core__es3plus_mmc1,
3080 &omap3xxx_l4_core__es3plus_mmc2,
3081 &omap3xxx_l4_core__hdq1w,
3082 &am35xx_mdio__l3,
3083 &am35xx_l4_core__mdio,
3084 &am35xx_emac__l3,
3085 &am35xx_l4_core__emac,
3086 NULL,
3087 };
3088
3089 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3090 &omap3xxx_l4_core__dss_dispc,
3091 &omap3xxx_l4_core__dss_dsi1,
3092 &omap3xxx_l4_core__dss_rfbi,
3093 &omap3xxx_l4_core__dss_venc,
3094 NULL,
3095 };
3096
3097 /**
3098 * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
3099 * @bus: struct device_node * for the top-level OMAP DT data
3100 * @dev_name: device name used in the DT file
3101 *
3102 * Determine whether a "secure" IP block @dev_name is usable by Linux.
3103 * There doesn't appear to be a 100% reliable way to determine this,
3104 * so we rely on heuristics. If @bus is null, meaning there's no DT
3105 * data, then we only assume the IP block is accessible if the OMAP is
3106 * fused as a 'general-purpose' SoC. If however DT data is present,
3107 * test to see if the IP block is described in the DT data and set to
3108 * 'status = "okay"'. If so then we assume the ODM has configured the
3109 * OMAP firewalls to allow access to the IP block.
3110 *
3111 * Return: 0 if device named @dev_name is not likely to be accessible,
3112 * or 1 if it is likely to be accessible.
3113 */
3114 static int __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
3115 const char *dev_name)
3116 {
3117 if (!bus)
3118 return (omap_type() == OMAP2_DEVICE_TYPE_GP) ? 1 : 0;
3119
3120 if (of_device_is_available(of_find_node_by_name(bus, dev_name)))
3121 return 1;
3122
3123 return 0;
3124 }
3125
3126 int __init omap3xxx_hwmod_init(void)
3127 {
3128 int r;
3129 struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
3130 struct omap_hwmod_ocp_if **h_aes = NULL;
3131 struct device_node *bus = NULL;
3132 unsigned int rev;
3133
3134 omap_hwmod_init();
3135
3136 /* Register hwmod links common to all OMAP3 */
3137 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3138 if (r < 0)
3139 return r;
3140
3141 rev = omap_rev();
3142
3143 /*
3144 * Register hwmod links common to individual OMAP3 families, all
3145 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3146 * All possible revisions should be included in this conditional.
3147 */
3148 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3149 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3150 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3151 h = omap34xx_hwmod_ocp_ifs;
3152 h_gp = omap34xx_gp_hwmod_ocp_ifs;
3153 h_sham = omap34xx_sham_hwmod_ocp_ifs;
3154 h_aes = omap34xx_aes_hwmod_ocp_ifs;
3155 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3156 h = am35xx_hwmod_ocp_ifs;
3157 h_gp = am35xx_gp_hwmod_ocp_ifs;
3158 h_sham = am35xx_sham_hwmod_ocp_ifs;
3159 h_aes = am35xx_aes_hwmod_ocp_ifs;
3160 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3161 rev == OMAP3630_REV_ES1_2) {
3162 h = omap36xx_hwmod_ocp_ifs;
3163 h_gp = omap36xx_gp_hwmod_ocp_ifs;
3164 h_sham = omap36xx_sham_hwmod_ocp_ifs;
3165 h_aes = omap36xx_aes_hwmod_ocp_ifs;
3166 } else {
3167 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3168 return -EINVAL;
3169 }
3170
3171 r = omap_hwmod_register_links(h);
3172 if (r < 0)
3173 return r;
3174
3175 /* Register GP-only hwmod links. */
3176 if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3177 r = omap_hwmod_register_links(h_gp);
3178 if (r < 0)
3179 return r;
3180 }
3181
3182 /*
3183 * Register crypto hwmod links only if they are not disabled in DT.
3184 * If DT information is missing, enable them only for GP devices.
3185 */
3186
3187 if (of_have_populated_dt())
3188 bus = of_find_node_by_name(NULL, "ocp");
3189
3190 if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
3191 r = omap_hwmod_register_links(h_sham);
3192 if (r < 0)
3193 return r;
3194 }
3195
3196 if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
3197 r = omap_hwmod_register_links(h_aes);
3198 if (r < 0)
3199 return r;
3200 }
3201
3202 /*
3203 * Register hwmod links specific to certain ES levels of a
3204 * particular family of silicon (e.g., 34xx ES1.0)
3205 */
3206 h = NULL;
3207 if (rev == OMAP3430_REV_ES1_0) {
3208 h = omap3430es1_hwmod_ocp_ifs;
3209 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3210 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3211 rev == OMAP3430_REV_ES3_1_2) {
3212 h = omap3430es2plus_hwmod_ocp_ifs;
3213 }
3214
3215 if (h) {
3216 r = omap_hwmod_register_links(h);
3217 if (r < 0)
3218 return r;
3219 }
3220
3221 h = NULL;
3222 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3223 rev == OMAP3430_REV_ES2_1) {
3224 h = omap3430_pre_es3_hwmod_ocp_ifs;
3225 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3226 rev == OMAP3430_REV_ES3_1_2) {
3227 h = omap3430_es3plus_hwmod_ocp_ifs;
3228 }
3229
3230 if (h)
3231 r = omap_hwmod_register_links(h);
3232 if (r < 0)
3233 return r;
3234
3235 /*
3236 * DSS code presumes that dss_core hwmod is handled first,
3237 * _before_ any other DSS related hwmods so register common
3238 * DSS hwmod links last to ensure that dss_core is already
3239 * registered. Otherwise some change things may happen, for
3240 * ex. if dispc is handled before dss_core and DSS is enabled
3241 * in bootloader DISPC will be reset with outputs enabled
3242 * which sometimes leads to unrecoverable L3 error. XXX The
3243 * long-term fix to this is to ensure hwmods are set up in
3244 * dependency order in the hwmod core code.
3245 */
3246 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3247
3248 return r;
3249 }
Linux with added FPC-III support