| blob | 02f32cbf67893f0154fbd866e664ba97c92d28fe |
1 [
2 {
3 "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
4 "EventCode": "0xAE",
5 "Counter": "0,1,2,3",
6 "UMask": "0x1",
7 "EventName": "ITLB.ITLB_FLUSH",
8 "SampleAfterValue": "100007",
9 "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
10 "CounterHTOff": "0,1,2,3,4,5,6,7"
11 },
12 {
13 "EventCode": "0x4F",
14 "Counter": "0,1,2,3",
15 "UMask": "0x10",
16 "EventName": "EPT.WALK_PENDING",
17 "SampleAfterValue": "2000003",
18 "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
19 "CounterHTOff": "0,1,2,3,4,5,6,7"
20 },
21 {
22 "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
23 "EventCode": "0x85",
24 "Counter": "0,1,2,3",
25 "UMask": "0x1",
26 "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
27 "SampleAfterValue": "100003",
28 "BriefDescription": "Misses at all ITLB levels that cause page walks",
29 "CounterHTOff": "0,1,2,3,4,5,6,7"
30 },
31 {
32 "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
33 "EventCode": "0x85",
34 "Counter": "0,1,2,3",
35 "UMask": "0x2",
36 "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
37 "SampleAfterValue": "100003",
38 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
39 "CounterHTOff": "0,1,2,3,4,5,6,7"
40 },
41 {
42 "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
43 "EventCode": "0x85",
44 "Counter": "0,1,2,3",
45 "UMask": "0x4",
46 "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
47 "SampleAfterValue": "100003",
48 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
49 "CounterHTOff": "0,1,2,3,4,5,6,7"
50 },
51 {
52 "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
53 "EventCode": "0x85",
54 "Counter": "0,1,2,3",
55 "UMask": "0x8",
56 "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
57 "SampleAfterValue": "100003",
58 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
59 "CounterHTOff": "0,1,2,3,4,5,6,7"
60 },
61 {
62 "EventCode": "0x85",
63 "Counter": "0,1,2,3",
64 "UMask": "0x10",
65 "EventName": "ITLB_MISSES.WALK_PENDING",
66 "SampleAfterValue": "100003",
67 "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake. ",
68 "CounterHTOff": "0,1,2,3,4,5,6,7"
69 },
70 {
71 "EventCode": "0x85",
72 "Counter": "0,1,2,3",
73 "UMask": "0x20",
74 "EventName": "ITLB_MISSES.STLB_HIT",
75 "SampleAfterValue": "100003",
76 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
77 "CounterHTOff": "0,1,2,3,4,5,6,7"
78 },
79 {
80 "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
81 "EventCode": "0x08",
82 "Counter": "0,1,2,3",
83 "UMask": "0x1",
84 "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
85 "SampleAfterValue": "100003",
86 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
87 "CounterHTOff": "0,1,2,3,4,5,6,7"
88 },
89 {
90 "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
91 "EventCode": "0x08",
92 "Counter": "0,1,2,3",
93 "UMask": "0x2",
94 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
95 "SampleAfterValue": "2000003",
96 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
97 "CounterHTOff": "0,1,2,3,4,5,6,7"
98 },
99 {
100 "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
101 "EventCode": "0x08",
102 "Counter": "0,1,2,3",
103 "UMask": "0x4",
104 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
105 "SampleAfterValue": "2000003",
106 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
107 "CounterHTOff": "0,1,2,3,4,5,6,7"
108 },
109 {
110 "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
111 "EventCode": "0x08",
112 "Counter": "0,1,2,3",
113 "UMask": "0x8",
114 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
115 "SampleAfterValue": "2000003",
116 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
117 "CounterHTOff": "0,1,2,3,4,5,6,7"
118 },
119 {
120 "EventCode": "0x08",
121 "Counter": "0,1,2,3",
122 "UMask": "0x10",
123 "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
124 "SampleAfterValue": "2000003",
125 "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake. ",
126 "CounterHTOff": "0,1,2,3,4,5,6,7"
127 },
128 {
129 "EventCode": "0x08",
130 "Counter": "0,1,2,3",
131 "UMask": "0x20",
132 "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
133 "SampleAfterValue": "2000003",
134 "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
135 "CounterHTOff": "0,1,2,3,4,5,6,7"
136 },
137 {
138 "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
139 "EventCode": "0x49",
140 "Counter": "0,1,2,3",
141 "UMask": "0x1",
142 "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
143 "SampleAfterValue": "100003",
144 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
145 "CounterHTOff": "0,1,2,3,4,5,6,7"
146 },
147 {
148 "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
149 "EventCode": "0x49",
150 "Counter": "0,1,2,3",
151 "UMask": "0x2",
152 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
153 "SampleAfterValue": "100003",
154 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
155 "CounterHTOff": "0,1,2,3,4,5,6,7"
156 },
157 {
158 "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
159 "EventCode": "0x49",
160 "Counter": "0,1,2,3",
161 "UMask": "0x4",
162 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
163 "SampleAfterValue": "100003",
164 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
165 "CounterHTOff": "0,1,2,3,4,5,6,7"
166 },
167 {
168 "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
169 "EventCode": "0x49",
170 "Counter": "0,1,2,3",
171 "UMask": "0x8",
172 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
173 "SampleAfterValue": "100003",
174 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
175 "CounterHTOff": "0,1,2,3,4,5,6,7"
176 },
177 {
178 "EventCode": "0x49",
179 "Counter": "0,1,2,3",
180 "UMask": "0x10",
181 "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
182 "SampleAfterValue": "2000003",
183 "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake. ",
184 "CounterHTOff": "0,1,2,3,4,5,6,7"
185 },
186 {
187 "EventCode": "0x49",
188 "Counter": "0,1,2,3",
189 "UMask": "0x20",
190 "EventName": "DTLB_STORE_MISSES.STLB_HIT",
191 "SampleAfterValue": "100003",
192 "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
193 "CounterHTOff": "0,1,2,3,4,5,6,7"
194 },
195 {
196 "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
197 "EventCode": "0xBD",
198 "Counter": "0,1,2,3",
199 "UMask": "0x1",
200 "EventName": "TLB_FLUSH.DTLB_THREAD",
201 "SampleAfterValue": "100007",
202 "BriefDescription": "DTLB flush attempts of the thread-specific entries",
203 "CounterHTOff": "0,1,2,3,4,5,6,7"
204 },
205 {
206 "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",
207 "EventCode": "0xBD",
208 "Counter": "0,1,2,3",
209 "UMask": "0x20",
210 "EventName": "TLB_FLUSH.STLB_ANY",
211 "SampleAfterValue": "100007",
212 "BriefDescription": "STLB flush attempts",
213 "CounterHTOff": "0,1,2,3,4,5,6,7"
214 },
215 {
216 "EventCode": "0x85",
217 "Counter": "0,1,2,3",
218 "UMask": "0xe",
219 "EventName": "ITLB_MISSES.WALK_COMPLETED",
220 "SampleAfterValue": "100003",
221 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
222 "CounterHTOff": "0,1,2,3,4,5,6,7"
223 },
224 {
225 "EventCode": "0x08",
226 "Counter": "0,1,2,3",
227 "UMask": "0xe",
228 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
229 "SampleAfterValue": "100003",
230 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
231 "CounterHTOff": "0,1,2,3,4,5,6,7"
232 },
233 {
234 "EventCode": "0x49",
235 "Counter": "0,1,2,3",
236 "UMask": "0xe",
237 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
238 "SampleAfterValue": "100003",
239 "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
240 "CounterHTOff": "0,1,2,3,4,5,6,7"
241 },
242 {
243 "EventCode": "0x49",
244 "Counter": "0,1,2,3",
245 "UMask": "0x10",
246 "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
247 "SampleAfterValue": "100003",
248 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake. ",
249 "CounterMask": "1",
250 "CounterHTOff": "0,1,2,3,4,5,6,7"
251 },
252 {
253 "EventCode": "0x08",
254 "Counter": "0,1,2,3",
255 "UMask": "0x10",
256 "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
257 "SampleAfterValue": "100003",
258 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake. ",
259 "CounterMask": "1",
260 "CounterHTOff": "0,1,2,3,4,5,6,7"
261 },
262 {
263 "EventCode": "0x85",
264 "Counter": "0,1,2,3",
265 "UMask": "0x10",
266 "EventName": "ITLB_MISSES.WALK_ACTIVE",
267 "SampleAfterValue": "100003",
268 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
269 "CounterMask": "1",
270 "CounterHTOff": "0,1,2,3,4,5,6,7"
271 }
272 ]