target/cxgbit: Use T6 specific macros to get ETH/IP hdr len
[linux/fpc-iii.git] / tools / perf / pmu-events / arch / x86 / westmereex / floating-point.json
blob7d2f71a9dee3ef04934087f1e645557335192af9
2     {
3         "PEBS": "1",
4         "EventCode": "0xF7",
5         "Counter": "0,1,2,3",
6         "UMask": "0x1",
7         "EventName": "FP_ASSIST.ALL",
8         "SampleAfterValue": "20000",
9         "BriefDescription": "X87 Floating point assists (Precise Event)"
10     },
11     {
12         "PEBS": "1",
13         "EventCode": "0xF7",
14         "Counter": "0,1,2,3",
15         "UMask": "0x4",
16         "EventName": "FP_ASSIST.INPUT",
17         "SampleAfterValue": "20000",
18         "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)"
19     },
20     {
21         "PEBS": "1",
22         "EventCode": "0xF7",
23         "Counter": "0,1,2,3",
24         "UMask": "0x2",
25         "EventName": "FP_ASSIST.OUTPUT",
26         "SampleAfterValue": "20000",
27         "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)"
28     },
29     {
30         "EventCode": "0x10",
31         "Counter": "0,1,2,3",
32         "UMask": "0x2",
33         "EventName": "FP_COMP_OPS_EXE.MMX",
34         "SampleAfterValue": "2000000",
35         "BriefDescription": "MMX Uops"
36     },
37     {
38         "EventCode": "0x10",
39         "Counter": "0,1,2,3",
40         "UMask": "0x80",
41         "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
42         "SampleAfterValue": "2000000",
43         "BriefDescription": "SSE* FP double precision Uops"
44     },
45     {
46         "EventCode": "0x10",
47         "Counter": "0,1,2,3",
48         "UMask": "0x4",
49         "EventName": "FP_COMP_OPS_EXE.SSE_FP",
50         "SampleAfterValue": "2000000",
51         "BriefDescription": "SSE and SSE2 FP Uops"
52     },
53     {
54         "EventCode": "0x10",
55         "Counter": "0,1,2,3",
56         "UMask": "0x10",
57         "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
58         "SampleAfterValue": "2000000",
59         "BriefDescription": "SSE FP packed Uops"
60     },
61     {
62         "EventCode": "0x10",
63         "Counter": "0,1,2,3",
64         "UMask": "0x20",
65         "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
66         "SampleAfterValue": "2000000",
67         "BriefDescription": "SSE FP scalar Uops"
68     },
69     {
70         "EventCode": "0x10",
71         "Counter": "0,1,2,3",
72         "UMask": "0x40",
73         "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
74         "SampleAfterValue": "2000000",
75         "BriefDescription": "SSE* FP single precision Uops"
76     },
77     {
78         "EventCode": "0x10",
79         "Counter": "0,1,2,3",
80         "UMask": "0x8",
81         "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
82         "SampleAfterValue": "2000000",
83         "BriefDescription": "SSE2 integer Uops"
84     },
85     {
86         "EventCode": "0x10",
87         "Counter": "0,1,2,3",
88         "UMask": "0x1",
89         "EventName": "FP_COMP_OPS_EXE.X87",
90         "SampleAfterValue": "2000000",
91         "BriefDescription": "Computational floating-point operations executed"
92     },
93     {
94         "EventCode": "0xCC",
95         "Counter": "0,1,2,3",
96         "UMask": "0x3",
97         "EventName": "FP_MMX_TRANS.ANY",
98         "SampleAfterValue": "2000000",
99         "BriefDescription": "All Floating Point to and from MMX transitions"
100     },
101     {
102         "EventCode": "0xCC",
103         "Counter": "0,1,2,3",
104         "UMask": "0x1",
105         "EventName": "FP_MMX_TRANS.TO_FP",
106         "SampleAfterValue": "2000000",
107         "BriefDescription": "Transitions from MMX to Floating Point instructions"
108     },
109     {
110         "EventCode": "0xCC",
111         "Counter": "0,1,2,3",
112         "UMask": "0x2",
113         "EventName": "FP_MMX_TRANS.TO_MMX",
114         "SampleAfterValue": "2000000",
115         "BriefDescription": "Transitions from Floating Point to MMX instructions"
116     },
117     {
118         "EventCode": "0x12",
119         "Counter": "0,1,2,3",
120         "UMask": "0x4",
121         "EventName": "SIMD_INT_128.PACK",
122         "SampleAfterValue": "200000",
123         "BriefDescription": "128 bit SIMD integer pack operations"
124     },
125     {
126         "EventCode": "0x12",
127         "Counter": "0,1,2,3",
128         "UMask": "0x20",
129         "EventName": "SIMD_INT_128.PACKED_ARITH",
130         "SampleAfterValue": "200000",
131         "BriefDescription": "128 bit SIMD integer arithmetic operations"
132     },
133     {
134         "EventCode": "0x12",
135         "Counter": "0,1,2,3",
136         "UMask": "0x10",
137         "EventName": "SIMD_INT_128.PACKED_LOGICAL",
138         "SampleAfterValue": "200000",
139         "BriefDescription": "128 bit SIMD integer logical operations"
140     },
141     {
142         "EventCode": "0x12",
143         "Counter": "0,1,2,3",
144         "UMask": "0x1",
145         "EventName": "SIMD_INT_128.PACKED_MPY",
146         "SampleAfterValue": "200000",
147         "BriefDescription": "128 bit SIMD integer multiply operations"
148     },
149     {
150         "EventCode": "0x12",
151         "Counter": "0,1,2,3",
152         "UMask": "0x2",
153         "EventName": "SIMD_INT_128.PACKED_SHIFT",
154         "SampleAfterValue": "200000",
155         "BriefDescription": "128 bit SIMD integer shift operations"
156     },
157     {
158         "EventCode": "0x12",
159         "Counter": "0,1,2,3",
160         "UMask": "0x40",
161         "EventName": "SIMD_INT_128.SHUFFLE_MOVE",
162         "SampleAfterValue": "200000",
163         "BriefDescription": "128 bit SIMD integer shuffle/move operations"
164     },
165     {
166         "EventCode": "0x12",
167         "Counter": "0,1,2,3",
168         "UMask": "0x8",
169         "EventName": "SIMD_INT_128.UNPACK",
170         "SampleAfterValue": "200000",
171         "BriefDescription": "128 bit SIMD integer unpack operations"
172     },
173     {
174         "EventCode": "0xFD",
175         "Counter": "0,1,2,3",
176         "UMask": "0x4",
177         "EventName": "SIMD_INT_64.PACK",
178         "SampleAfterValue": "200000",
179         "BriefDescription": "SIMD integer 64 bit pack operations"
180     },
181     {
182         "EventCode": "0xFD",
183         "Counter": "0,1,2,3",
184         "UMask": "0x20",
185         "EventName": "SIMD_INT_64.PACKED_ARITH",
186         "SampleAfterValue": "200000",
187         "BriefDescription": "SIMD integer 64 bit arithmetic operations"
188     },
189     {
190         "EventCode": "0xFD",
191         "Counter": "0,1,2,3",
192         "UMask": "0x10",
193         "EventName": "SIMD_INT_64.PACKED_LOGICAL",
194         "SampleAfterValue": "200000",
195         "BriefDescription": "SIMD integer 64 bit logical operations"
196     },
197     {
198         "EventCode": "0xFD",
199         "Counter": "0,1,2,3",
200         "UMask": "0x1",
201         "EventName": "SIMD_INT_64.PACKED_MPY",
202         "SampleAfterValue": "200000",
203         "BriefDescription": "SIMD integer 64 bit packed multiply operations"
204     },
205     {
206         "EventCode": "0xFD",
207         "Counter": "0,1,2,3",
208         "UMask": "0x2",
209         "EventName": "SIMD_INT_64.PACKED_SHIFT",
210         "SampleAfterValue": "200000",
211         "BriefDescription": "SIMD integer 64 bit shift operations"
212     },
213     {
214         "EventCode": "0xFD",
215         "Counter": "0,1,2,3",
216         "UMask": "0x40",
217         "EventName": "SIMD_INT_64.SHUFFLE_MOVE",
218         "SampleAfterValue": "200000",
219         "BriefDescription": "SIMD integer 64 bit shuffle/move operations"
220     },
221     {
222         "EventCode": "0xFD",
223         "Counter": "0,1,2,3",
224         "UMask": "0x8",
225         "EventName": "SIMD_INT_64.UNPACK",
226         "SampleAfterValue": "200000",
227         "BriefDescription": "SIMD integer 64 bit unpack operations"
228     }