2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <linux/amd-iommu.h>
28 #include <linux/export.h>
29 #include <asm/pci-direct.h>
30 #include <asm/iommu.h>
32 #include <asm/x86_init.h>
33 #include <asm/iommu_table.h>
35 #include "amd_iommu_proto.h"
36 #include "amd_iommu_types.h"
39 * definitions for the ACPI scanning code
41 #define IVRS_HEADER_LENGTH 48
43 #define ACPI_IVHD_TYPE 0x10
44 #define ACPI_IVMD_TYPE_ALL 0x20
45 #define ACPI_IVMD_TYPE 0x21
46 #define ACPI_IVMD_TYPE_RANGE 0x22
48 #define IVHD_DEV_ALL 0x01
49 #define IVHD_DEV_SELECT 0x02
50 #define IVHD_DEV_SELECT_RANGE_START 0x03
51 #define IVHD_DEV_RANGE_END 0x04
52 #define IVHD_DEV_ALIAS 0x42
53 #define IVHD_DEV_ALIAS_RANGE 0x43
54 #define IVHD_DEV_EXT_SELECT 0x46
55 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
57 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
58 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
59 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
60 #define IVHD_FLAG_ISOC_EN_MASK 0x08
62 #define IVMD_FLAG_EXCL_RANGE 0x08
63 #define IVMD_FLAG_UNITY_MAP 0x01
65 #define ACPI_DEVFLAG_INITPASS 0x01
66 #define ACPI_DEVFLAG_EXTINT 0x02
67 #define ACPI_DEVFLAG_NMI 0x04
68 #define ACPI_DEVFLAG_SYSMGT1 0x10
69 #define ACPI_DEVFLAG_SYSMGT2 0x20
70 #define ACPI_DEVFLAG_LINT0 0x40
71 #define ACPI_DEVFLAG_LINT1 0x80
72 #define ACPI_DEVFLAG_ATSDIS 0x10000000
75 * ACPI table definitions
77 * These data structures are laid over the table to parse the important values
82 * structure describing one IOMMU in the ACPI table. Typically followed by one
83 * or more ivhd_entrys.
95 } __attribute__((packed
));
98 * A device entry describing which devices a specific IOMMU translates and
99 * which requestor ids they use.
106 } __attribute__((packed
));
109 * An AMD IOMMU memory definition structure. It defines things like exclusion
110 * ranges for devices and regions that should be unity mapped.
121 } __attribute__((packed
));
125 static int __initdata amd_iommu_detected
;
126 static bool __initdata amd_iommu_disabled
;
128 u16 amd_iommu_last_bdf
; /* largest PCI device id we have
130 LIST_HEAD(amd_iommu_unity_map
); /* a list of required unity mappings
132 bool amd_iommu_unmap_flush
; /* if true, flush on every unmap */
134 LIST_HEAD(amd_iommu_list
); /* list of all AMD IOMMUs in the
137 /* Array to assign indices to IOMMUs*/
138 struct amd_iommu
*amd_iommus
[MAX_IOMMUS
];
139 int amd_iommus_present
;
141 /* IOMMUs have a non-present cache? */
142 bool amd_iommu_np_cache __read_mostly
;
143 bool amd_iommu_iotlb_sup __read_mostly
= true;
145 u32 amd_iommu_max_pasids __read_mostly
= ~0;
147 bool amd_iommu_v2_present __read_mostly
;
149 bool amd_iommu_force_isolation __read_mostly
;
152 * The ACPI table parsing functions set this variable on an error
154 static int __initdata amd_iommu_init_err
;
157 * List of protection domains - used during resume
159 LIST_HEAD(amd_iommu_pd_list
);
160 spinlock_t amd_iommu_pd_lock
;
163 * Pointer to the device table which is shared by all AMD IOMMUs
164 * it is indexed by the PCI device id or the HT unit id and contains
165 * information about the domain the device belongs to as well as the
166 * page table root pointer.
168 struct dev_table_entry
*amd_iommu_dev_table
;
171 * The alias table is a driver specific data structure which contains the
172 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
173 * More than one device can share the same requestor id.
175 u16
*amd_iommu_alias_table
;
178 * The rlookup table is used to find the IOMMU which is responsible
179 * for a specific device. It is also indexed by the PCI device id.
181 struct amd_iommu
**amd_iommu_rlookup_table
;
184 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
185 * to know which ones are already in use.
187 unsigned long *amd_iommu_pd_alloc_bitmap
;
189 static u32 dev_table_size
; /* size of the device table */
190 static u32 alias_table_size
; /* size of the alias table */
191 static u32 rlookup_table_size
; /* size if the rlookup table */
194 * This function flushes all internal caches of
195 * the IOMMU used by this driver.
197 extern void iommu_flush_all_caches(struct amd_iommu
*iommu
);
199 static inline void update_last_devid(u16 devid
)
201 if (devid
> amd_iommu_last_bdf
)
202 amd_iommu_last_bdf
= devid
;
205 static inline unsigned long tbl_size(int entry_size
)
207 unsigned shift
= PAGE_SHIFT
+
208 get_order(((int)amd_iommu_last_bdf
+ 1) * entry_size
);
213 /* Access to l1 and l2 indexed register spaces */
215 static u32
iommu_read_l1(struct amd_iommu
*iommu
, u16 l1
, u8 address
)
219 pci_write_config_dword(iommu
->dev
, 0xf8, (address
| l1
<< 16));
220 pci_read_config_dword(iommu
->dev
, 0xfc, &val
);
224 static void iommu_write_l1(struct amd_iommu
*iommu
, u16 l1
, u8 address
, u32 val
)
226 pci_write_config_dword(iommu
->dev
, 0xf8, (address
| l1
<< 16 | 1 << 31));
227 pci_write_config_dword(iommu
->dev
, 0xfc, val
);
228 pci_write_config_dword(iommu
->dev
, 0xf8, (address
| l1
<< 16));
231 static u32
iommu_read_l2(struct amd_iommu
*iommu
, u8 address
)
235 pci_write_config_dword(iommu
->dev
, 0xf0, address
);
236 pci_read_config_dword(iommu
->dev
, 0xf4, &val
);
240 static void iommu_write_l2(struct amd_iommu
*iommu
, u8 address
, u32 val
)
242 pci_write_config_dword(iommu
->dev
, 0xf0, (address
| 1 << 8));
243 pci_write_config_dword(iommu
->dev
, 0xf4, val
);
246 /****************************************************************************
248 * AMD IOMMU MMIO register space handling functions
250 * These functions are used to program the IOMMU device registers in
251 * MMIO space required for that driver.
253 ****************************************************************************/
256 * This function set the exclusion range in the IOMMU. DMA accesses to the
257 * exclusion range are passed through untranslated
259 static void iommu_set_exclusion_range(struct amd_iommu
*iommu
)
261 u64 start
= iommu
->exclusion_start
& PAGE_MASK
;
262 u64 limit
= (start
+ iommu
->exclusion_length
) & PAGE_MASK
;
265 if (!iommu
->exclusion_start
)
268 entry
= start
| MMIO_EXCL_ENABLE_MASK
;
269 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_BASE_OFFSET
,
270 &entry
, sizeof(entry
));
273 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_LIMIT_OFFSET
,
274 &entry
, sizeof(entry
));
277 /* Programs the physical address of the device table into the IOMMU hardware */
278 static void __init
iommu_set_device_table(struct amd_iommu
*iommu
)
282 BUG_ON(iommu
->mmio_base
== NULL
);
284 entry
= virt_to_phys(amd_iommu_dev_table
);
285 entry
|= (dev_table_size
>> 12) - 1;
286 memcpy_toio(iommu
->mmio_base
+ MMIO_DEV_TABLE_OFFSET
,
287 &entry
, sizeof(entry
));
290 /* Generic functions to enable/disable certain features of the IOMMU. */
291 static void iommu_feature_enable(struct amd_iommu
*iommu
, u8 bit
)
295 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
297 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
300 static void iommu_feature_disable(struct amd_iommu
*iommu
, u8 bit
)
304 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
306 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
309 static void iommu_set_inv_tlb_timeout(struct amd_iommu
*iommu
, int timeout
)
313 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
314 ctrl
&= ~CTRL_INV_TO_MASK
;
315 ctrl
|= (timeout
<< CONTROL_INV_TIMEOUT
) & CTRL_INV_TO_MASK
;
316 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
319 /* Function to enable the hardware */
320 static void iommu_enable(struct amd_iommu
*iommu
)
322 static const char * const feat_str
[] = {
323 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
324 "IA", "GA", "HE", "PC", NULL
328 printk(KERN_INFO
"AMD-Vi: Enabling IOMMU at %s cap 0x%hx",
329 dev_name(&iommu
->dev
->dev
), iommu
->cap_ptr
);
331 if (iommu
->cap
& (1 << IOMMU_CAP_EFR
)) {
332 printk(KERN_CONT
" extended features: ");
333 for (i
= 0; feat_str
[i
]; ++i
)
334 if (iommu_feature(iommu
, (1ULL << i
)))
335 printk(KERN_CONT
" %s", feat_str
[i
]);
337 printk(KERN_CONT
"\n");
339 iommu_feature_enable(iommu
, CONTROL_IOMMU_EN
);
342 static void iommu_disable(struct amd_iommu
*iommu
)
344 /* Disable command buffer */
345 iommu_feature_disable(iommu
, CONTROL_CMDBUF_EN
);
347 /* Disable event logging and event interrupts */
348 iommu_feature_disable(iommu
, CONTROL_EVT_INT_EN
);
349 iommu_feature_disable(iommu
, CONTROL_EVT_LOG_EN
);
351 /* Disable IOMMU hardware itself */
352 iommu_feature_disable(iommu
, CONTROL_IOMMU_EN
);
356 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
357 * the system has one.
359 static u8
* __init
iommu_map_mmio_space(u64 address
)
363 if (!request_mem_region(address
, MMIO_REGION_LENGTH
, "amd_iommu")) {
364 pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
366 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
370 ret
= ioremap_nocache(address
, MMIO_REGION_LENGTH
);
374 release_mem_region(address
, MMIO_REGION_LENGTH
);
379 static void __init
iommu_unmap_mmio_space(struct amd_iommu
*iommu
)
381 if (iommu
->mmio_base
)
382 iounmap(iommu
->mmio_base
);
383 release_mem_region(iommu
->mmio_phys
, MMIO_REGION_LENGTH
);
386 /****************************************************************************
388 * The functions below belong to the first pass of AMD IOMMU ACPI table
389 * parsing. In this pass we try to find out the highest device id this
390 * code has to handle. Upon this information the size of the shared data
391 * structures is determined later.
393 ****************************************************************************/
396 * This function calculates the length of a given IVHD entry
398 static inline int ivhd_entry_length(u8
*ivhd
)
400 return 0x04 << (*ivhd
>> 6);
404 * This function reads the last device id the IOMMU has to handle from the PCI
405 * capability header for this IOMMU
407 static int __init
find_last_devid_on_pci(int bus
, int dev
, int fn
, int cap_ptr
)
411 cap
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_RANGE_OFFSET
);
412 update_last_devid(calc_devid(MMIO_GET_BUS(cap
), MMIO_GET_LD(cap
)));
418 * After reading the highest device id from the IOMMU PCI capability header
419 * this function looks if there is a higher device id defined in the ACPI table
421 static int __init
find_last_devid_from_ivhd(struct ivhd_header
*h
)
423 u8
*p
= (void *)h
, *end
= (void *)h
;
424 struct ivhd_entry
*dev
;
429 find_last_devid_on_pci(PCI_BUS(h
->devid
),
435 dev
= (struct ivhd_entry
*)p
;
437 case IVHD_DEV_SELECT
:
438 case IVHD_DEV_RANGE_END
:
440 case IVHD_DEV_EXT_SELECT
:
441 /* all the above subfield types refer to device ids */
442 update_last_devid(dev
->devid
);
447 p
+= ivhd_entry_length(p
);
456 * Iterate over all IVHD entries in the ACPI table and find the highest device
457 * id which we need to handle. This is the first of three functions which parse
458 * the ACPI table. So we check the checksum here.
460 static int __init
find_last_devid_acpi(struct acpi_table_header
*table
)
463 u8 checksum
= 0, *p
= (u8
*)table
, *end
= (u8
*)table
;
464 struct ivhd_header
*h
;
467 * Validate checksum here so we don't need to do it when
468 * we actually parse the table
470 for (i
= 0; i
< table
->length
; ++i
)
473 /* ACPI table corrupt */
474 amd_iommu_init_err
= -ENODEV
;
478 p
+= IVRS_HEADER_LENGTH
;
480 end
+= table
->length
;
482 h
= (struct ivhd_header
*)p
;
485 find_last_devid_from_ivhd(h
);
497 /****************************************************************************
499 * The following functions belong the the code path which parses the ACPI table
500 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
501 * data structures, initialize the device/alias/rlookup table and also
502 * basically initialize the hardware.
504 ****************************************************************************/
507 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
508 * write commands to that buffer later and the IOMMU will execute them
511 static u8
* __init
alloc_command_buffer(struct amd_iommu
*iommu
)
513 u8
*cmd_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
514 get_order(CMD_BUFFER_SIZE
));
519 iommu
->cmd_buf_size
= CMD_BUFFER_SIZE
| CMD_BUFFER_UNINITIALIZED
;
525 * This function resets the command buffer if the IOMMU stopped fetching
528 void amd_iommu_reset_cmd_buffer(struct amd_iommu
*iommu
)
530 iommu_feature_disable(iommu
, CONTROL_CMDBUF_EN
);
532 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
533 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
535 iommu_feature_enable(iommu
, CONTROL_CMDBUF_EN
);
539 * This function writes the command buffer address to the hardware and
542 static void iommu_enable_command_buffer(struct amd_iommu
*iommu
)
546 BUG_ON(iommu
->cmd_buf
== NULL
);
548 entry
= (u64
)virt_to_phys(iommu
->cmd_buf
);
549 entry
|= MMIO_CMD_SIZE_512
;
551 memcpy_toio(iommu
->mmio_base
+ MMIO_CMD_BUF_OFFSET
,
552 &entry
, sizeof(entry
));
554 amd_iommu_reset_cmd_buffer(iommu
);
555 iommu
->cmd_buf_size
&= ~(CMD_BUFFER_UNINITIALIZED
);
558 static void __init
free_command_buffer(struct amd_iommu
*iommu
)
560 free_pages((unsigned long)iommu
->cmd_buf
,
561 get_order(iommu
->cmd_buf_size
& ~(CMD_BUFFER_UNINITIALIZED
)));
564 /* allocates the memory where the IOMMU will log its events to */
565 static u8
* __init
alloc_event_buffer(struct amd_iommu
*iommu
)
567 iommu
->evt_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
568 get_order(EVT_BUFFER_SIZE
));
570 if (iommu
->evt_buf
== NULL
)
573 iommu
->evt_buf_size
= EVT_BUFFER_SIZE
;
575 return iommu
->evt_buf
;
578 static void iommu_enable_event_buffer(struct amd_iommu
*iommu
)
582 BUG_ON(iommu
->evt_buf
== NULL
);
584 entry
= (u64
)virt_to_phys(iommu
->evt_buf
) | EVT_LEN_MASK
;
586 memcpy_toio(iommu
->mmio_base
+ MMIO_EVT_BUF_OFFSET
,
587 &entry
, sizeof(entry
));
589 /* set head and tail to zero manually */
590 writel(0x00, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
591 writel(0x00, iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
593 iommu_feature_enable(iommu
, CONTROL_EVT_LOG_EN
);
596 static void __init
free_event_buffer(struct amd_iommu
*iommu
)
598 free_pages((unsigned long)iommu
->evt_buf
, get_order(EVT_BUFFER_SIZE
));
601 /* allocates the memory where the IOMMU will log its events to */
602 static u8
* __init
alloc_ppr_log(struct amd_iommu
*iommu
)
604 iommu
->ppr_log
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
605 get_order(PPR_LOG_SIZE
));
607 if (iommu
->ppr_log
== NULL
)
610 return iommu
->ppr_log
;
613 static void iommu_enable_ppr_log(struct amd_iommu
*iommu
)
617 if (iommu
->ppr_log
== NULL
)
620 entry
= (u64
)virt_to_phys(iommu
->ppr_log
) | PPR_LOG_SIZE_512
;
622 memcpy_toio(iommu
->mmio_base
+ MMIO_PPR_LOG_OFFSET
,
623 &entry
, sizeof(entry
));
625 /* set head and tail to zero manually */
626 writel(0x00, iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
627 writel(0x00, iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
629 iommu_feature_enable(iommu
, CONTROL_PPFLOG_EN
);
630 iommu_feature_enable(iommu
, CONTROL_PPR_EN
);
633 static void __init
free_ppr_log(struct amd_iommu
*iommu
)
635 if (iommu
->ppr_log
== NULL
)
638 free_pages((unsigned long)iommu
->ppr_log
, get_order(PPR_LOG_SIZE
));
641 static void iommu_enable_gt(struct amd_iommu
*iommu
)
643 if (!iommu_feature(iommu
, FEATURE_GT
))
646 iommu_feature_enable(iommu
, CONTROL_GT_EN
);
649 /* sets a specific bit in the device table entry. */
650 static void set_dev_entry_bit(u16 devid
, u8 bit
)
652 int i
= (bit
>> 6) & 0x03;
653 int _bit
= bit
& 0x3f;
655 amd_iommu_dev_table
[devid
].data
[i
] |= (1UL << _bit
);
658 static int get_dev_entry_bit(u16 devid
, u8 bit
)
660 int i
= (bit
>> 6) & 0x03;
661 int _bit
= bit
& 0x3f;
663 return (amd_iommu_dev_table
[devid
].data
[i
] & (1UL << _bit
)) >> _bit
;
667 void amd_iommu_apply_erratum_63(u16 devid
)
671 sysmgt
= get_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
) |
672 (get_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
) << 1);
675 set_dev_entry_bit(devid
, DEV_ENTRY_IW
);
678 /* Writes the specific IOMMU for a device into the rlookup table */
679 static void __init
set_iommu_for_device(struct amd_iommu
*iommu
, u16 devid
)
681 amd_iommu_rlookup_table
[devid
] = iommu
;
685 * This function takes the device specific flags read from the ACPI
686 * table and sets up the device table entry with that information
688 static void __init
set_dev_entry_from_acpi(struct amd_iommu
*iommu
,
689 u16 devid
, u32 flags
, u32 ext_flags
)
691 if (flags
& ACPI_DEVFLAG_INITPASS
)
692 set_dev_entry_bit(devid
, DEV_ENTRY_INIT_PASS
);
693 if (flags
& ACPI_DEVFLAG_EXTINT
)
694 set_dev_entry_bit(devid
, DEV_ENTRY_EINT_PASS
);
695 if (flags
& ACPI_DEVFLAG_NMI
)
696 set_dev_entry_bit(devid
, DEV_ENTRY_NMI_PASS
);
697 if (flags
& ACPI_DEVFLAG_SYSMGT1
)
698 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
);
699 if (flags
& ACPI_DEVFLAG_SYSMGT2
)
700 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
);
701 if (flags
& ACPI_DEVFLAG_LINT0
)
702 set_dev_entry_bit(devid
, DEV_ENTRY_LINT0_PASS
);
703 if (flags
& ACPI_DEVFLAG_LINT1
)
704 set_dev_entry_bit(devid
, DEV_ENTRY_LINT1_PASS
);
706 amd_iommu_apply_erratum_63(devid
);
708 set_iommu_for_device(iommu
, devid
);
712 * Reads the device exclusion range from ACPI and initialize IOMMU with
715 static void __init
set_device_exclusion_range(u16 devid
, struct ivmd_header
*m
)
717 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
719 if (!(m
->flags
& IVMD_FLAG_EXCL_RANGE
))
724 * We only can configure exclusion ranges per IOMMU, not
725 * per device. But we can enable the exclusion range per
726 * device. This is done here
728 set_dev_entry_bit(m
->devid
, DEV_ENTRY_EX
);
729 iommu
->exclusion_start
= m
->range_start
;
730 iommu
->exclusion_length
= m
->range_length
;
735 * This function reads some important data from the IOMMU PCI space and
736 * initializes the driver data structure with it. It reads the hardware
737 * capabilities and the first/last device entries
739 static void __init
init_iommu_from_pci(struct amd_iommu
*iommu
)
741 int cap_ptr
= iommu
->cap_ptr
;
742 u32 range
, misc
, low
, high
;
745 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_CAP_HDR_OFFSET
,
747 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_RANGE_OFFSET
,
749 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_MISC_OFFSET
,
752 iommu
->first_device
= calc_devid(MMIO_GET_BUS(range
),
754 iommu
->last_device
= calc_devid(MMIO_GET_BUS(range
),
756 iommu
->evt_msi_num
= MMIO_MSI_NUM(misc
);
758 if (!(iommu
->cap
& (1 << IOMMU_CAP_IOTLB
)))
759 amd_iommu_iotlb_sup
= false;
761 /* read extended feature bits */
762 low
= readl(iommu
->mmio_base
+ MMIO_EXT_FEATURES
);
763 high
= readl(iommu
->mmio_base
+ MMIO_EXT_FEATURES
+ 4);
765 iommu
->features
= ((u64
)high
<< 32) | low
;
767 if (iommu_feature(iommu
, FEATURE_GT
)) {
772 shift
= iommu
->features
& FEATURE_PASID_MASK
;
773 shift
>>= FEATURE_PASID_SHIFT
;
774 pasids
= (1 << shift
);
776 amd_iommu_max_pasids
= min(amd_iommu_max_pasids
, pasids
);
778 glxval
= iommu
->features
& FEATURE_GLXVAL_MASK
;
779 glxval
>>= FEATURE_GLXVAL_SHIFT
;
781 if (amd_iommu_max_glx_val
== -1)
782 amd_iommu_max_glx_val
= glxval
;
784 amd_iommu_max_glx_val
= min(amd_iommu_max_glx_val
, glxval
);
787 if (iommu_feature(iommu
, FEATURE_GT
) &&
788 iommu_feature(iommu
, FEATURE_PPR
)) {
789 iommu
->is_iommu_v2
= true;
790 amd_iommu_v2_present
= true;
793 if (!is_rd890_iommu(iommu
->dev
))
797 * Some rd890 systems may not be fully reconfigured by the BIOS, so
798 * it's necessary for us to store this information so it can be
799 * reprogrammed on resume
802 pci_read_config_dword(iommu
->dev
, iommu
->cap_ptr
+ 4,
803 &iommu
->stored_addr_lo
);
804 pci_read_config_dword(iommu
->dev
, iommu
->cap_ptr
+ 8,
805 &iommu
->stored_addr_hi
);
807 /* Low bit locks writes to configuration space */
808 iommu
->stored_addr_lo
&= ~1;
810 for (i
= 0; i
< 6; i
++)
811 for (j
= 0; j
< 0x12; j
++)
812 iommu
->stored_l1
[i
][j
] = iommu_read_l1(iommu
, i
, j
);
814 for (i
= 0; i
< 0x83; i
++)
815 iommu
->stored_l2
[i
] = iommu_read_l2(iommu
, i
);
819 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
820 * initializes the hardware and our data structures with it.
822 static void __init
init_iommu_from_acpi(struct amd_iommu
*iommu
,
823 struct ivhd_header
*h
)
826 u8
*end
= p
, flags
= 0;
827 u16 devid
= 0, devid_start
= 0, devid_to
= 0;
828 u32 dev_i
, ext_flags
= 0;
830 struct ivhd_entry
*e
;
833 * First save the recommended feature enable bits from ACPI
835 iommu
->acpi_flags
= h
->flags
;
838 * Done. Now parse the device entries
840 p
+= sizeof(struct ivhd_header
);
845 e
= (struct ivhd_entry
*)p
;
849 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
850 " last device %02x:%02x.%x flags: %02x\n",
851 PCI_BUS(iommu
->first_device
),
852 PCI_SLOT(iommu
->first_device
),
853 PCI_FUNC(iommu
->first_device
),
854 PCI_BUS(iommu
->last_device
),
855 PCI_SLOT(iommu
->last_device
),
856 PCI_FUNC(iommu
->last_device
),
859 for (dev_i
= iommu
->first_device
;
860 dev_i
<= iommu
->last_device
; ++dev_i
)
861 set_dev_entry_from_acpi(iommu
, dev_i
,
864 case IVHD_DEV_SELECT
:
866 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
874 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
876 case IVHD_DEV_SELECT_RANGE_START
:
878 DUMP_printk(" DEV_SELECT_RANGE_START\t "
879 "devid: %02x:%02x.%x flags: %02x\n",
885 devid_start
= e
->devid
;
892 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
893 "flags: %02x devid_to: %02x:%02x.%x\n",
898 PCI_BUS(e
->ext
>> 8),
899 PCI_SLOT(e
->ext
>> 8),
900 PCI_FUNC(e
->ext
>> 8));
903 devid_to
= e
->ext
>> 8;
904 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
905 set_dev_entry_from_acpi(iommu
, devid_to
, e
->flags
, 0);
906 amd_iommu_alias_table
[devid
] = devid_to
;
908 case IVHD_DEV_ALIAS_RANGE
:
910 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
911 "devid: %02x:%02x.%x flags: %02x "
912 "devid_to: %02x:%02x.%x\n",
917 PCI_BUS(e
->ext
>> 8),
918 PCI_SLOT(e
->ext
>> 8),
919 PCI_FUNC(e
->ext
>> 8));
921 devid_start
= e
->devid
;
923 devid_to
= e
->ext
>> 8;
927 case IVHD_DEV_EXT_SELECT
:
929 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
930 "flags: %02x ext: %08x\n",
937 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
,
940 case IVHD_DEV_EXT_SELECT_RANGE
:
942 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
943 "%02x:%02x.%x flags: %02x ext: %08x\n",
949 devid_start
= e
->devid
;
954 case IVHD_DEV_RANGE_END
:
956 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
962 for (dev_i
= devid_start
; dev_i
<= devid
; ++dev_i
) {
964 amd_iommu_alias_table
[dev_i
] = devid_to
;
965 set_dev_entry_from_acpi(iommu
,
966 devid_to
, flags
, ext_flags
);
968 set_dev_entry_from_acpi(iommu
, dev_i
,
976 p
+= ivhd_entry_length(p
);
980 /* Initializes the device->iommu mapping for the driver */
981 static int __init
init_iommu_devices(struct amd_iommu
*iommu
)
985 for (i
= iommu
->first_device
; i
<= iommu
->last_device
; ++i
)
986 set_iommu_for_device(iommu
, i
);
991 static void __init
free_iommu_one(struct amd_iommu
*iommu
)
993 free_command_buffer(iommu
);
994 free_event_buffer(iommu
);
996 iommu_unmap_mmio_space(iommu
);
999 static void __init
free_iommu_all(void)
1001 struct amd_iommu
*iommu
, *next
;
1003 for_each_iommu_safe(iommu
, next
) {
1004 list_del(&iommu
->list
);
1005 free_iommu_one(iommu
);
1011 * This function clues the initialization function for one IOMMU
1012 * together and also allocates the command buffer and programs the
1013 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1015 static int __init
init_iommu_one(struct amd_iommu
*iommu
, struct ivhd_header
*h
)
1017 spin_lock_init(&iommu
->lock
);
1019 /* Add IOMMU to internal data structures */
1020 list_add_tail(&iommu
->list
, &amd_iommu_list
);
1021 iommu
->index
= amd_iommus_present
++;
1023 if (unlikely(iommu
->index
>= MAX_IOMMUS
)) {
1024 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1028 /* Index is fine - add IOMMU to the array */
1029 amd_iommus
[iommu
->index
] = iommu
;
1032 * Copy data from ACPI table entry to the iommu struct
1034 iommu
->dev
= pci_get_bus_and_slot(PCI_BUS(h
->devid
), h
->devid
& 0xff);
1038 iommu
->cap_ptr
= h
->cap_ptr
;
1039 iommu
->pci_seg
= h
->pci_seg
;
1040 iommu
->mmio_phys
= h
->mmio_phys
;
1041 iommu
->mmio_base
= iommu_map_mmio_space(h
->mmio_phys
);
1042 if (!iommu
->mmio_base
)
1045 iommu
->cmd_buf
= alloc_command_buffer(iommu
);
1046 if (!iommu
->cmd_buf
)
1049 iommu
->evt_buf
= alloc_event_buffer(iommu
);
1050 if (!iommu
->evt_buf
)
1053 iommu
->int_enabled
= false;
1055 init_iommu_from_pci(iommu
);
1056 init_iommu_from_acpi(iommu
, h
);
1057 init_iommu_devices(iommu
);
1059 if (iommu_feature(iommu
, FEATURE_PPR
)) {
1060 iommu
->ppr_log
= alloc_ppr_log(iommu
);
1061 if (!iommu
->ppr_log
)
1065 if (iommu
->cap
& (1UL << IOMMU_CAP_NPCACHE
))
1066 amd_iommu_np_cache
= true;
1068 return pci_enable_device(iommu
->dev
);
1072 * Iterates over all IOMMU entries in the ACPI table, allocates the
1073 * IOMMU structure and initializes it with init_iommu_one()
1075 static int __init
init_iommu_all(struct acpi_table_header
*table
)
1077 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
1078 struct ivhd_header
*h
;
1079 struct amd_iommu
*iommu
;
1082 end
+= table
->length
;
1083 p
+= IVRS_HEADER_LENGTH
;
1086 h
= (struct ivhd_header
*)p
;
1088 case ACPI_IVHD_TYPE
:
1090 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1091 "seg: %d flags: %01x info %04x\n",
1092 PCI_BUS(h
->devid
), PCI_SLOT(h
->devid
),
1093 PCI_FUNC(h
->devid
), h
->cap_ptr
,
1094 h
->pci_seg
, h
->flags
, h
->info
);
1095 DUMP_printk(" mmio-addr: %016llx\n",
1098 iommu
= kzalloc(sizeof(struct amd_iommu
), GFP_KERNEL
);
1099 if (iommu
== NULL
) {
1100 amd_iommu_init_err
= -ENOMEM
;
1104 ret
= init_iommu_one(iommu
, h
);
1106 amd_iommu_init_err
= ret
;
1121 /****************************************************************************
1123 * The following functions initialize the MSI interrupts for all IOMMUs
1124 * in the system. Its a bit challenging because there could be multiple
1125 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1128 ****************************************************************************/
1130 static int iommu_setup_msi(struct amd_iommu
*iommu
)
1134 if (pci_enable_msi(iommu
->dev
))
1137 r
= request_threaded_irq(iommu
->dev
->irq
,
1138 amd_iommu_int_handler
,
1139 amd_iommu_int_thread
,
1144 pci_disable_msi(iommu
->dev
);
1148 iommu
->int_enabled
= true;
1149 iommu_feature_enable(iommu
, CONTROL_EVT_INT_EN
);
1151 if (iommu
->ppr_log
!= NULL
)
1152 iommu_feature_enable(iommu
, CONTROL_PPFINT_EN
);
1157 static int iommu_init_msi(struct amd_iommu
*iommu
)
1159 if (iommu
->int_enabled
)
1162 if (pci_find_capability(iommu
->dev
, PCI_CAP_ID_MSI
))
1163 return iommu_setup_msi(iommu
);
1168 /****************************************************************************
1170 * The next functions belong to the third pass of parsing the ACPI
1171 * table. In this last pass the memory mapping requirements are
1172 * gathered (like exclusion and unity mapping reanges).
1174 ****************************************************************************/
1176 static void __init
free_unity_maps(void)
1178 struct unity_map_entry
*entry
, *next
;
1180 list_for_each_entry_safe(entry
, next
, &amd_iommu_unity_map
, list
) {
1181 list_del(&entry
->list
);
1186 /* called when we find an exclusion range definition in ACPI */
1187 static int __init
init_exclusion_range(struct ivmd_header
*m
)
1192 case ACPI_IVMD_TYPE
:
1193 set_device_exclusion_range(m
->devid
, m
);
1195 case ACPI_IVMD_TYPE_ALL
:
1196 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
1197 set_device_exclusion_range(i
, m
);
1199 case ACPI_IVMD_TYPE_RANGE
:
1200 for (i
= m
->devid
; i
<= m
->aux
; ++i
)
1201 set_device_exclusion_range(i
, m
);
1210 /* called for unity map ACPI definition */
1211 static int __init
init_unity_map_range(struct ivmd_header
*m
)
1213 struct unity_map_entry
*e
= 0;
1216 e
= kzalloc(sizeof(*e
), GFP_KERNEL
);
1224 case ACPI_IVMD_TYPE
:
1225 s
= "IVMD_TYPEi\t\t\t";
1226 e
->devid_start
= e
->devid_end
= m
->devid
;
1228 case ACPI_IVMD_TYPE_ALL
:
1229 s
= "IVMD_TYPE_ALL\t\t";
1231 e
->devid_end
= amd_iommu_last_bdf
;
1233 case ACPI_IVMD_TYPE_RANGE
:
1234 s
= "IVMD_TYPE_RANGE\t\t";
1235 e
->devid_start
= m
->devid
;
1236 e
->devid_end
= m
->aux
;
1239 e
->address_start
= PAGE_ALIGN(m
->range_start
);
1240 e
->address_end
= e
->address_start
+ PAGE_ALIGN(m
->range_length
);
1241 e
->prot
= m
->flags
>> 1;
1243 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1244 " range_start: %016llx range_end: %016llx flags: %x\n", s
,
1245 PCI_BUS(e
->devid_start
), PCI_SLOT(e
->devid_start
),
1246 PCI_FUNC(e
->devid_start
), PCI_BUS(e
->devid_end
),
1247 PCI_SLOT(e
->devid_end
), PCI_FUNC(e
->devid_end
),
1248 e
->address_start
, e
->address_end
, m
->flags
);
1250 list_add_tail(&e
->list
, &amd_iommu_unity_map
);
1255 /* iterates over all memory definitions we find in the ACPI table */
1256 static int __init
init_memory_definitions(struct acpi_table_header
*table
)
1258 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
1259 struct ivmd_header
*m
;
1261 end
+= table
->length
;
1262 p
+= IVRS_HEADER_LENGTH
;
1265 m
= (struct ivmd_header
*)p
;
1266 if (m
->flags
& IVMD_FLAG_EXCL_RANGE
)
1267 init_exclusion_range(m
);
1268 else if (m
->flags
& IVMD_FLAG_UNITY_MAP
)
1269 init_unity_map_range(m
);
1278 * Init the device table to not allow DMA access for devices and
1279 * suppress all page faults
1281 static void init_device_table(void)
1285 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
) {
1286 set_dev_entry_bit(devid
, DEV_ENTRY_VALID
);
1287 set_dev_entry_bit(devid
, DEV_ENTRY_TRANSLATION
);
1291 static void iommu_init_flags(struct amd_iommu
*iommu
)
1293 iommu
->acpi_flags
& IVHD_FLAG_HT_TUN_EN_MASK
?
1294 iommu_feature_enable(iommu
, CONTROL_HT_TUN_EN
) :
1295 iommu_feature_disable(iommu
, CONTROL_HT_TUN_EN
);
1297 iommu
->acpi_flags
& IVHD_FLAG_PASSPW_EN_MASK
?
1298 iommu_feature_enable(iommu
, CONTROL_PASSPW_EN
) :
1299 iommu_feature_disable(iommu
, CONTROL_PASSPW_EN
);
1301 iommu
->acpi_flags
& IVHD_FLAG_RESPASSPW_EN_MASK
?
1302 iommu_feature_enable(iommu
, CONTROL_RESPASSPW_EN
) :
1303 iommu_feature_disable(iommu
, CONTROL_RESPASSPW_EN
);
1305 iommu
->acpi_flags
& IVHD_FLAG_ISOC_EN_MASK
?
1306 iommu_feature_enable(iommu
, CONTROL_ISOC_EN
) :
1307 iommu_feature_disable(iommu
, CONTROL_ISOC_EN
);
1310 * make IOMMU memory accesses cache coherent
1312 iommu_feature_enable(iommu
, CONTROL_COHERENT_EN
);
1314 /* Set IOTLB invalidation timeout to 1s */
1315 iommu_set_inv_tlb_timeout(iommu
, CTRL_INV_TO_1S
);
1318 static void iommu_apply_resume_quirks(struct amd_iommu
*iommu
)
1321 u32 ioc_feature_control
;
1322 struct pci_dev
*pdev
= NULL
;
1324 /* RD890 BIOSes may not have completely reconfigured the iommu */
1325 if (!is_rd890_iommu(iommu
->dev
))
1329 * First, we need to ensure that the iommu is enabled. This is
1330 * controlled by a register in the northbridge
1332 pdev
= pci_get_bus_and_slot(iommu
->dev
->bus
->number
, PCI_DEVFN(0, 0));
1337 /* Select Northbridge indirect register 0x75 and enable writing */
1338 pci_write_config_dword(pdev
, 0x60, 0x75 | (1 << 7));
1339 pci_read_config_dword(pdev
, 0x64, &ioc_feature_control
);
1341 /* Enable the iommu */
1342 if (!(ioc_feature_control
& 0x1))
1343 pci_write_config_dword(pdev
, 0x64, ioc_feature_control
| 1);
1347 /* Restore the iommu BAR */
1348 pci_write_config_dword(iommu
->dev
, iommu
->cap_ptr
+ 4,
1349 iommu
->stored_addr_lo
);
1350 pci_write_config_dword(iommu
->dev
, iommu
->cap_ptr
+ 8,
1351 iommu
->stored_addr_hi
);
1353 /* Restore the l1 indirect regs for each of the 6 l1s */
1354 for (i
= 0; i
< 6; i
++)
1355 for (j
= 0; j
< 0x12; j
++)
1356 iommu_write_l1(iommu
, i
, j
, iommu
->stored_l1
[i
][j
]);
1358 /* Restore the l2 indirect regs */
1359 for (i
= 0; i
< 0x83; i
++)
1360 iommu_write_l2(iommu
, i
, iommu
->stored_l2
[i
]);
1362 /* Lock PCI setup registers */
1363 pci_write_config_dword(iommu
->dev
, iommu
->cap_ptr
+ 4,
1364 iommu
->stored_addr_lo
| 1);
1368 * This function finally enables all IOMMUs found in the system after
1369 * they have been initialized
1371 static void enable_iommus(void)
1373 struct amd_iommu
*iommu
;
1375 for_each_iommu(iommu
) {
1376 iommu_disable(iommu
);
1377 iommu_init_flags(iommu
);
1378 iommu_set_device_table(iommu
);
1379 iommu_enable_command_buffer(iommu
);
1380 iommu_enable_event_buffer(iommu
);
1381 iommu_enable_ppr_log(iommu
);
1382 iommu_enable_gt(iommu
);
1383 iommu_set_exclusion_range(iommu
);
1384 iommu_init_msi(iommu
);
1385 iommu_enable(iommu
);
1386 iommu_flush_all_caches(iommu
);
1390 static void disable_iommus(void)
1392 struct amd_iommu
*iommu
;
1394 for_each_iommu(iommu
)
1395 iommu_disable(iommu
);
1399 * Suspend/Resume support
1400 * disable suspend until real resume implemented
1403 static void amd_iommu_resume(void)
1405 struct amd_iommu
*iommu
;
1407 for_each_iommu(iommu
)
1408 iommu_apply_resume_quirks(iommu
);
1410 /* re-load the hardware */
1414 static int amd_iommu_suspend(void)
1416 /* disable IOMMUs to go out of the way for BIOS */
1422 static struct syscore_ops amd_iommu_syscore_ops
= {
1423 .suspend
= amd_iommu_suspend
,
1424 .resume
= amd_iommu_resume
,
1428 * This is the core init function for AMD IOMMU hardware in the system.
1429 * This function is called from the generic x86 DMA layer initialization
1432 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1435 * 1 pass) Find the highest PCI device id the driver has to handle.
1436 * Upon this information the size of the data structures is
1437 * determined that needs to be allocated.
1439 * 2 pass) Initialize the data structures just allocated with the
1440 * information in the ACPI table about available AMD IOMMUs
1441 * in the system. It also maps the PCI devices in the
1442 * system to specific IOMMUs
1444 * 3 pass) After the basic data structures are allocated and
1445 * initialized we update them with information about memory
1446 * remapping requirements parsed out of the ACPI table in
1449 * After that the hardware is initialized and ready to go. In the last
1450 * step we do some Linux specific things like registering the driver in
1451 * the dma_ops interface and initializing the suspend/resume support
1452 * functions. Finally it prints some information about AMD IOMMUs and
1453 * the driver state and enables the hardware.
1455 static int __init
amd_iommu_init(void)
1460 * First parse ACPI tables to find the largest Bus/Dev/Func
1461 * we need to handle. Upon this information the shared data
1462 * structures for the IOMMUs in the system will be allocated
1464 if (acpi_table_parse("IVRS", find_last_devid_acpi
) != 0)
1467 ret
= amd_iommu_init_err
;
1471 dev_table_size
= tbl_size(DEV_TABLE_ENTRY_SIZE
);
1472 alias_table_size
= tbl_size(ALIAS_TABLE_ENTRY_SIZE
);
1473 rlookup_table_size
= tbl_size(RLOOKUP_TABLE_ENTRY_SIZE
);
1477 /* Device table - directly used by all IOMMUs */
1478 amd_iommu_dev_table
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
1479 get_order(dev_table_size
));
1480 if (amd_iommu_dev_table
== NULL
)
1484 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1485 * IOMMU see for that device
1487 amd_iommu_alias_table
= (void *)__get_free_pages(GFP_KERNEL
,
1488 get_order(alias_table_size
));
1489 if (amd_iommu_alias_table
== NULL
)
1492 /* IOMMU rlookup table - find the IOMMU for a specific device */
1493 amd_iommu_rlookup_table
= (void *)__get_free_pages(
1494 GFP_KERNEL
| __GFP_ZERO
,
1495 get_order(rlookup_table_size
));
1496 if (amd_iommu_rlookup_table
== NULL
)
1499 amd_iommu_pd_alloc_bitmap
= (void *)__get_free_pages(
1500 GFP_KERNEL
| __GFP_ZERO
,
1501 get_order(MAX_DOMAIN_ID
/8));
1502 if (amd_iommu_pd_alloc_bitmap
== NULL
)
1505 /* init the device table */
1506 init_device_table();
1509 * let all alias entries point to itself
1511 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
1512 amd_iommu_alias_table
[i
] = i
;
1515 * never allocate domain 0 because its used as the non-allocated and
1516 * error value placeholder
1518 amd_iommu_pd_alloc_bitmap
[0] = 1;
1520 spin_lock_init(&amd_iommu_pd_lock
);
1523 * now the data structures are allocated and basically initialized
1524 * start the real acpi table scan
1527 if (acpi_table_parse("IVRS", init_iommu_all
) != 0)
1530 if (amd_iommu_init_err
) {
1531 ret
= amd_iommu_init_err
;
1535 if (acpi_table_parse("IVRS", init_memory_definitions
) != 0)
1538 if (amd_iommu_init_err
) {
1539 ret
= amd_iommu_init_err
;
1543 ret
= amd_iommu_init_devices();
1549 if (iommu_pass_through
)
1550 ret
= amd_iommu_init_passthrough();
1552 ret
= amd_iommu_init_dma_ops();
1557 amd_iommu_init_api();
1559 amd_iommu_init_notifier();
1561 register_syscore_ops(&amd_iommu_syscore_ops
);
1563 if (iommu_pass_through
)
1566 if (amd_iommu_unmap_flush
)
1567 printk(KERN_INFO
"AMD-Vi: IO/TLB flush on unmap enabled\n");
1569 printk(KERN_INFO
"AMD-Vi: Lazy IO/TLB flushing enabled\n");
1571 x86_platform
.iommu_shutdown
= disable_iommus
;
1579 amd_iommu_uninit_devices();
1581 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap
,
1582 get_order(MAX_DOMAIN_ID
/8));
1584 free_pages((unsigned long)amd_iommu_rlookup_table
,
1585 get_order(rlookup_table_size
));
1587 free_pages((unsigned long)amd_iommu_alias_table
,
1588 get_order(alias_table_size
));
1590 free_pages((unsigned long)amd_iommu_dev_table
,
1591 get_order(dev_table_size
));
1597 #ifdef CONFIG_GART_IOMMU
1599 * We failed to initialize the AMD IOMMU - try fallback to GART
1609 /****************************************************************************
1611 * Early detect code. This code runs at IOMMU detection time in the DMA
1612 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1615 ****************************************************************************/
1616 static int __init
early_amd_iommu_detect(struct acpi_table_header
*table
)
1621 int __init
amd_iommu_detect(void)
1623 if (no_iommu
|| (iommu_detected
&& !gart_iommu_aperture
))
1626 if (amd_iommu_disabled
)
1629 if (acpi_table_parse("IVRS", early_amd_iommu_detect
) == 0) {
1631 amd_iommu_detected
= 1;
1632 x86_init
.iommu
.iommu_init
= amd_iommu_init
;
1634 /* Make sure ACS will be enabled */
1641 /****************************************************************************
1643 * Parsing functions for the AMD IOMMU specific kernel command line
1646 ****************************************************************************/
1648 static int __init
parse_amd_iommu_dump(char *str
)
1650 amd_iommu_dump
= true;
1655 static int __init
parse_amd_iommu_options(char *str
)
1657 for (; *str
; ++str
) {
1658 if (strncmp(str
, "fullflush", 9) == 0)
1659 amd_iommu_unmap_flush
= true;
1660 if (strncmp(str
, "off", 3) == 0)
1661 amd_iommu_disabled
= true;
1662 if (strncmp(str
, "force_isolation", 15) == 0)
1663 amd_iommu_force_isolation
= true;
1669 __setup("amd_iommu_dump", parse_amd_iommu_dump
);
1670 __setup("amd_iommu=", parse_amd_iommu_options
);
1672 IOMMU_INIT_FINISH(amd_iommu_detect
,
1673 gart_iommu_hole_init
,
1677 bool amd_iommu_v2_supported(void)
1679 return amd_iommu_v2_present
;
1681 EXPORT_SYMBOL(amd_iommu_v2_supported
);