2 * IRQ chip definitions for INTC IRQs.
4 * Copyright (C) 2007, 2008 Magnus Damm
5 * Copyright (C) 2009, 2010 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/cpumask.h>
13 #include "internals.h"
15 void _intc_enable(struct irq_data
*data
, unsigned long handle
)
17 unsigned int irq
= data
->irq
;
18 struct intc_desc_int
*d
= get_intc_desc(irq
);
22 for (cpu
= 0; cpu
< SMP_NR(d
, _INTC_ADDR_E(handle
)); cpu
++) {
24 if (!cpumask_test_cpu(cpu
, data
->affinity
))
27 addr
= INTC_REG(d
, _INTC_ADDR_E(handle
), cpu
);
28 intc_enable_fns
[_INTC_MODE(handle
)](addr
, handle
, intc_reg_fns\
29 [_INTC_FN(handle
)], irq
);
32 intc_balancing_enable(irq
);
35 static void intc_enable(struct irq_data
*data
)
37 _intc_enable(data
, (unsigned long)irq_data_get_irq_chip_data(data
));
40 static void intc_disable(struct irq_data
*data
)
42 unsigned int irq
= data
->irq
;
43 struct intc_desc_int
*d
= get_intc_desc(irq
);
44 unsigned long handle
= (unsigned long)irq_data_get_irq_chip_data(data
);
48 intc_balancing_disable(irq
);
50 for (cpu
= 0; cpu
< SMP_NR(d
, _INTC_ADDR_D(handle
)); cpu
++) {
52 if (!cpumask_test_cpu(cpu
, data
->affinity
))
55 addr
= INTC_REG(d
, _INTC_ADDR_D(handle
), cpu
);
56 intc_disable_fns
[_INTC_MODE(handle
)](addr
, handle
,intc_reg_fns\
57 [_INTC_FN(handle
)], irq
);
61 static int intc_set_wake(struct irq_data
*data
, unsigned int on
)
63 return 0; /* allow wakeup, but setup hardware in intc_suspend() */
68 * This is held with the irq desc lock held, so we don't require any
69 * additional locking here at the intc desc level. The affinity mask is
70 * later tested in the enable/disable paths.
72 static int intc_set_affinity(struct irq_data
*data
,
73 const struct cpumask
*cpumask
,
76 if (!cpumask_intersects(cpumask
, cpu_online_mask
))
79 cpumask_copy(data
->affinity
, cpumask
);
85 static void intc_mask_ack(struct irq_data
*data
)
87 unsigned int irq
= data
->irq
;
88 struct intc_desc_int
*d
= get_intc_desc(irq
);
89 unsigned long handle
= intc_get_ack_handle(irq
);
94 /* read register and write zero only to the associated bit */
98 addr
= INTC_REG(d
, _INTC_ADDR_D(handle
), 0);
99 value
= intc_set_field_from_handle(0, 1, handle
);
101 switch (_INTC_FN(handle
)) {
102 case REG_FN_MODIFY_BASE
+ 0: /* 8bit */
104 __raw_writeb(0xff ^ value
, addr
);
106 case REG_FN_MODIFY_BASE
+ 1: /* 16bit */
108 __raw_writew(0xffff ^ value
, addr
);
110 case REG_FN_MODIFY_BASE
+ 3: /* 32bit */
112 __raw_writel(0xffffffff ^ value
, addr
);
121 static struct intc_handle_int
*intc_find_irq(struct intc_handle_int
*hp
,
128 * this doesn't scale well, but...
130 * this function should only be used for cerain uncommon
131 * operations such as intc_set_priority() and intc_set_type()
132 * and in those rare cases performance doesn't matter that much.
133 * keeping the memory footprint low is more important.
135 * one rather simple way to speed this up and still keep the
136 * memory footprint down is to make sure the array is sorted
137 * and then perform a bisect to lookup the irq.
139 for (i
= 0; i
< nr_hp
; i
++) {
140 if ((hp
+ i
)->irq
!= irq
)
149 int intc_set_priority(unsigned int irq
, unsigned int prio
)
151 struct intc_desc_int
*d
= get_intc_desc(irq
);
152 struct irq_data
*data
= irq_get_irq_data(irq
);
153 struct intc_handle_int
*ihp
;
155 if (!intc_get_prio_level(irq
) || prio
<= 1)
158 ihp
= intc_find_irq(d
->prio
, d
->nr_prio
, irq
);
160 if (prio
>= (1 << _INTC_WIDTH(ihp
->handle
)))
163 intc_set_prio_level(irq
, prio
);
166 * only set secondary masking method directly
167 * primary masking method is using intc_prio_level[irq]
168 * priority level will be set during next enable()
170 if (_INTC_FN(ihp
->handle
) != REG_FN_ERR
)
171 _intc_enable(data
, ihp
->handle
);
176 #define SENSE_VALID_FLAG 0x80
177 #define VALID(x) (x | SENSE_VALID_FLAG)
179 static unsigned char intc_irq_sense_table
[IRQ_TYPE_SENSE_MASK
+ 1] = {
180 [IRQ_TYPE_EDGE_FALLING
] = VALID(0),
181 [IRQ_TYPE_EDGE_RISING
] = VALID(1),
182 [IRQ_TYPE_LEVEL_LOW
] = VALID(2),
183 /* SH7706, SH7707 and SH7709 do not support high level triggered */
184 #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
185 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
186 !defined(CONFIG_CPU_SUBTYPE_SH7709)
187 [IRQ_TYPE_LEVEL_HIGH
] = VALID(3),
189 #if defined(CONFIG_ARM) /* all recent SH-Mobile / R-Mobile ARM support this */
190 [IRQ_TYPE_EDGE_BOTH
] = VALID(4),
194 static int intc_set_type(struct irq_data
*data
, unsigned int type
)
196 unsigned int irq
= data
->irq
;
197 struct intc_desc_int
*d
= get_intc_desc(irq
);
198 unsigned char value
= intc_irq_sense_table
[type
& IRQ_TYPE_SENSE_MASK
];
199 struct intc_handle_int
*ihp
;
205 value
&= ~SENSE_VALID_FLAG
;
207 ihp
= intc_find_irq(d
->sense
, d
->nr_sense
, irq
);
209 /* PINT has 2-bit sense registers, should fail on EDGE_BOTH */
210 if (value
>= (1 << _INTC_WIDTH(ihp
->handle
)))
213 addr
= INTC_REG(d
, _INTC_ADDR_E(ihp
->handle
), 0);
214 intc_reg_fns
[_INTC_FN(ihp
->handle
)](addr
, ihp
->handle
, value
);
220 struct irq_chip intc_irq_chip
= {
221 .irq_mask
= intc_disable
,
222 .irq_unmask
= intc_enable
,
223 .irq_mask_ack
= intc_mask_ack
,
224 .irq_enable
= intc_enable
,
225 .irq_disable
= intc_disable
,
226 .irq_shutdown
= intc_disable
,
227 .irq_set_type
= intc_set_type
,
228 .irq_set_wake
= intc_set_wake
,
230 .irq_set_affinity
= intc_set_affinity
,