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ath9k: Replace ath9k_opmode with nl80211_iftype
[linux/fpc-iii.git] / drivers / net / wireless / iwlwifi / iwl-tx.c
blobe045dfeaa1fe973cc0b3336f0634ee5018d8b784
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #include <linux/etherdevice.h>
31 #include <net/mac80211.h>
32 #include "iwl-eeprom.h"
33 #include "iwl-dev.h"
34 #include "iwl-core.h"
35 #include "iwl-sta.h"
36 #include "iwl-io.h"
37 #include "iwl-helpers.h"
38
39 static const u16 default_tid_to_tx_fifo[] = {
40 IWL_TX_FIFO_AC1,
41 IWL_TX_FIFO_AC0,
42 IWL_TX_FIFO_AC0,
43 IWL_TX_FIFO_AC1,
44 IWL_TX_FIFO_AC2,
45 IWL_TX_FIFO_AC2,
46 IWL_TX_FIFO_AC3,
47 IWL_TX_FIFO_AC3,
48 IWL_TX_FIFO_NONE,
49 IWL_TX_FIFO_NONE,
50 IWL_TX_FIFO_NONE,
51 IWL_TX_FIFO_NONE,
52 IWL_TX_FIFO_NONE,
53 IWL_TX_FIFO_NONE,
54 IWL_TX_FIFO_NONE,
55 IWL_TX_FIFO_NONE,
56 IWL_TX_FIFO_AC3
57 };
58
59 static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
60 struct iwl_dma_ptr *ptr, size_t size)
61 {
62 ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma);
63 if (!ptr->addr)
64 return -ENOMEM;
65 ptr->size = size;
66 return 0;
67 }
68
69 static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
70 struct iwl_dma_ptr *ptr)
71 {
72 if (unlikely(!ptr->addr))
73 return;
74
75 pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma);
76 memset(ptr, 0, sizeof(*ptr));
77 }
78
79 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
80 {
81 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
82
83 dma_addr_t addr = get_unaligned_le32(&tb->lo);
84 if (sizeof(dma_addr_t) > sizeof(u32))
85 addr |=
86 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
87
88 return addr;
89 }
90
91 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
92 {
93 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
94
95 return le16_to_cpu(tb->hi_n_len) >> 4;
96 }
97
98 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
99 dma_addr_t addr, u16 len)
100 {
101 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
102 u16 hi_n_len = len << 4;
103
104 put_unaligned_le32(addr, &tb->lo);
105 if (sizeof(dma_addr_t) > sizeof(u32))
106 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
107
108 tb->hi_n_len = cpu_to_le16(hi_n_len);
109
110 tfd->num_tbs = idx + 1;
111 }
112
113 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
114 {
115 return tfd->num_tbs & 0x1f;
116 }
117
118 /**
119 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
120 * @priv - driver private data
121 * @txq - tx queue
122 *
123 * Does NOT advance any TFD circular buffer read/write indexes
124 * Does NOT free the TFD itself (which is within circular buffer)
125 */
126 static void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
127 {
128 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)&txq->tfds[0];
129 struct iwl_tfd *tfd;
130 struct pci_dev *dev = priv->pci_dev;
131 int index = txq->q.read_ptr;
132 int i;
133 int num_tbs;
134
135 tfd = &tfd_tmp[index];
136
137 /* Sanity check on number of chunks */
138 num_tbs = iwl_tfd_get_num_tbs(tfd);
139
140 if (num_tbs >= IWL_NUM_OF_TBS) {
141 IWL_ERROR("Too many chunks: %i\n", num_tbs);
142 /* @todo issue fatal error, it is quite serious situation */
143 return;
144 }
145
146 /* Unmap tx_cmd */
147 if (num_tbs)
148 pci_unmap_single(dev,
149 pci_unmap_addr(&txq->cmd[index]->meta, mapping),
150 pci_unmap_len(&txq->cmd[index]->meta, len),
151 PCI_DMA_TODEVICE);
152
153 /* Unmap chunks, if any. */
154 for (i = 1; i < num_tbs; i++) {
155 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
156 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
157
158 if (txq->txb) {
159 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
160 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
161 }
162 }
163 }
164
165 static int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
166 struct iwl_tfd *tfd,
167 dma_addr_t addr, u16 len)
168 {
169
170 u32 num_tbs = iwl_tfd_get_num_tbs(tfd);
171
172 /* Each TFD can point to a maximum 20 Tx buffers */
173 if (num_tbs >= IWL_NUM_OF_TBS) {
174 IWL_ERROR("Error can not send more than %d chunks\n",
175 IWL_NUM_OF_TBS);
176 return -EINVAL;
177 }
178
179 BUG_ON(addr & ~DMA_BIT_MASK(36));
180 if (unlikely(addr & ~IWL_TX_DMA_MASK))
181 IWL_ERROR("Unaligned address = %llx\n",
182 (unsigned long long)addr);
183
184 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
185
186 return 0;
187 }
188
189 /**
190 * iwl_txq_update_write_ptr - Send new write index to hardware
191 */
192 int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
193 {
194 u32 reg = 0;
195 int ret = 0;
196 int txq_id = txq->q.id;
197
198 if (txq->need_update == 0)
199 return ret;
200
201 /* if we're trying to save power */
202 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
203 /* wake up nic if it's powered down ...
204 * uCode will wake up, and interrupt us again, so next
205 * time we'll skip this part. */
206 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
207
208 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
209 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
210 iwl_set_bit(priv, CSR_GP_CNTRL,
211 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
212 return ret;
213 }
214
215 /* restore this queue's parameters in nic hardware. */
216 ret = iwl_grab_nic_access(priv);
217 if (ret)
218 return ret;
219 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
220 txq->q.write_ptr | (txq_id << 8));
221 iwl_release_nic_access(priv);
222
223 /* else not in power-save mode, uCode will never sleep when we're
224 * trying to tx (during RFKILL, we're not trying to tx). */
225 } else
226 iwl_write32(priv, HBUS_TARG_WRPTR,
227 txq->q.write_ptr | (txq_id << 8));
228
229 txq->need_update = 0;
230
231 return ret;
232 }
233 EXPORT_SYMBOL(iwl_txq_update_write_ptr);
234
235
236 /**
237 * iwl_tx_queue_free - Deallocate DMA queue.
238 * @txq: Transmit queue to deallocate.
239 *
240 * Empty queue by removing and destroying all BD's.
241 * Free all buffers.
242 * 0-fill, but do not free "txq" descriptor structure.
243 */
244 static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
245 {
246 struct iwl_tx_queue *txq = &priv->txq[txq_id];
247 struct iwl_queue *q = &txq->q;
248 struct pci_dev *dev = priv->pci_dev;
249 int i, len;
250
251 if (q->n_bd == 0)
252 return;
253
254 /* first, empty all BD's */
255 for (; q->write_ptr != q->read_ptr;
256 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
257 iwl_hw_txq_free_tfd(priv, txq);
258
259 len = sizeof(struct iwl_cmd) * q->n_window;
260
261 /* De-alloc array of command/tx buffers */
262 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
263 kfree(txq->cmd[i]);
264
265 /* De-alloc circular buffer of TFDs */
266 if (txq->q.n_bd)
267 pci_free_consistent(dev, sizeof(struct iwl_tfd) *
268 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
269
270 /* De-alloc array of per-TFD driver data */
271 kfree(txq->txb);
272 txq->txb = NULL;
273
274 /* 0-fill queue descriptor structure */
275 memset(txq, 0, sizeof(*txq));
276 }
277
278
279 /**
280 * iwl_cmd_queue_free - Deallocate DMA queue.
281 * @txq: Transmit queue to deallocate.
282 *
283 * Empty queue by removing and destroying all BD's.
284 * Free all buffers.
285 * 0-fill, but do not free "txq" descriptor structure.
286 */
287 static void iwl_cmd_queue_free(struct iwl_priv *priv)
288 {
289 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
290 struct iwl_queue *q = &txq->q;
291 struct pci_dev *dev = priv->pci_dev;
292 int i, len;
293
294 if (q->n_bd == 0)
295 return;
296
297 len = sizeof(struct iwl_cmd) * q->n_window;
298 len += IWL_MAX_SCAN_SIZE;
299
300 /* De-alloc array of command/tx buffers */
301 for (i = 0; i <= TFD_CMD_SLOTS; i++)
302 kfree(txq->cmd[i]);
303
304 /* De-alloc circular buffer of TFDs */
305 if (txq->q.n_bd)
306 pci_free_consistent(dev, sizeof(struct iwl_tfd) *
307 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
308
309 /* 0-fill queue descriptor structure */
310 memset(txq, 0, sizeof(*txq));
311 }
312 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
313 * DMA services
314 *
315 * Theory of operation
316 *
317 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
318 * of buffer descriptors, each of which points to one or more data buffers for
319 * the device to read from or fill. Driver and device exchange status of each
320 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
321 * entries in each circular buffer, to protect against confusing empty and full
322 * queue states.
323 *
324 * The device reads or writes the data in the queues via the device's several
325 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
326 *
327 * For Tx queue, there are low mark and high mark limits. If, after queuing
328 * the packet for Tx, free space become < low mark, Tx queue stopped. When
329 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
330 * Tx queue resumed.
331 *
332 * See more detailed info in iwl-4965-hw.h.
333 ***************************************************/
334
335 int iwl_queue_space(const struct iwl_queue *q)
336 {
337 int s = q->read_ptr - q->write_ptr;
338
339 if (q->read_ptr > q->write_ptr)
340 s -= q->n_bd;
341
342 if (s <= 0)
343 s += q->n_window;
344 /* keep some reserve to not confuse empty and full situations */
345 s -= 2;
346 if (s < 0)
347 s = 0;
348 return s;
349 }
350 EXPORT_SYMBOL(iwl_queue_space);
351
352
353 /**
354 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
355 */
356 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
357 int count, int slots_num, u32 id)
358 {
359 q->n_bd = count;
360 q->n_window = slots_num;
361 q->id = id;
362
363 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
364 * and iwl_queue_dec_wrap are broken. */
365 BUG_ON(!is_power_of_2(count));
366
367 /* slots_num must be power-of-two size, otherwise
368 * get_cmd_index is broken. */
369 BUG_ON(!is_power_of_2(slots_num));
370
371 q->low_mark = q->n_window / 4;
372 if (q->low_mark < 4)
373 q->low_mark = 4;
374
375 q->high_mark = q->n_window / 8;
376 if (q->high_mark < 2)
377 q->high_mark = 2;
378
379 q->write_ptr = q->read_ptr = 0;
380
381 return 0;
382 }
383
384 /**
385 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
386 */
387 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
388 struct iwl_tx_queue *txq, u32 id)
389 {
390 struct pci_dev *dev = priv->pci_dev;
391
392 /* Driver private data, only for Tx (not command) queues,
393 * not shared with device. */
394 if (id != IWL_CMD_QUEUE_NUM) {
395 txq->txb = kmalloc(sizeof(txq->txb[0]) *
396 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
397 if (!txq->txb) {
398 IWL_ERROR("kmalloc for auxiliary BD "
399 "structures failed\n");
400 goto error;
401 }
402 } else
403 txq->txb = NULL;
404
405 /* Circular buffer of transmit frame descriptors (TFDs),
406 * shared with device */
407 txq->tfds = pci_alloc_consistent(dev,
408 sizeof(txq->tfds[0]) * TFD_QUEUE_SIZE_MAX,
409 &txq->q.dma_addr);
410
411 if (!txq->tfds) {
412 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
413 sizeof(txq->tfds[0]) * TFD_QUEUE_SIZE_MAX);
414 goto error;
415 }
416 txq->q.id = id;
417
418 return 0;
419
420 error:
421 kfree(txq->txb);
422 txq->txb = NULL;
423
424 return -ENOMEM;
425 }
426
427 /*
428 * Tell nic where to find circular buffer of Tx Frame Descriptors for
429 * given Tx queue, and enable the DMA channel used for that queue.
430 *
431 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
432 * channels supported in hardware.
433 */
434 static int iwl_hw_tx_queue_init(struct iwl_priv *priv,
435 struct iwl_tx_queue *txq)
436 {
437 int ret;
438 unsigned long flags;
439 int txq_id = txq->q.id;
440
441 spin_lock_irqsave(&priv->lock, flags);
442 ret = iwl_grab_nic_access(priv);
443 if (ret) {
444 spin_unlock_irqrestore(&priv->lock, flags);
445 return ret;
446 }
447
448 /* Circular buffer (TFD queue in DRAM) physical base address */
449 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
450 txq->q.dma_addr >> 8);
451
452 iwl_release_nic_access(priv);
453 spin_unlock_irqrestore(&priv->lock, flags);
454
455 return 0;
456 }
457
458 /**
459 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
460 */
461 static int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
462 int slots_num, u32 txq_id)
463 {
464 int i, len;
465 int ret;
466
467 /*
468 * Alloc buffer array for commands (Tx or other types of commands).
469 * For the command queue (#4), allocate command space + one big
470 * command for scan, since scan command is very huge; the system will
471 * not have two scans at the same time, so only one is needed.
472 * For normal Tx queues (all other queues), no super-size command
473 * space is needed.
474 */
475 len = sizeof(struct iwl_cmd);
476 for (i = 0; i <= slots_num; i++) {
477 if (i == slots_num) {
478 if (txq_id == IWL_CMD_QUEUE_NUM)
479 len += IWL_MAX_SCAN_SIZE;
480 else
481 continue;
482 }
483
484 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
485 if (!txq->cmd[i])
486 goto err;
487 }
488
489 /* Alloc driver data array and TFD circular buffer */
490 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
491 if (ret)
492 goto err;
493
494 txq->need_update = 0;
495
496 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
497 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
498 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
499
500 /* Initialize queue's high/low-water marks, and head/tail indexes */
501 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
502
503 /* Tell device where to find queue */
504 iwl_hw_tx_queue_init(priv, txq);
505
506 return 0;
507 err:
508 for (i = 0; i < slots_num; i++) {
509 kfree(txq->cmd[i]);
510 txq->cmd[i] = NULL;
511 }
512
513 if (txq_id == IWL_CMD_QUEUE_NUM) {
514 kfree(txq->cmd[slots_num]);
515 txq->cmd[slots_num] = NULL;
516 }
517 return -ENOMEM;
518 }
519 /**
520 * iwl_hw_txq_ctx_free - Free TXQ Context
521 *
522 * Destroy all TX DMA queues and structures
523 */
524 void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
525 {
526 int txq_id;
527
528 /* Tx queues */
529 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
530 if (txq_id == IWL_CMD_QUEUE_NUM)
531 iwl_cmd_queue_free(priv);
532 else
533 iwl_tx_queue_free(priv, txq_id);
534
535 iwl_free_dma_ptr(priv, &priv->kw);
536
537 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
538 }
539 EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
540
541 /**
542 * iwl_txq_ctx_reset - Reset TX queue context
543 * Destroys all DMA structures and initialize them again
544 *
545 * @param priv
546 * @return error code
547 */
548 int iwl_txq_ctx_reset(struct iwl_priv *priv)
549 {
550 int ret = 0;
551 int txq_id, slots_num;
552 unsigned long flags;
553
554 /* Free all tx/cmd queues and keep-warm buffer */
555 iwl_hw_txq_ctx_free(priv);
556
557 ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
558 priv->hw_params.scd_bc_tbls_size);
559 if (ret) {
560 IWL_ERROR("Scheduler BC Table allocation failed\n");
561 goto error_bc_tbls;
562 }
563 /* Alloc keep-warm buffer */
564 ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
565 if (ret) {
566 IWL_ERROR("Keep Warm allocation failed\n");
567 goto error_kw;
568 }
569 spin_lock_irqsave(&priv->lock, flags);
570 ret = iwl_grab_nic_access(priv);
571 if (unlikely(ret)) {
572 spin_unlock_irqrestore(&priv->lock, flags);
573 goto error_reset;
574 }
575
576 /* Turn off all Tx DMA fifos */
577 priv->cfg->ops->lib->txq_set_sched(priv, 0);
578
579 /* Tell NIC where to find the "keep warm" buffer */
580 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
581
582 iwl_release_nic_access(priv);
583 spin_unlock_irqrestore(&priv->lock, flags);
584
585 /* Alloc and init all Tx queues, including the command queue (#4) */
586 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
587 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
588 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
589 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
590 txq_id);
591 if (ret) {
592 IWL_ERROR("Tx %d queue init failed\n", txq_id);
593 goto error;
594 }
595 }
596
597 return ret;
598
599 error:
600 iwl_hw_txq_ctx_free(priv);
601 error_reset:
602 iwl_free_dma_ptr(priv, &priv->kw);
603 error_kw:
604 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
605 error_bc_tbls:
606 return ret;
607 }
608
609 /**
610 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
611 */
612 void iwl_txq_ctx_stop(struct iwl_priv *priv)
613 {
614 int txq_id;
615 unsigned long flags;
616
617 /* Turn off all Tx DMA fifos */
618 spin_lock_irqsave(&priv->lock, flags);
619 if (iwl_grab_nic_access(priv)) {
620 spin_unlock_irqrestore(&priv->lock, flags);
621 return;
622 }
623
624 priv->cfg->ops->lib->txq_set_sched(priv, 0);
625
626 /* Stop each Tx DMA channel, and wait for it to be idle */
627 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
628 iwl_write_direct32(priv,
629 FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
630 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
631 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
632 (txq_id), 200);
633 }
634 iwl_release_nic_access(priv);
635 spin_unlock_irqrestore(&priv->lock, flags);
636
637 /* Deallocate memory for all Tx queues */
638 iwl_hw_txq_ctx_free(priv);
639 }
640 EXPORT_SYMBOL(iwl_txq_ctx_stop);
641
642 /*
643 * handle build REPLY_TX command notification.
644 */
645 static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
646 struct iwl_tx_cmd *tx_cmd,
647 struct ieee80211_tx_info *info,
648 struct ieee80211_hdr *hdr,
649 int is_unicast, u8 std_id)
650 {
651 __le16 fc = hdr->frame_control;
652 __le32 tx_flags = tx_cmd->tx_flags;
653
654 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
655 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
656 tx_flags |= TX_CMD_FLG_ACK_MSK;
657 if (ieee80211_is_mgmt(fc))
658 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
659 if (ieee80211_is_probe_resp(fc) &&
660 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
661 tx_flags |= TX_CMD_FLG_TSF_MSK;
662 } else {
663 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
664 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
665 }
666
667 if (ieee80211_is_back_req(fc))
668 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
669
670
671 tx_cmd->sta_id = std_id;
672 if (ieee80211_has_morefrags(fc))
673 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
674
675 if (ieee80211_is_data_qos(fc)) {
676 u8 *qc = ieee80211_get_qos_ctl(hdr);
677 tx_cmd->tid_tspec = qc[0] & 0xf;
678 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
679 } else {
680 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
681 }
682
683 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
684
685 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
686 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
687
688 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
689 if (ieee80211_is_mgmt(fc)) {
690 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
691 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
692 else
693 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
694 } else {
695 tx_cmd->timeout.pm_frame_timeout = 0;
696 }
697
698 tx_cmd->driver_txop = 0;
699 tx_cmd->tx_flags = tx_flags;
700 tx_cmd->next_frame_len = 0;
701 }
702
703 #define RTS_HCCA_RETRY_LIMIT 3
704 #define RTS_DFAULT_RETRY_LIMIT 60
705
706 static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
707 struct iwl_tx_cmd *tx_cmd,
708 struct ieee80211_tx_info *info,
709 __le16 fc, int sta_id,
710 int is_hcca)
711 {
712 u32 rate_flags = 0;
713 int rate_idx;
714 u8 rts_retry_limit = 0;
715 u8 data_retry_limit = 0;
716 u8 rate_plcp;
717
718 rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff,
719 IWL_RATE_COUNT - 1);
720
721 rate_plcp = iwl_rates[rate_idx].plcp;
722
723 rts_retry_limit = (is_hcca) ?
724 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
725
726 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
727 rate_flags |= RATE_MCS_CCK_MSK;
728
729
730 if (ieee80211_is_probe_resp(fc)) {
731 data_retry_limit = 3;
732 if (data_retry_limit < rts_retry_limit)
733 rts_retry_limit = data_retry_limit;
734 } else
735 data_retry_limit = IWL_DEFAULT_TX_RETRY;
736
737 if (priv->data_retry_limit != -1)
738 data_retry_limit = priv->data_retry_limit;
739
740
741 if (ieee80211_is_data(fc)) {
742 tx_cmd->initial_rate_index = 0;
743 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
744 } else {
745 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
746 case cpu_to_le16(IEEE80211_STYPE_AUTH):
747 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
748 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
749 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
750 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
751 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
752 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
753 }
754 break;
755 default:
756 break;
757 }
758
759 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
760 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
761 }
762
763 tx_cmd->rts_retry_limit = rts_retry_limit;
764 tx_cmd->data_retry_limit = data_retry_limit;
765 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
766 }
767
768 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
769 struct ieee80211_tx_info *info,
770 struct iwl_tx_cmd *tx_cmd,
771 struct sk_buff *skb_frag,
772 int sta_id)
773 {
774 struct ieee80211_key_conf *keyconf = info->control.hw_key;
775
776 switch (keyconf->alg) {
777 case ALG_CCMP:
778 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
779 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
780 if (info->flags & IEEE80211_TX_CTL_AMPDU)
781 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
782 IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
783 break;
784
785 case ALG_TKIP:
786 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
787 ieee80211_get_tkip_key(keyconf, skb_frag,
788 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
789 IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n");
790 break;
791
792 case ALG_WEP:
793 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
794 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
795
796 if (keyconf->keylen == WEP_KEY_LEN_128)
797 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
798
799 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
800
801 IWL_DEBUG_TX("Configuring packet for WEP encryption "
802 "with key %d\n", keyconf->keyidx);
803 break;
804
805 default:
806 printk(KERN_ERR "Unknown encode alg %d\n", keyconf->alg);
807 break;
808 }
809 }
810
811 static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len)
812 {
813 /* 0 - mgmt, 1 - cnt, 2 - data */
814 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
815 priv->tx_stats[idx].cnt++;
816 priv->tx_stats[idx].bytes += len;
817 }
818
819 /*
820 * start REPLY_TX command process
821 */
822 int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
823 {
824 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
825 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
826 struct iwl_tfd *tfd;
827 struct iwl_tx_queue *txq;
828 struct iwl_queue *q;
829 struct iwl_cmd *out_cmd;
830 struct iwl_tx_cmd *tx_cmd;
831 int swq_id, txq_id;
832 dma_addr_t phys_addr;
833 dma_addr_t txcmd_phys;
834 dma_addr_t scratch_phys;
835 u16 len, len_org;
836 u16 seq_number = 0;
837 __le16 fc;
838 u8 hdr_len, unicast;
839 u8 sta_id;
840 u8 wait_write_ptr = 0;
841 u8 tid = 0;
842 u8 *qc = NULL;
843 unsigned long flags;
844 int ret;
845
846 spin_lock_irqsave(&priv->lock, flags);
847 if (iwl_is_rfkill(priv)) {
848 IWL_DEBUG_DROP("Dropping - RF KILL\n");
849 goto drop_unlock;
850 }
851
852 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) ==
853 IWL_INVALID_RATE) {
854 IWL_ERROR("ERROR: No TX rate available.\n");
855 goto drop_unlock;
856 }
857
858 unicast = !is_multicast_ether_addr(hdr->addr1);
859
860 fc = hdr->frame_control;
861
862 #ifdef CONFIG_IWLWIFI_DEBUG
863 if (ieee80211_is_auth(fc))
864 IWL_DEBUG_TX("Sending AUTH frame\n");
865 else if (ieee80211_is_assoc_req(fc))
866 IWL_DEBUG_TX("Sending ASSOC frame\n");
867 else if (ieee80211_is_reassoc_req(fc))
868 IWL_DEBUG_TX("Sending REASSOC frame\n");
869 #endif
870
871 /* drop all data frame if we are not associated */
872 if (ieee80211_is_data(fc) &&
873 (priv->iw_mode != NL80211_IFTYPE_MONITOR ||
874 !(info->flags & IEEE80211_TX_CTL_INJECTED)) && /* packet injection */
875 (!iwl_is_associated(priv) ||
876 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
877 !priv->assoc_station_added)) {
878 IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n");
879 goto drop_unlock;
880 }
881
882 spin_unlock_irqrestore(&priv->lock, flags);
883
884 hdr_len = ieee80211_hdrlen(fc);
885
886 /* Find (or create) index into station table for destination station */
887 sta_id = iwl_get_sta_id(priv, hdr);
888 if (sta_id == IWL_INVALID_STATION) {
889 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
890 hdr->addr1);
891 goto drop;
892 }
893
894 IWL_DEBUG_TX("station Id %d\n", sta_id);
895
896 swq_id = skb_get_queue_mapping(skb);
897 txq_id = swq_id;
898 if (ieee80211_is_data_qos(fc)) {
899 qc = ieee80211_get_qos_ctl(hdr);
900 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
901 seq_number = priv->stations[sta_id].tid[tid].seq_number;
902 seq_number &= IEEE80211_SCTL_SEQ;
903 hdr->seq_ctrl = hdr->seq_ctrl &
904 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG);
905 hdr->seq_ctrl |= cpu_to_le16(seq_number);
906 seq_number += 0x10;
907 /* aggregation is on for this <sta,tid> */
908 if (info->flags & IEEE80211_TX_CTL_AMPDU)
909 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
910 priv->stations[sta_id].tid[tid].tfds_in_queue++;
911 }
912
913 txq = &priv->txq[txq_id];
914 q = &txq->q;
915 txq->swq_id = swq_id;
916
917 spin_lock_irqsave(&priv->lock, flags);
918
919 /* Set up first empty TFD within this queue's circular TFD buffer */
920 tfd = &txq->tfds[q->write_ptr];
921 memset(tfd, 0, sizeof(*tfd));
922
923 /* Set up driver data for this TFD */
924 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
925 txq->txb[q->write_ptr].skb[0] = skb;
926
927 /* Set up first empty entry in queue's array of Tx/cmd buffers */
928 out_cmd = txq->cmd[q->write_ptr];
929 tx_cmd = &out_cmd->cmd.tx;
930 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
931 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
932
933 /*
934 * Set up the Tx-command (not MAC!) header.
935 * Store the chosen Tx queue and TFD index within the sequence field;
936 * after Tx, uCode's Tx response will return this value so driver can
937 * locate the frame within the tx queue and do post-tx processing.
938 */
939 out_cmd->hdr.cmd = REPLY_TX;
940 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
941 INDEX_TO_SEQ(q->write_ptr)));
942
943 /* Copy MAC header from skb into command buffer */
944 memcpy(tx_cmd->hdr, hdr, hdr_len);
945
946 /*
947 * Use the first empty entry in this queue's command buffer array
948 * to contain the Tx command and MAC header concatenated together
949 * (payload data will be in another buffer).
950 * Size of this varies, due to varying MAC header length.
951 * If end is not dword aligned, we'll have 2 extra bytes at the end
952 * of the MAC header (device reads on dword boundaries).
953 * We'll tell device about this padding later.
954 */
955 len = sizeof(struct iwl_tx_cmd) +
956 sizeof(struct iwl_cmd_header) + hdr_len;
957
958 len_org = len;
959 len = (len + 3) & ~3;
960
961 if (len_org != len)
962 len_org = 1;
963 else
964 len_org = 0;
965
966 /* Physical address of this Tx command's header (not MAC header!),
967 * within command buffer array. */
968 txcmd_phys = pci_map_single(priv->pci_dev,
969 out_cmd, sizeof(struct iwl_cmd),
970 PCI_DMA_TODEVICE);
971 pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
972 pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd));
973 /* Add buffer containing Tx command and MAC(!) header to TFD's
974 * first entry */
975 txcmd_phys += offsetof(struct iwl_cmd, hdr);
976 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
977
978 if (info->control.hw_key)
979 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
980
981 /* Set up TFD's 2nd entry to point directly to remainder of skb,
982 * if any (802.11 null frames have no payload). */
983 len = skb->len - hdr_len;
984 if (len) {
985 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
986 len, PCI_DMA_TODEVICE);
987 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
988 }
989
990 /* Tell NIC about any 2-byte padding after MAC header */
991 if (len_org)
992 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
993
994 /* Total # bytes to be transmitted */
995 len = (u16)skb->len;
996 tx_cmd->len = cpu_to_le16(len);
997 /* TODO need this for burst mode later on */
998 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, unicast, sta_id);
999
1000 /* set is_hcca to 0; it probably will never be implemented */
1001 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);
1002
1003 iwl_update_tx_stats(priv, le16_to_cpu(fc), len);
1004
1005 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1006 offsetof(struct iwl_tx_cmd, scratch);
1007 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1008 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1009
1010 if (!ieee80211_has_morefrags(hdr->frame_control)) {
1011 txq->need_update = 1;
1012 if (qc)
1013 priv->stations[sta_id].tid[tid].seq_number = seq_number;
1014 } else {
1015 wait_write_ptr = 1;
1016 txq->need_update = 0;
1017 }
1018
1019 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1020
1021 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1022
1023 /* Set up entry for this TFD in Tx byte-count array */
1024 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len);
1025
1026 /* Tell device the write index *just past* this latest filled TFD */
1027 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1028 ret = iwl_txq_update_write_ptr(priv, txq);
1029 spin_unlock_irqrestore(&priv->lock, flags);
1030
1031 if (ret)
1032 return ret;
1033
1034 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
1035 if (wait_write_ptr) {
1036 spin_lock_irqsave(&priv->lock, flags);
1037 txq->need_update = 1;
1038 iwl_txq_update_write_ptr(priv, txq);
1039 spin_unlock_irqrestore(&priv->lock, flags);
1040 } else {
1041 ieee80211_stop_queue(priv->hw, txq->swq_id);
1042 }
1043 }
1044
1045 return 0;
1046
1047 drop_unlock:
1048 spin_unlock_irqrestore(&priv->lock, flags);
1049 drop:
1050 return -1;
1051 }
1052 EXPORT_SYMBOL(iwl_tx_skb);
1053
1054 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1055
1056 /**
1057 * iwl_enqueue_hcmd - enqueue a uCode command
1058 * @priv: device private data point
1059 * @cmd: a point to the ucode command structure
1060 *
1061 * The function returns < 0 values to indicate the operation is
1062 * failed. On success, it turns the index (> 0) of command in the
1063 * command queue.
1064 */
1065 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
1066 {
1067 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
1068 struct iwl_queue *q = &txq->q;
1069 struct iwl_tfd *tfd;
1070 struct iwl_cmd *out_cmd;
1071 dma_addr_t phys_addr;
1072 unsigned long flags;
1073 int len, ret;
1074 u32 idx;
1075 u16 fix_size;
1076
1077 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
1078 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
1079
1080 /* If any of the command structures end up being larger than
1081 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1082 * we will need to increase the size of the TFD entries */
1083 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
1084 !(cmd->meta.flags & CMD_SIZE_HUGE));
1085
1086 if (iwl_is_rfkill(priv)) {
1087 IWL_DEBUG_INFO("Not sending command - RF KILL");
1088 return -EIO;
1089 }
1090
1091 if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
1092 IWL_ERROR("No space for Tx\n");
1093 return -ENOSPC;
1094 }
1095
1096 spin_lock_irqsave(&priv->hcmd_lock, flags);
1097
1098 tfd = &txq->tfds[q->write_ptr];
1099 memset(tfd, 0, sizeof(*tfd));
1100
1101
1102 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
1103 out_cmd = txq->cmd[idx];
1104
1105 out_cmd->hdr.cmd = cmd->id;
1106 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
1107 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1108
1109 /* At this point, the out_cmd now has all of the incoming cmd
1110 * information */
1111
1112 out_cmd->hdr.flags = 0;
1113 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1114 INDEX_TO_SEQ(q->write_ptr));
1115 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
1116 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
1117 len = (idx == TFD_CMD_SLOTS) ?
1118 IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
1119
1120 phys_addr = pci_map_single(priv->pci_dev, out_cmd,
1121 len, PCI_DMA_TODEVICE);
1122 pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
1123 pci_unmap_len_set(&out_cmd->meta, len, len);
1124 phys_addr += offsetof(struct iwl_cmd, hdr);
1125
1126 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
1127
1128 #ifdef CONFIG_IWLWIFI_DEBUG
1129 switch (out_cmd->hdr.cmd) {
1130 case REPLY_TX_LINK_QUALITY_CMD:
1131 case SENSITIVITY_CMD:
1132 IWL_DEBUG_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
1133 "%d bytes at %d[%d]:%d\n",
1134 get_cmd_string(out_cmd->hdr.cmd),
1135 out_cmd->hdr.cmd,
1136 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1137 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1138 break;
1139 default:
1140 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
1141 "%d bytes at %d[%d]:%d\n",
1142 get_cmd_string(out_cmd->hdr.cmd),
1143 out_cmd->hdr.cmd,
1144 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1145 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1146 }
1147 #endif
1148 txq->need_update = 1;
1149
1150 /* Set up entry in queue's byte count circular buffer */
1151 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1152
1153 /* Increment and update queue's write index */
1154 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1155 ret = iwl_txq_update_write_ptr(priv, txq);
1156
1157 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1158 return ret ? ret : idx;
1159 }
1160
1161 int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1162 {
1163 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1164 struct iwl_queue *q = &txq->q;
1165 struct iwl_tx_info *tx_info;
1166 int nfreed = 0;
1167
1168 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1169 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1170 "is out of range [0-%d] %d %d.\n", txq_id,
1171 index, q->n_bd, q->write_ptr, q->read_ptr);
1172 return 0;
1173 }
1174
1175 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1176 q->read_ptr != index;
1177 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1178
1179 tx_info = &txq->txb[txq->q.read_ptr];
1180 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
1181 tx_info->skb[0] = NULL;
1182
1183 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1184 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1185
1186 iwl_hw_txq_free_tfd(priv, txq);
1187 nfreed++;
1188 }
1189 return nfreed;
1190 }
1191 EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1192
1193
1194 /**
1195 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1196 *
1197 * When FW advances 'R' index, all entries between old and new 'R' index
1198 * need to be reclaimed. As result, some free space forms. If there is
1199 * enough free space (> low mark), wake the stack that feeds us.
1200 */
1201 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
1202 int idx, int cmd_idx)
1203 {
1204 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1205 struct iwl_queue *q = &txq->q;
1206 int nfreed = 0;
1207
1208 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
1209 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1210 "is out of range [0-%d] %d %d.\n", txq_id,
1211 idx, q->n_bd, q->write_ptr, q->read_ptr);
1212 return;
1213 }
1214
1215 pci_unmap_single(priv->pci_dev,
1216 pci_unmap_addr(&txq->cmd[cmd_idx]->meta, mapping),
1217 pci_unmap_len(&txq->cmd[cmd_idx]->meta, len),
1218 PCI_DMA_TODEVICE);
1219
1220 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1221 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1222
1223 if (nfreed++ > 0) {
1224 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", idx,
1225 q->write_ptr, q->read_ptr);
1226 queue_work(priv->workqueue, &priv->restart);
1227 }
1228
1229 }
1230 }
1231
1232 /**
1233 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1234 * @rxb: Rx buffer to reclaim
1235 *
1236 * If an Rx buffer has an async callback associated with it the callback
1237 * will be executed. The attached skb (if present) will only be freed
1238 * if the callback returns 1
1239 */
1240 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1241 {
1242 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1243 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1244 int txq_id = SEQ_TO_QUEUE(sequence);
1245 int index = SEQ_TO_INDEX(sequence);
1246 int cmd_index;
1247 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
1248 struct iwl_cmd *cmd;
1249
1250 /* If a Tx command is being handled and it isn't in the actual
1251 * command queue then there a command routing bug has been introduced
1252 * in the queue management code. */
1253 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1254 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1255 txq_id, sequence,
1256 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
1257 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
1258 iwl_print_hex_dump(priv, IWL_DL_INFO , rxb, 32);
1259 return;
1260 }
1261
1262 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1263 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1264
1265 /* Input error checking is done when commands are added to queue. */
1266 if (cmd->meta.flags & CMD_WANT_SKB) {
1267 cmd->meta.source->u.skb = rxb->skb;
1268 rxb->skb = NULL;
1269 } else if (cmd->meta.u.callback &&
1270 !cmd->meta.u.callback(priv, cmd, rxb->skb))
1271 rxb->skb = NULL;
1272
1273 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
1274
1275 if (!(cmd->meta.flags & CMD_ASYNC)) {
1276 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1277 wake_up_interruptible(&priv->wait_command_queue);
1278 }
1279 }
1280 EXPORT_SYMBOL(iwl_tx_cmd_complete);
1281
1282 /*
1283 * Find first available (lowest unused) Tx Queue, mark it "active".
1284 * Called only when finding queue for aggregation.
1285 * Should never return anything < 7, because they should already
1286 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1287 */
1288 static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1289 {
1290 int txq_id;
1291
1292 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1293 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1294 return txq_id;
1295 return -1;
1296 }
1297
1298 int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1299 {
1300 int sta_id;
1301 int tx_fifo;
1302 int txq_id;
1303 int ret;
1304 unsigned long flags;
1305 struct iwl_tid_data *tid_data;
1306
1307 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1308 tx_fifo = default_tid_to_tx_fifo[tid];
1309 else
1310 return -EINVAL;
1311
1312 IWL_WARNING("%s on ra = %pM tid = %d\n",
1313 __func__, ra, tid);
1314
1315 sta_id = iwl_find_station(priv, ra);
1316 if (sta_id == IWL_INVALID_STATION)
1317 return -ENXIO;
1318
1319 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1320 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
1321 return -ENXIO;
1322 }
1323
1324 txq_id = iwl_txq_ctx_activate_free(priv);
1325 if (txq_id == -1)
1326 return -ENXIO;
1327
1328 spin_lock_irqsave(&priv->sta_lock, flags);
1329 tid_data = &priv->stations[sta_id].tid[tid];
1330 *ssn = SEQ_TO_SN(tid_data->seq_number);
1331 tid_data->agg.txq_id = txq_id;
1332 spin_unlock_irqrestore(&priv->sta_lock, flags);
1333
1334 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1335 sta_id, tid, *ssn);
1336 if (ret)
1337 return ret;
1338
1339 if (tid_data->tfds_in_queue == 0) {
1340 printk(KERN_ERR "HW queue is empty\n");
1341 tid_data->agg.state = IWL_AGG_ON;
1342 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1343 } else {
1344 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
1345 tid_data->tfds_in_queue);
1346 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1347 }
1348 return ret;
1349 }
1350 EXPORT_SYMBOL(iwl_tx_agg_start);
1351
1352 int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1353 {
1354 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1355 struct iwl_tid_data *tid_data;
1356 int ret, write_ptr, read_ptr;
1357 unsigned long flags;
1358
1359 if (!ra) {
1360 IWL_ERROR("ra = NULL\n");
1361 return -EINVAL;
1362 }
1363
1364 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1365 tx_fifo_id = default_tid_to_tx_fifo[tid];
1366 else
1367 return -EINVAL;
1368
1369 sta_id = iwl_find_station(priv, ra);
1370
1371 if (sta_id == IWL_INVALID_STATION)
1372 return -ENXIO;
1373
1374 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1375 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
1376
1377 tid_data = &priv->stations[sta_id].tid[tid];
1378 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1379 txq_id = tid_data->agg.txq_id;
1380 write_ptr = priv->txq[txq_id].q.write_ptr;
1381 read_ptr = priv->txq[txq_id].q.read_ptr;
1382
1383 /* The queue is not empty */
1384 if (write_ptr != read_ptr) {
1385 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
1386 priv->stations[sta_id].tid[tid].agg.state =
1387 IWL_EMPTYING_HW_QUEUE_DELBA;
1388 return 0;
1389 }
1390
1391 IWL_DEBUG_HT("HW queue is empty\n");
1392 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1393
1394 spin_lock_irqsave(&priv->lock, flags);
1395 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1396 tx_fifo_id);
1397 spin_unlock_irqrestore(&priv->lock, flags);
1398
1399 if (ret)
1400 return ret;
1401
1402 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1403
1404 return 0;
1405 }
1406 EXPORT_SYMBOL(iwl_tx_agg_stop);
1407
1408 int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1409 {
1410 struct iwl_queue *q = &priv->txq[txq_id].q;
1411 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1412 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1413
1414 switch (priv->stations[sta_id].tid[tid].agg.state) {
1415 case IWL_EMPTYING_HW_QUEUE_DELBA:
1416 /* We are reclaiming the last packet of the */
1417 /* aggregated HW queue */
1418 if ((txq_id == tid_data->agg.txq_id) &&
1419 (q->read_ptr == q->write_ptr)) {
1420 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1421 int tx_fifo = default_tid_to_tx_fifo[tid];
1422 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
1423 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1424 ssn, tx_fifo);
1425 tid_data->agg.state = IWL_AGG_OFF;
1426 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1427 }
1428 break;
1429 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1430 /* We are reclaiming the last packet of the queue */
1431 if (tid_data->tfds_in_queue == 0) {
1432 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
1433 tid_data->agg.state = IWL_AGG_ON;
1434 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1435 }
1436 break;
1437 }
1438 return 0;
1439 }
1440 EXPORT_SYMBOL(iwl_txq_check_empty);
1441
1442 /**
1443 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1444 *
1445 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1446 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1447 */
1448 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1449 struct iwl_ht_agg *agg,
1450 struct iwl_compressed_ba_resp *ba_resp)
1451
1452 {
1453 int i, sh, ack;
1454 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1455 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1456 u64 bitmap;
1457 int successes = 0;
1458 struct ieee80211_tx_info *info;
1459
1460 if (unlikely(!agg->wait_for_ba)) {
1461 IWL_ERROR("Received BA when not expected\n");
1462 return -EINVAL;
1463 }
1464
1465 /* Mark that the expected block-ack response arrived */
1466 agg->wait_for_ba = 0;
1467 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1468
1469 /* Calculate shift to align block-ack bits with our Tx window bits */
1470 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1471 if (sh < 0) /* tbw something is wrong with indices */
1472 sh += 0x100;
1473
1474 /* don't use 64-bit values for now */
1475 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1476
1477 if (agg->frame_count > (64 - sh)) {
1478 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
1479 return -1;
1480 }
1481
1482 /* check for success or failure according to the
1483 * transmitted bitmap and block-ack bitmap */
1484 bitmap &= agg->bitmap;
1485
1486 /* For each frame attempted in aggregation,
1487 * update driver's record of tx frame's status. */
1488 for (i = 0; i < agg->frame_count ; i++) {
1489 ack = bitmap & (1ULL << i);
1490 successes += !!ack;
1491 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
1492 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1493 agg->start_idx + i);
1494 }
1495
1496 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1497 memset(&info->status, 0, sizeof(info->status));
1498 info->flags = IEEE80211_TX_STAT_ACK;
1499 info->flags |= IEEE80211_TX_STAT_AMPDU;
1500 info->status.ampdu_ack_map = successes;
1501 info->status.ampdu_ack_len = agg->frame_count;
1502 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1503
1504 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
1505
1506 return 0;
1507 }
1508
1509 /**
1510 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1511 *
1512 * Handles block-acknowledge notification from device, which reports success
1513 * of frames sent via aggregation.
1514 */
1515 void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1516 struct iwl_rx_mem_buffer *rxb)
1517 {
1518 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1519 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1520 struct iwl_tx_queue *txq = NULL;
1521 struct iwl_ht_agg *agg;
1522 int index;
1523 int sta_id;
1524 int tid;
1525
1526 /* "flow" corresponds to Tx queue */
1527 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1528
1529 /* "ssn" is start of block-ack Tx window, corresponds to index
1530 * (in Tx queue's circular buffer) of first TFD/frame in window */
1531 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1532
1533 if (scd_flow >= priv->hw_params.max_txq_num) {
1534 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues\n");
1535 return;
1536 }
1537
1538 txq = &priv->txq[scd_flow];
1539 sta_id = ba_resp->sta_id;
1540 tid = ba_resp->tid;
1541 agg = &priv->stations[sta_id].tid[tid].agg;
1542
1543 /* Find index just before block-ack window */
1544 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1545
1546 /* TODO: Need to get this copy more safely - now good for debug */
1547
1548 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d] Received from %pM, "
1549 "sta_id = %d\n",
1550 agg->wait_for_ba,
1551 (u8 *) &ba_resp->sta_addr_lo32,
1552 ba_resp->sta_id);
1553 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1554 "%d, scd_ssn = %d\n",
1555 ba_resp->tid,
1556 ba_resp->seq_ctl,
1557 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1558 ba_resp->scd_flow,
1559 ba_resp->scd_ssn);
1560 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
1561 agg->start_idx,
1562 (unsigned long long)agg->bitmap);
1563
1564 /* Update driver's record of ACK vs. not for each frame in window */
1565 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1566
1567 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1568 * block-ack window (we assume that they've been successfully
1569 * transmitted ... if not, it's too late anyway). */
1570 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1571 /* calculate mac80211 ampdu sw queue to wake */
1572 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1573 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1574
1575 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1576 priv->mac80211_registered &&
1577 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1578 ieee80211_wake_queue(priv->hw, txq->swq_id);
1579
1580 iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
1581 }
1582 }
1583 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1584
1585 #ifdef CONFIG_IWLWIFI_DEBUG
1586 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1587
1588 const char *iwl_get_tx_fail_reason(u32 status)
1589 {
1590 switch (status & TX_STATUS_MSK) {
1591 case TX_STATUS_SUCCESS:
1592 return "SUCCESS";
1593 TX_STATUS_ENTRY(SHORT_LIMIT);
1594 TX_STATUS_ENTRY(LONG_LIMIT);
1595 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1596 TX_STATUS_ENTRY(MGMNT_ABORT);
1597 TX_STATUS_ENTRY(NEXT_FRAG);
1598 TX_STATUS_ENTRY(LIFE_EXPIRE);
1599 TX_STATUS_ENTRY(DEST_PS);
1600 TX_STATUS_ENTRY(ABORTED);
1601 TX_STATUS_ENTRY(BT_RETRY);
1602 TX_STATUS_ENTRY(STA_INVALID);
1603 TX_STATUS_ENTRY(FRAG_DROPPED);
1604 TX_STATUS_ENTRY(TID_DISABLE);
1605 TX_STATUS_ENTRY(FRAME_FLUSHED);
1606 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1607 TX_STATUS_ENTRY(TX_LOCKED);
1608 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1609 }
1610
1611 return "UNKNOWN";
1612 }
1613 EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1614 #endif /* CONFIG_IWLWIFI_DEBUG */
Linux with added FPC-III support