x86/irq: Check for valid irq descriptor in check_irq_vectors_for_cpu_disable()
[linux/fpc-iii.git] / include / dt-bindings / pinctrl / pinctrl-tegra.h
blobebafa498be0ff7425eb13d68f173d1b228f0a346
1 /*
2 * This header provides constants for Tegra pinctrl bindings.
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
6 * Author: Laxman Dewangan <ldewangan@nvidia.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
18 #ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
19 #define _DT_BINDINGS_PINCTRL_TEGRA_H
22 * Enable/disable for diffeent dt properties. This is applicable for
23 * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
24 * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
26 #define TEGRA_PIN_DISABLE 0
27 #define TEGRA_PIN_ENABLE 1
29 #define TEGRA_PIN_PULL_NONE 0
30 #define TEGRA_PIN_PULL_DOWN 1
31 #define TEGRA_PIN_PULL_UP 2
33 /* Low power mode driver */
34 #define TEGRA_PIN_LP_DRIVE_DIV_8 0
35 #define TEGRA_PIN_LP_DRIVE_DIV_4 1
36 #define TEGRA_PIN_LP_DRIVE_DIV_2 2
37 #define TEGRA_PIN_LP_DRIVE_DIV_1 3
39 /* Rising/Falling slew rate */
40 #define TEGRA_PIN_SLEW_RATE_FASTEST 0
41 #define TEGRA_PIN_SLEW_RATE_FAST 1
42 #define TEGRA_PIN_SLEW_RATE_SLOW 2
43 #define TEGRA_PIN_SLEW_RATE_SLOWEST 3
45 #endif