arch/arm64/kernel/setup.c

   1 /*
   2  * Based on arch/arm/kernel/setup.c
   3  *
   4  * Copyright (C) 1995-2001 Russell King
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/export.h>
  21 #include <linux/kernel.h>
  22 #include <linux/stddef.h>
  23 #include <linux/ioport.h>
  24 #include <linux/delay.h>
  25 #include <linux/utsname.h>
  26 #include <linux/initrd.h>
  27 #include <linux/console.h>
  28 #include <linux/bootmem.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/screen_info.h>
  31 #include <linux/init.h>
  32 #include <linux/kexec.h>
  33 #include <linux/crash_dump.h>
  34 #include <linux/root_dev.h>
  35 #include <linux/clk-provider.h>
  36 #include <linux/cpu.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/smp.h>
  39 #include <linux/fs.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/memblock.h>
  42 #include <linux/of_fdt.h>
  43 #include <linux/of_platform.h>
  44
  45 #include <asm/cputype.h>
  46 #include <asm/elf.h>
  47 #include <asm/cputable.h>
  48 #include <asm/cpu_ops.h>
  49 #include <asm/sections.h>
  50 #include <asm/setup.h>
  51 #include <asm/smp_plat.h>
  52 #include <asm/cacheflush.h>
  53 #include <asm/tlbflush.h>
  54 #include <asm/traps.h>
  55 #include <asm/memblock.h>
  56 #include <asm/psci.h>
  57
  58 unsigned int processor_id;
  59 EXPORT_SYMBOL(processor_id);
  60
  61 unsigned long elf_hwcap __read_mostly;
  62 EXPORT_SYMBOL_GPL(elf_hwcap);
  63
  64 #ifdef CONFIG_COMPAT
  65 #define COMPAT_ELF_HWCAP_DEFAULT        \
  66                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  67                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  68                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  69                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  70                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV)
  71 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  72 #endif
  73
  74 static const char *cpu_name;
  75 static const char *machine_name;
  76 phys_addr_t __fdt_pointer __initdata;
  77
  78 /*
  79  * Standard memory resources
  80  */
  81 static struct resource mem_res[] = {
  82         {
  83                 .name = "Kernel code",
  84                 .start = 0,
  85                 .end = 0,
  86                 .flags = IORESOURCE_MEM
  87         },
  88         {
  89                 .name = "Kernel data",
  90                 .start = 0,
  91                 .end = 0,
  92                 .flags = IORESOURCE_MEM
  93         }
  94 };
  95
  96 #define kernel_code mem_res[0]
  97 #define kernel_data mem_res[1]
  98
  99 void __init early_print(const char *str, ...)
 100 {
 101         char buf[256];
 102         va_list ap;
 103
 104         va_start(ap, str);
 105         vsnprintf(buf, sizeof(buf), str, ap);
 106         va_end(ap);
 107
 108         printk("%s", buf);
 109 }
 110
 111 void __init smp_setup_processor_id(void)
 112 {
 113         /*
 114          * clear __my_cpu_offset on boot CPU to avoid hang caused by
 115          * using percpu variable early, for example, lockdep will
 116          * access percpu variable inside lock_release
 117          */
 118         set_my_cpu_offset(0);
 119 }
 120
 121 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
 122 {
 123         return phys_id == cpu_logical_map(cpu);
 124 }
 125
 126 struct mpidr_hash mpidr_hash;
 127 #ifdef CONFIG_SMP
 128 /**
 129  * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
 130  *                        level in order to build a linear index from an
 131  *                        MPIDR value. Resulting algorithm is a collision
 132  *                        free hash carried out through shifting and ORing
 133  */
 134 static void __init smp_build_mpidr_hash(void)
 135 {
 136         u32 i, affinity, fs[4], bits[4], ls;
 137         u64 mask = 0;
 138         /*
 139          * Pre-scan the list of MPIDRS and filter out bits that do
 140          * not contribute to affinity levels, ie they never toggle.
 141          */
 142         for_each_possible_cpu(i)
 143                 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
 144         pr_debug("mask of set bits %#llx\n", mask);
 145         /*
 146          * Find and stash the last and first bit set at all affinity levels to
 147          * check how many bits are required to represent them.
 148          */
 149         for (i = 0; i < 4; i++) {
 150                 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
 151                 /*
 152                  * Find the MSB bit and LSB bits position
 153                  * to determine how many bits are required
 154                  * to express the affinity level.
 155                  */
 156                 ls = fls(affinity);
 157                 fs[i] = affinity ? ffs(affinity) - 1 : 0;
 158                 bits[i] = ls - fs[i];
 159         }
 160         /*
 161          * An index can be created from the MPIDR_EL1 by isolating the
 162          * significant bits at each affinity level and by shifting
 163          * them in order to compress the 32 bits values space to a
 164          * compressed set of values. This is equivalent to hashing
 165          * the MPIDR_EL1 through shifting and ORing. It is a collision free
 166          * hash though not minimal since some levels might contain a number
 167          * of CPUs that is not an exact power of 2 and their bit
 168          * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
 169          */
 170         mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
 171         mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
 172         mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
 173                                                 (bits[1] + bits[0]);
 174         mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
 175                                   fs[3] - (bits[2] + bits[1] + bits[0]);
 176         mpidr_hash.mask = mask;
 177         mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
 178         pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
 179                 mpidr_hash.shift_aff[0],
 180                 mpidr_hash.shift_aff[1],
 181                 mpidr_hash.shift_aff[2],
 182                 mpidr_hash.shift_aff[3],
 183                 mpidr_hash.mask,
 184                 mpidr_hash.bits);
 185         /*
 186          * 4x is an arbitrary value used to warn on a hash table much bigger
 187          * than expected on most systems.
 188          */
 189         if (mpidr_hash_size() > 4 * num_possible_cpus())
 190                 pr_warn("Large number of MPIDR hash buckets detected\n");
 191         __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash));
 192 }
 193 #endif
 194
 195 static void __init setup_processor(void)
 196 {
 197         struct cpu_info *cpu_info;
 198         u64 features, block;
 199
 200         cpu_info = lookup_processor_type(read_cpuid_id());
 201         if (!cpu_info) {
 202                 printk("CPU configuration botched (ID %08x), unable to continue.\n",
 203                        read_cpuid_id());
 204                 while (1);
 205         }
 206
 207         cpu_name = cpu_info->cpu_name;
 208
 209         printk("CPU: %s [%08x] revision %d\n",
 210                cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
 211
 212         sprintf(init_utsname()->machine, ELF_PLATFORM);
 213         elf_hwcap = 0;
 214
 215         /*
 216          * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
 217          * The blocks we test below represent incremental functionality
 218          * for non-negative values. Negative values are reserved.
 219          */
 220         features = read_cpuid(ID_AA64ISAR0_EL1);
 221         block = (features >> 4) & 0xf;
 222         if (!(block & 0x8)) {
 223                 switch (block) {
 224                 default:
 225                 case 2:
 226                         elf_hwcap |= HWCAP_PMULL;
 227                 case 1:
 228                         elf_hwcap |= HWCAP_AES;
 229                 case 0:
 230                         break;
 231                 }
 232         }
 233
 234         block = (features >> 8) & 0xf;
 235         if (block && !(block & 0x8))
 236                 elf_hwcap |= HWCAP_SHA1;
 237
 238         block = (features >> 12) & 0xf;
 239         if (block && !(block & 0x8))
 240                 elf_hwcap |= HWCAP_SHA2;
 241
 242         block = (features >> 16) & 0xf;
 243         if (block && !(block & 0x8))
 244                 elf_hwcap |= HWCAP_CRC32;
 245 }
 246
 247 static void __init setup_machine_fdt(phys_addr_t dt_phys)
 248 {
 249         if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) {
 250                 early_print("\n"
 251                         "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
 252                         "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
 253                         "\nPlease check your bootloader.\n",
 254                         dt_phys, phys_to_virt(dt_phys));
 255
 256                 while (true)
 257                         cpu_relax();
 258         }
 259
 260         machine_name = of_flat_dt_get_machine_name();
 261 }
 262
 263 /*
 264  * Limit the memory size that was specified via FDT.
 265  */
 266 static int __init early_mem(char *p)
 267 {
 268         phys_addr_t limit;
 269
 270         if (!p)
 271                 return 1;
 272
 273         limit = memparse(p, &p) & PAGE_MASK;
 274         pr_notice("Memory limited to %lldMB\n", limit >> 20);
 275
 276         memblock_enforce_memory_limit(limit);
 277
 278         return 0;
 279 }
 280 early_param("mem", early_mem);
 281
 282 static void __init request_standard_resources(void)
 283 {
 284         struct memblock_region *region;
 285         struct resource *res;
 286
 287         kernel_code.start   = virt_to_phys(_text);
 288         kernel_code.end     = virt_to_phys(_etext - 1);
 289         kernel_data.start   = virt_to_phys(_sdata);
 290         kernel_data.end     = virt_to_phys(_end - 1);
 291
 292         for_each_memblock(memory, region) {
 293                 res = alloc_bootmem_low(sizeof(*res));
 294                 res->name  = "System RAM";
 295                 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
 296                 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
 297                 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 298
 299                 request_resource(&iomem_resource, res);
 300
 301                 if (kernel_code.start >= res->start &&
 302                     kernel_code.end <= res->end)
 303                         request_resource(res, &kernel_code);
 304                 if (kernel_data.start >= res->start &&
 305                     kernel_data.end <= res->end)
 306                         request_resource(res, &kernel_data);
 307         }
 308 }
 309
 310 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
 311
 312 void __init setup_arch(char **cmdline_p)
 313 {
 314         /*
 315          * Unmask asynchronous aborts early to catch possible system errors.
 316          */
 317         local_async_enable();
 318
 319         setup_processor();
 320
 321         setup_machine_fdt(__fdt_pointer);
 322
 323         init_mm.start_code = (unsigned long) _text;
 324         init_mm.end_code   = (unsigned long) _etext;
 325         init_mm.end_data   = (unsigned long) _edata;
 326         init_mm.brk        = (unsigned long) _end;
 327
 328         *cmdline_p = boot_command_line;
 329
 330         parse_early_param();
 331
 332         arm64_memblock_init();
 333
 334         paging_init();
 335         request_standard_resources();
 336
 337         unflatten_device_tree();
 338
 339         psci_init();
 340
 341         cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
 342         cpu_read_bootcpu_ops();
 343 #ifdef CONFIG_SMP
 344         smp_init_cpus();
 345         smp_build_mpidr_hash();
 346 #endif
 347
 348 #ifdef CONFIG_VT
 349 #if defined(CONFIG_VGA_CONSOLE)
 350         conswitchp = &vga_con;
 351 #elif defined(CONFIG_DUMMY_CONSOLE)
 352         conswitchp = &dummy_con;
 353 #endif
 354 #endif
 355 }
 356
 357 static int __init arm64_device_init(void)
 358 {
 359         of_clk_init(NULL);
 360         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 361         return 0;
 362 }
 363 arch_initcall(arm64_device_init);
 364
 365 static DEFINE_PER_CPU(struct cpu, cpu_data);
 366
 367 static int __init topology_init(void)
 368 {
 369         int i;
 370
 371         for_each_possible_cpu(i) {
 372                 struct cpu *cpu = &per_cpu(cpu_data, i);
 373                 cpu->hotpluggable = 1;
 374                 register_cpu(cpu, i);
 375         }
 376
 377         return 0;
 378 }
 379 subsys_initcall(topology_init);
 380
 381 static const char *hwcap_str[] = {
 382         "fp",
 383         "asimd",
 384         "evtstrm",
 385         "aes",
 386         "pmull",
 387         "sha1",
 388         "sha2",
 389         "crc32",
 390         NULL
 391 };
 392
 393 static int c_show(struct seq_file *m, void *v)
 394 {
 395         int i;
 396
 397         seq_printf(m, "Processor\t: %s rev %d (%s)\n",
 398                    cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
 399
 400         for_each_online_cpu(i) {
 401                 /*
 402                  * glibc reads /proc/cpuinfo to determine the number of
 403                  * online processors, looking for lines beginning with
 404                  * "processor".  Give glibc what it expects.
 405                  */
 406 #ifdef CONFIG_SMP
 407                 seq_printf(m, "processor\t: %d\n", i);
 408 #endif
 409         }
 410
 411         /* dump out the processor features */
 412         seq_puts(m, "Features\t: ");
 413
 414         for (i = 0; hwcap_str[i]; i++)
 415                 if (elf_hwcap & (1 << i))
 416                         seq_printf(m, "%s ", hwcap_str[i]);
 417
 418         seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
 419         seq_printf(m, "CPU architecture: AArch64\n");
 420         seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
 421         seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
 422         seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
 423
 424         seq_puts(m, "\n");
 425
 426         seq_printf(m, "Hardware\t: %s\n", machine_name);
 427
 428         return 0;
 429 }
 430
 431 static void *c_start(struct seq_file *m, loff_t *pos)
 432 {
 433         return *pos < 1 ? (void *)1 : NULL;
 434 }
 435
 436 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 437 {
 438         ++*pos;
 439         return NULL;
 440 }
 441
 442 static void c_stop(struct seq_file *m, void *v)
 443 {
 444 }
 445
 446 const struct seq_operations cpuinfo_op = {
 447         .start  = c_start,
 448         .next   = c_next,
 449         .stop   = c_stop,
 450         .show   = c_show
 451 };