arch/powerpc/platforms/85xx/corenet_generic.c

   1 /*
   2  * Corenet based SoC DS Setup
   3  *
   4  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
   5  *
   6  * Copyright 2009-2011 Freescale Semiconductor Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/kdev_t.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19
  20 #include <asm/time.h>
  21 #include <asm/machdep.h>
  22 #include <asm/pci-bridge.h>
  23 #include <asm/ppc-pci.h>
  24 #include <mm/mmu_decl.h>
  25 #include <asm/prom.h>
  26 #include <asm/udbg.h>
  27 #include <asm/mpic.h>
  28 #include <asm/ehv_pic.h>
  29
  30 #include <linux/of_platform.h>
  31 #include <sysdev/fsl_soc.h>
  32 #include <sysdev/fsl_pci.h>
  33 #include "smp.h"
  34
  35 void __init corenet_gen_pic_init(void)
  36 {
  37         struct mpic *mpic;
  38         unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
  39                 MPIC_NO_RESET;
  40
  41         if (ppc_md.get_irq == mpic_get_coreint_irq)
  42                 flags |= MPIC_ENABLE_COREINT;
  43
  44         mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC  ");
  45         BUG_ON(mpic == NULL);
  46
  47         mpic_init(mpic);
  48 }
  49
  50 /*
  51  * Setup the architecture
  52  */
  53 void __init corenet_gen_setup_arch(void)
  54 {
  55         mpc85xx_smp_init();
  56
  57         swiotlb_detect_4g();
  58
  59         pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
  60 }
  61
  62 static const struct of_device_id of_device_ids[] = {
  63         {
  64                 .compatible     = "simple-bus"
  65         },
  66         {
  67                 .compatible     = "fsl,srio",
  68         },
  69         {
  70                 .compatible     = "fsl,p4080-pcie",
  71         },
  72         {
  73                 .compatible     = "fsl,qoriq-pcie-v2.2",
  74         },
  75         {
  76                 .compatible     = "fsl,qoriq-pcie-v2.3",
  77         },
  78         {
  79                 .compatible     = "fsl,qoriq-pcie-v2.4",
  80         },
  81         {
  82                 .compatible     = "fsl,qoriq-pcie-v3.0",
  83         },
  84         /* The following two are for the Freescale hypervisor */
  85         {
  86                 .name           = "hypervisor",
  87         },
  88         {
  89                 .name           = "handles",
  90         },
  91         {}
  92 };
  93
  94 int __init corenet_gen_publish_devices(void)
  95 {
  96         return of_platform_bus_probe(NULL, of_device_ids, NULL);
  97 }
  98
  99 static const char * const boards[] __initconst = {
 100         "fsl,P2041RDB",
 101         "fsl,P3041DS",
 102         "fsl,P4080DS",
 103         "fsl,P5020DS",
 104         "fsl,P5040DS",
 105         "fsl,T4240QDS",
 106         "fsl,B4860QDS",
 107         "fsl,B4420QDS",
 108         "fsl,B4220QDS",
 109         NULL
 110 };
 111
 112 static const char * const hv_boards[] __initconst = {
 113         "fsl,P2041RDB-hv",
 114         "fsl,P3041DS-hv",
 115         "fsl,P4080DS-hv",
 116         "fsl,P5020DS-hv",
 117         "fsl,P5040DS-hv",
 118         "fsl,T4240QDS-hv",
 119         "fsl,B4860QDS-hv",
 120         "fsl,B4420QDS-hv",
 121         "fsl,B4220QDS-hv",
 122         NULL
 123 };
 124
 125 /*
 126  * Called very early, device-tree isn't unflattened
 127  */
 128 static int __init corenet_generic_probe(void)
 129 {
 130         unsigned long root = of_get_flat_dt_root();
 131 #ifdef CONFIG_SMP
 132         extern struct smp_ops_t smp_85xx_ops;
 133 #endif
 134
 135         if (of_flat_dt_match(root, boards))
 136                 return 1;
 137
 138         /* Check if we're running under the Freescale hypervisor */
 139         if (of_flat_dt_match(root, hv_boards)) {
 140                 ppc_md.init_IRQ = ehv_pic_init;
 141                 ppc_md.get_irq = ehv_pic_get_irq;
 142                 ppc_md.restart = fsl_hv_restart;
 143                 ppc_md.power_off = fsl_hv_halt;
 144                 ppc_md.halt = fsl_hv_halt;
 145 #ifdef CONFIG_SMP
 146                 /*
 147                  * Disable the timebase sync operations because we can't write
 148                  * to the timebase registers under the hypervisor.
 149                   */
 150                 smp_85xx_ops.give_timebase = NULL;
 151                 smp_85xx_ops.take_timebase = NULL;
 152 #endif
 153                 return 1;
 154         }
 155
 156         return 0;
 157 }
 158
 159 define_machine(corenet_generic) {
 160         .name                   = "CoreNet Generic",
 161         .probe                  = corenet_generic_probe,
 162         .setup_arch             = corenet_gen_setup_arch,
 163         .init_IRQ               = corenet_gen_pic_init,
 164 #ifdef CONFIG_PCI
 165         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 166 #endif
 167         .get_irq                = mpic_get_coreint_irq,
 168         .restart                = fsl_rstcr_restart,
 169         .calibrate_decr         = generic_calibrate_decr,
 170         .progress               = udbg_progress,
 171 #ifdef CONFIG_PPC64
 172         .power_save             = book3e_idle,
 173 #else
 174         .power_save             = e500_idle,
 175 #endif
 176 };
 177
 178 machine_arch_initcall(corenet_generic, corenet_gen_publish_devices);
 179
 180 #ifdef CONFIG_SWIOTLB
 181 machine_arch_initcall(corenet_generic, swiotlb_setup_bus_notifier);
 182 #endif