2 * Generic device tree based pinctrl driver for one register per pin
3 * type pinmux controllers
5 * Copyright (C) 2012 Texas Instruments, Inc.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/list.h>
18 #include <linux/interrupt.h>
20 #include <linux/irqchip/chained_irq.h>
23 #include <linux/of_device.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
36 #define DRIVER_NAME "pinctrl-single"
37 #define PCS_MUX_PINS_NAME "pinctrl-single,pins"
38 #define PCS_MUX_BITS_NAME "pinctrl-single,bits"
39 #define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 3)
40 #define PCS_OFF_DISABLED ~0U
43 * struct pcs_pingroup - pingroups for a function
44 * @np: pingroup device node pointer
45 * @name: pingroup name
46 * @gpins: array of the pins in the group
47 * @ngpins: number of pins in the group
51 struct device_node
*np
;
55 struct list_head node
;
59 * struct pcs_func_vals - mux function register offset and value pair
60 * @reg: register virtual address
61 * @val: register value
63 struct pcs_func_vals
{
70 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
71 * and value, enable, disable, mask
72 * @param: config parameter
73 * @val: user input bits in the pinconf register
74 * @enable: enable bits in the pinconf register
75 * @disable: disable bits in the pinconf register
76 * @mask: mask bits in the register value
78 struct pcs_conf_vals
{
79 enum pin_config_param param
;
87 * struct pcs_conf_type - pinconf property name, pinconf param pair
88 * @name: property name in DTS file
89 * @param: config parameter
91 struct pcs_conf_type
{
93 enum pin_config_param param
;
97 * struct pcs_function - pinctrl function
98 * @name: pinctrl function name
99 * @vals: register and vals array
100 * @nvals: number of entries in vals array
101 * @pgnames: array of pingroup names the function uses
102 * @npgnames: number of pingroup names the function uses
105 struct pcs_function
{
107 struct pcs_func_vals
*vals
;
109 const char **pgnames
;
111 struct pcs_conf_vals
*conf
;
113 struct list_head node
;
117 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
118 * @offset: offset base of pins
119 * @npins: number pins with the same mux value of gpio function
120 * @gpiofunc: mux value of gpio function
123 struct pcs_gpiofunc_range
{
127 struct list_head node
;
131 * struct pcs_data - wrapper for data needed by pinctrl framework
133 * @cur: index to current element
135 * REVISIT: We should be able to drop this eventually by adding
136 * support for registering pins individually in the pinctrl
137 * framework for those drivers that don't need a static array.
140 struct pinctrl_pin_desc
*pa
;
145 * struct pcs_name - register name for a pin
146 * @name: name of the pinctrl register
148 * REVISIT: We may want to make names optional in the pinctrl
149 * framework as some drivers may not care about pin names to
150 * avoid kernel bloat. The pin names can be deciphered by user
151 * space tools using debugfs based on the register address and
152 * SoC packaging information.
155 char name
[PCS_REG_NAME_LEN
];
159 * struct pcs_soc_data - SoC specific settings
160 * @flags: initial SoC specific PCS_FEAT_xxx values
161 * @irq: optional interrupt for the controller
162 * @irq_enable_mask: optional SoC specific interrupt enable mask
163 * @irq_status_mask: optional SoC specific interrupt status mask
164 * @rearm: optional SoC specific wake-up rearm function
166 struct pcs_soc_data
{
169 unsigned irq_enable_mask
;
170 unsigned irq_status_mask
;
175 * struct pcs_device - pinctrl device instance
177 * @base: virtual address of the controller
178 * @size: size of the ioremapped area
180 * @pctl: pin controller device
181 * @flags: mask of PCS_FEAT_xxx values
182 * @lock: spinlock for register access
183 * @mutex: mutex protecting the lists
184 * @width: bits per mux register
185 * @fmask: function register mask
186 * @fshift: function register shift
187 * @foff: value to turn mux off
188 * @fmax: max number of functions in fmask
189 * @bits_per_pin:number of bits per pin
190 * @names: array of register names for pins
191 * @pins: physical pins on the SoC
192 * @pgtree: pingroup index radix tree
193 * @ftree: function index radix tree
194 * @pingroups: list of pingroups
195 * @functions: list of functions
196 * @gpiofuncs: list of gpio functions
197 * @irqs: list of interrupt registers
198 * @chip: chip container for this instance
199 * @domain: IRQ domain for this instance
200 * @ngroups: number of pingroups
201 * @nfuncs: number of functions
202 * @desc: pin controller descriptor
203 * @read: register read function to use
204 * @write: register write function to use
207 struct resource
*res
;
211 struct pinctrl_dev
*pctl
;
213 #define PCS_QUIRK_SHARED_IRQ (1 << 2)
214 #define PCS_FEAT_IRQ (1 << 1)
215 #define PCS_FEAT_PINCONF (1 << 0)
216 struct pcs_soc_data socdata
;
225 unsigned bits_per_pin
;
226 struct pcs_name
*names
;
227 struct pcs_data pins
;
228 struct radix_tree_root pgtree
;
229 struct radix_tree_root ftree
;
230 struct list_head pingroups
;
231 struct list_head functions
;
232 struct list_head gpiofuncs
;
233 struct list_head irqs
;
234 struct irq_chip chip
;
235 struct irq_domain
*domain
;
238 struct pinctrl_desc desc
;
239 unsigned (*read
)(void __iomem
*reg
);
240 void (*write
)(unsigned val
, void __iomem
*reg
);
243 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
244 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
245 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
247 static int pcs_pinconf_get(struct pinctrl_dev
*pctldev
, unsigned pin
,
248 unsigned long *config
);
249 static int pcs_pinconf_set(struct pinctrl_dev
*pctldev
, unsigned pin
,
250 unsigned long *configs
, unsigned num_configs
);
252 static enum pin_config_param pcs_bias
[] = {
253 PIN_CONFIG_BIAS_PULL_DOWN
,
254 PIN_CONFIG_BIAS_PULL_UP
,
258 * REVISIT: Reads and writes could eventually use regmap or something
259 * generic. But at least on omaps, some mux registers are performance
260 * critical as they may need to be remuxed every time before and after
261 * idle. Adding tests for register access width for every read and
262 * write like regmap is doing is not desired, and caching the registers
263 * does not help in this case.
266 static unsigned __maybe_unused
pcs_readb(void __iomem
*reg
)
271 static unsigned __maybe_unused
pcs_readw(void __iomem
*reg
)
276 static unsigned __maybe_unused
pcs_readl(void __iomem
*reg
)
281 static void __maybe_unused
pcs_writeb(unsigned val
, void __iomem
*reg
)
286 static void __maybe_unused
pcs_writew(unsigned val
, void __iomem
*reg
)
291 static void __maybe_unused
pcs_writel(unsigned val
, void __iomem
*reg
)
296 static int pcs_get_groups_count(struct pinctrl_dev
*pctldev
)
298 struct pcs_device
*pcs
;
300 pcs
= pinctrl_dev_get_drvdata(pctldev
);
305 static const char *pcs_get_group_name(struct pinctrl_dev
*pctldev
,
308 struct pcs_device
*pcs
;
309 struct pcs_pingroup
*group
;
311 pcs
= pinctrl_dev_get_drvdata(pctldev
);
312 group
= radix_tree_lookup(&pcs
->pgtree
, gselector
);
314 dev_err(pcs
->dev
, "%s could not find pingroup%i\n",
315 __func__
, gselector
);
322 static int pcs_get_group_pins(struct pinctrl_dev
*pctldev
,
324 const unsigned **pins
,
327 struct pcs_device
*pcs
;
328 struct pcs_pingroup
*group
;
330 pcs
= pinctrl_dev_get_drvdata(pctldev
);
331 group
= radix_tree_lookup(&pcs
->pgtree
, gselector
);
333 dev_err(pcs
->dev
, "%s could not find pingroup%i\n",
334 __func__
, gselector
);
338 *pins
= group
->gpins
;
339 *npins
= group
->ngpins
;
344 static void pcs_pin_dbg_show(struct pinctrl_dev
*pctldev
,
348 struct pcs_device
*pcs
;
349 unsigned val
, mux_bytes
;
351 pcs
= pinctrl_dev_get_drvdata(pctldev
);
353 mux_bytes
= pcs
->width
/ BITS_PER_BYTE
;
354 val
= pcs
->read(pcs
->base
+ pin
* mux_bytes
);
356 seq_printf(s
, "%08x %s " , val
, DRIVER_NAME
);
359 static void pcs_dt_free_map(struct pinctrl_dev
*pctldev
,
360 struct pinctrl_map
*map
, unsigned num_maps
)
362 struct pcs_device
*pcs
;
364 pcs
= pinctrl_dev_get_drvdata(pctldev
);
365 devm_kfree(pcs
->dev
, map
);
368 static int pcs_dt_node_to_map(struct pinctrl_dev
*pctldev
,
369 struct device_node
*np_config
,
370 struct pinctrl_map
**map
, unsigned *num_maps
);
372 static const struct pinctrl_ops pcs_pinctrl_ops
= {
373 .get_groups_count
= pcs_get_groups_count
,
374 .get_group_name
= pcs_get_group_name
,
375 .get_group_pins
= pcs_get_group_pins
,
376 .pin_dbg_show
= pcs_pin_dbg_show
,
377 .dt_node_to_map
= pcs_dt_node_to_map
,
378 .dt_free_map
= pcs_dt_free_map
,
381 static int pcs_get_functions_count(struct pinctrl_dev
*pctldev
)
383 struct pcs_device
*pcs
;
385 pcs
= pinctrl_dev_get_drvdata(pctldev
);
390 static const char *pcs_get_function_name(struct pinctrl_dev
*pctldev
,
393 struct pcs_device
*pcs
;
394 struct pcs_function
*func
;
396 pcs
= pinctrl_dev_get_drvdata(pctldev
);
397 func
= radix_tree_lookup(&pcs
->ftree
, fselector
);
399 dev_err(pcs
->dev
, "%s could not find function%i\n",
400 __func__
, fselector
);
407 static int pcs_get_function_groups(struct pinctrl_dev
*pctldev
,
409 const char * const **groups
,
410 unsigned * const ngroups
)
412 struct pcs_device
*pcs
;
413 struct pcs_function
*func
;
415 pcs
= pinctrl_dev_get_drvdata(pctldev
);
416 func
= radix_tree_lookup(&pcs
->ftree
, fselector
);
418 dev_err(pcs
->dev
, "%s could not find function%i\n",
419 __func__
, fselector
);
422 *groups
= func
->pgnames
;
423 *ngroups
= func
->npgnames
;
428 static int pcs_get_function(struct pinctrl_dev
*pctldev
, unsigned pin
,
429 struct pcs_function
**func
)
431 struct pcs_device
*pcs
= pinctrl_dev_get_drvdata(pctldev
);
432 struct pin_desc
*pdesc
= pin_desc_get(pctldev
, pin
);
433 const struct pinctrl_setting_mux
*setting
;
436 /* If pin is not described in DTS & enabled, mux_setting is NULL. */
437 setting
= pdesc
->mux_setting
;
440 fselector
= setting
->func
;
441 *func
= radix_tree_lookup(&pcs
->ftree
, fselector
);
443 dev_err(pcs
->dev
, "%s could not find function%i\n",
444 __func__
, fselector
);
450 static int pcs_enable(struct pinctrl_dev
*pctldev
, unsigned fselector
,
453 struct pcs_device
*pcs
;
454 struct pcs_function
*func
;
457 pcs
= pinctrl_dev_get_drvdata(pctldev
);
458 /* If function mask is null, needn't enable it. */
461 func
= radix_tree_lookup(&pcs
->ftree
, fselector
);
465 dev_dbg(pcs
->dev
, "enabling %s function%i\n",
466 func
->name
, fselector
);
468 for (i
= 0; i
< func
->nvals
; i
++) {
469 struct pcs_func_vals
*vals
;
473 vals
= &func
->vals
[i
];
474 raw_spin_lock_irqsave(&pcs
->lock
, flags
);
475 val
= pcs
->read(vals
->reg
);
477 if (pcs
->bits_per_mux
)
483 val
|= (vals
->val
& mask
);
484 pcs
->write(val
, vals
->reg
);
485 raw_spin_unlock_irqrestore(&pcs
->lock
, flags
);
491 static void pcs_disable(struct pinctrl_dev
*pctldev
, unsigned fselector
,
494 struct pcs_device
*pcs
;
495 struct pcs_function
*func
;
498 pcs
= pinctrl_dev_get_drvdata(pctldev
);
499 /* If function mask is null, needn't disable it. */
503 func
= radix_tree_lookup(&pcs
->ftree
, fselector
);
505 dev_err(pcs
->dev
, "%s could not find function%i\n",
506 __func__
, fselector
);
511 * Ignore disable if function-off is not specified. Some hardware
512 * does not have clearly defined disable function. For pin specific
513 * off modes, you can use alternate named states as described in
514 * pinctrl-bindings.txt.
516 if (pcs
->foff
== PCS_OFF_DISABLED
) {
517 dev_dbg(pcs
->dev
, "ignoring disable for %s function%i\n",
518 func
->name
, fselector
);
522 dev_dbg(pcs
->dev
, "disabling function%i %s\n",
523 fselector
, func
->name
);
525 for (i
= 0; i
< func
->nvals
; i
++) {
526 struct pcs_func_vals
*vals
;
530 vals
= &func
->vals
[i
];
531 raw_spin_lock_irqsave(&pcs
->lock
, flags
);
532 val
= pcs
->read(vals
->reg
);
534 if (pcs
->bits_per_mux
)
540 val
|= pcs
->foff
<< pcs
->fshift
;
541 pcs
->write(val
, vals
->reg
);
542 raw_spin_unlock_irqrestore(&pcs
->lock
, flags
);
546 static int pcs_request_gpio(struct pinctrl_dev
*pctldev
,
547 struct pinctrl_gpio_range
*range
, unsigned pin
)
549 struct pcs_device
*pcs
= pinctrl_dev_get_drvdata(pctldev
);
550 struct pcs_gpiofunc_range
*frange
= NULL
;
551 struct list_head
*pos
, *tmp
;
555 /* If function mask is null, return directly. */
559 list_for_each_safe(pos
, tmp
, &pcs
->gpiofuncs
) {
560 frange
= list_entry(pos
, struct pcs_gpiofunc_range
, node
);
561 if (pin
>= frange
->offset
+ frange
->npins
562 || pin
< frange
->offset
)
564 mux_bytes
= pcs
->width
/ BITS_PER_BYTE
;
565 data
= pcs
->read(pcs
->base
+ pin
* mux_bytes
) & ~pcs
->fmask
;
566 data
|= frange
->gpiofunc
;
567 pcs
->write(data
, pcs
->base
+ pin
* mux_bytes
);
573 static const struct pinmux_ops pcs_pinmux_ops
= {
574 .get_functions_count
= pcs_get_functions_count
,
575 .get_function_name
= pcs_get_function_name
,
576 .get_function_groups
= pcs_get_function_groups
,
577 .enable
= pcs_enable
,
578 .disable
= pcs_disable
,
579 .gpio_request_enable
= pcs_request_gpio
,
582 /* Clear BIAS value */
583 static void pcs_pinconf_clear_bias(struct pinctrl_dev
*pctldev
, unsigned pin
)
585 unsigned long config
;
587 for (i
= 0; i
< ARRAY_SIZE(pcs_bias
); i
++) {
588 config
= pinconf_to_config_packed(pcs_bias
[i
], 0);
589 pcs_pinconf_set(pctldev
, pin
, &config
, 1);
594 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
595 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
597 static bool pcs_pinconf_bias_disable(struct pinctrl_dev
*pctldev
, unsigned pin
)
599 unsigned long config
;
602 for (i
= 0; i
< ARRAY_SIZE(pcs_bias
); i
++) {
603 config
= pinconf_to_config_packed(pcs_bias
[i
], 0);
604 if (!pcs_pinconf_get(pctldev
, pin
, &config
))
612 static int pcs_pinconf_get(struct pinctrl_dev
*pctldev
,
613 unsigned pin
, unsigned long *config
)
615 struct pcs_device
*pcs
= pinctrl_dev_get_drvdata(pctldev
);
616 struct pcs_function
*func
;
617 enum pin_config_param param
;
618 unsigned offset
= 0, data
= 0, i
, j
, ret
;
620 ret
= pcs_get_function(pctldev
, pin
, &func
);
624 for (i
= 0; i
< func
->nconfs
; i
++) {
625 param
= pinconf_to_config_param(*config
);
626 if (param
== PIN_CONFIG_BIAS_DISABLE
) {
627 if (pcs_pinconf_bias_disable(pctldev
, pin
)) {
633 } else if (param
!= func
->conf
[i
].param
) {
637 offset
= pin
* (pcs
->width
/ BITS_PER_BYTE
);
638 data
= pcs
->read(pcs
->base
+ offset
) & func
->conf
[i
].mask
;
639 switch (func
->conf
[i
].param
) {
641 case PIN_CONFIG_BIAS_PULL_DOWN
:
642 case PIN_CONFIG_BIAS_PULL_UP
:
643 case PIN_CONFIG_INPUT_SCHMITT_ENABLE
:
644 if ((data
!= func
->conf
[i
].enable
) ||
645 (data
== func
->conf
[i
].disable
))
650 case PIN_CONFIG_INPUT_SCHMITT
:
651 for (j
= 0; j
< func
->nconfs
; j
++) {
652 switch (func
->conf
[j
].param
) {
653 case PIN_CONFIG_INPUT_SCHMITT_ENABLE
:
654 if (data
!= func
->conf
[j
].enable
)
663 case PIN_CONFIG_DRIVE_STRENGTH
:
664 case PIN_CONFIG_SLEW_RATE
:
674 static int pcs_pinconf_set(struct pinctrl_dev
*pctldev
,
675 unsigned pin
, unsigned long *configs
,
676 unsigned num_configs
)
678 struct pcs_device
*pcs
= pinctrl_dev_get_drvdata(pctldev
);
679 struct pcs_function
*func
;
680 unsigned offset
= 0, shift
= 0, i
, data
, ret
;
684 ret
= pcs_get_function(pctldev
, pin
, &func
);
688 for (j
= 0; j
< num_configs
; j
++) {
689 for (i
= 0; i
< func
->nconfs
; i
++) {
690 if (pinconf_to_config_param(configs
[j
])
691 != func
->conf
[i
].param
)
694 offset
= pin
* (pcs
->width
/ BITS_PER_BYTE
);
695 data
= pcs
->read(pcs
->base
+ offset
);
696 arg
= pinconf_to_config_argument(configs
[j
]);
697 switch (func
->conf
[i
].param
) {
699 case PIN_CONFIG_INPUT_SCHMITT
:
700 case PIN_CONFIG_DRIVE_STRENGTH
:
701 case PIN_CONFIG_SLEW_RATE
:
702 shift
= ffs(func
->conf
[i
].mask
) - 1;
703 data
&= ~func
->conf
[i
].mask
;
704 data
|= (arg
<< shift
) & func
->conf
[i
].mask
;
707 case PIN_CONFIG_BIAS_DISABLE
:
708 pcs_pinconf_clear_bias(pctldev
, pin
);
710 case PIN_CONFIG_BIAS_PULL_DOWN
:
711 case PIN_CONFIG_BIAS_PULL_UP
:
713 pcs_pinconf_clear_bias(pctldev
, pin
);
715 case PIN_CONFIG_INPUT_SCHMITT_ENABLE
:
716 data
&= ~func
->conf
[i
].mask
;
718 data
|= func
->conf
[i
].enable
;
720 data
|= func
->conf
[i
].disable
;
725 pcs
->write(data
, pcs
->base
+ offset
);
729 if (i
>= func
->nconfs
)
731 } /* for each config */
736 static int pcs_pinconf_group_get(struct pinctrl_dev
*pctldev
,
737 unsigned group
, unsigned long *config
)
739 const unsigned *pins
;
740 unsigned npins
, old
= 0;
743 ret
= pcs_get_group_pins(pctldev
, group
, &pins
, &npins
);
746 for (i
= 0; i
< npins
; i
++) {
747 if (pcs_pinconf_get(pctldev
, pins
[i
], config
))
749 /* configs do not match between two pins */
750 if (i
&& (old
!= *config
))
757 static int pcs_pinconf_group_set(struct pinctrl_dev
*pctldev
,
758 unsigned group
, unsigned long *configs
,
759 unsigned num_configs
)
761 const unsigned *pins
;
765 ret
= pcs_get_group_pins(pctldev
, group
, &pins
, &npins
);
768 for (i
= 0; i
< npins
; i
++) {
769 if (pcs_pinconf_set(pctldev
, pins
[i
], configs
, num_configs
))
775 static void pcs_pinconf_dbg_show(struct pinctrl_dev
*pctldev
,
776 struct seq_file
*s
, unsigned pin
)
780 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev
*pctldev
,
781 struct seq_file
*s
, unsigned selector
)
785 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev
*pctldev
,
787 unsigned long config
)
789 pinconf_generic_dump_config(pctldev
, s
, config
);
792 static const struct pinconf_ops pcs_pinconf_ops
= {
793 .pin_config_get
= pcs_pinconf_get
,
794 .pin_config_set
= pcs_pinconf_set
,
795 .pin_config_group_get
= pcs_pinconf_group_get
,
796 .pin_config_group_set
= pcs_pinconf_group_set
,
797 .pin_config_dbg_show
= pcs_pinconf_dbg_show
,
798 .pin_config_group_dbg_show
= pcs_pinconf_group_dbg_show
,
799 .pin_config_config_dbg_show
= pcs_pinconf_config_dbg_show
,
804 * pcs_add_pin() - add a pin to the static per controller pin array
805 * @pcs: pcs driver instance
806 * @offset: register offset from base
808 static int pcs_add_pin(struct pcs_device
*pcs
, unsigned offset
,
811 struct pinctrl_pin_desc
*pin
;
816 if (i
>= pcs
->desc
.npins
) {
817 dev_err(pcs
->dev
, "too many pins, max %i\n",
822 pin
= &pcs
->pins
.pa
[i
];
824 sprintf(pn
->name
, "%lx.%d",
825 (unsigned long)pcs
->res
->start
+ offset
, pin_pos
);
826 pin
->name
= pn
->name
;
834 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
835 * @pcs: pcs driver instance
837 * In case of errors, resources are freed in pcs_free_resources.
839 * If your hardware needs holes in the address space, then just set
840 * up multiple driver instances.
842 static int pcs_allocate_pin_table(struct pcs_device
*pcs
)
844 int mux_bytes
, nr_pins
, i
;
845 int num_pins_in_register
= 0;
847 mux_bytes
= pcs
->width
/ BITS_PER_BYTE
;
849 if (pcs
->bits_per_mux
) {
850 pcs
->bits_per_pin
= fls(pcs
->fmask
);
851 nr_pins
= (pcs
->size
* BITS_PER_BYTE
) / pcs
->bits_per_pin
;
852 num_pins_in_register
= pcs
->width
/ pcs
->bits_per_pin
;
854 nr_pins
= pcs
->size
/ mux_bytes
;
857 dev_dbg(pcs
->dev
, "allocating %i pins\n", nr_pins
);
858 pcs
->pins
.pa
= devm_kzalloc(pcs
->dev
,
859 sizeof(*pcs
->pins
.pa
) * nr_pins
,
864 pcs
->names
= devm_kzalloc(pcs
->dev
,
865 sizeof(struct pcs_name
) * nr_pins
,
870 pcs
->desc
.pins
= pcs
->pins
.pa
;
871 pcs
->desc
.npins
= nr_pins
;
873 for (i
= 0; i
< pcs
->desc
.npins
; i
++) {
879 if (pcs
->bits_per_mux
) {
880 byte_num
= (pcs
->bits_per_pin
* i
) / BITS_PER_BYTE
;
881 offset
= (byte_num
/ mux_bytes
) * mux_bytes
;
882 pin_pos
= i
% num_pins_in_register
;
884 offset
= i
* mux_bytes
;
886 res
= pcs_add_pin(pcs
, offset
, pin_pos
);
888 dev_err(pcs
->dev
, "error adding pins: %i\n", res
);
897 * pcs_add_function() - adds a new function to the function list
898 * @pcs: pcs driver instance
899 * @np: device node of the mux entry
900 * @name: name of the function
901 * @vals: array of mux register value pairs used by the function
902 * @nvals: number of mux register value pairs
903 * @pgnames: array of pingroup names for the function
904 * @npgnames: number of pingroup names
906 static struct pcs_function
*pcs_add_function(struct pcs_device
*pcs
,
907 struct device_node
*np
,
909 struct pcs_func_vals
*vals
,
911 const char **pgnames
,
914 struct pcs_function
*function
;
916 function
= devm_kzalloc(pcs
->dev
, sizeof(*function
), GFP_KERNEL
);
920 function
->name
= name
;
921 function
->vals
= vals
;
922 function
->nvals
= nvals
;
923 function
->pgnames
= pgnames
;
924 function
->npgnames
= npgnames
;
926 mutex_lock(&pcs
->mutex
);
927 list_add_tail(&function
->node
, &pcs
->functions
);
928 radix_tree_insert(&pcs
->ftree
, pcs
->nfuncs
, function
);
930 mutex_unlock(&pcs
->mutex
);
935 static void pcs_remove_function(struct pcs_device
*pcs
,
936 struct pcs_function
*function
)
940 mutex_lock(&pcs
->mutex
);
941 for (i
= 0; i
< pcs
->nfuncs
; i
++) {
942 struct pcs_function
*found
;
944 found
= radix_tree_lookup(&pcs
->ftree
, i
);
945 if (found
== function
)
946 radix_tree_delete(&pcs
->ftree
, i
);
948 list_del(&function
->node
);
949 mutex_unlock(&pcs
->mutex
);
953 * pcs_add_pingroup() - add a pingroup to the pingroup list
954 * @pcs: pcs driver instance
955 * @np: device node of the mux entry
956 * @name: name of the pingroup
957 * @gpins: array of the pins that belong to the group
958 * @ngpins: number of pins in the group
960 static int pcs_add_pingroup(struct pcs_device
*pcs
,
961 struct device_node
*np
,
966 struct pcs_pingroup
*pingroup
;
968 pingroup
= devm_kzalloc(pcs
->dev
, sizeof(*pingroup
), GFP_KERNEL
);
972 pingroup
->name
= name
;
974 pingroup
->gpins
= gpins
;
975 pingroup
->ngpins
= ngpins
;
977 mutex_lock(&pcs
->mutex
);
978 list_add_tail(&pingroup
->node
, &pcs
->pingroups
);
979 radix_tree_insert(&pcs
->pgtree
, pcs
->ngroups
, pingroup
);
981 mutex_unlock(&pcs
->mutex
);
987 * pcs_get_pin_by_offset() - get a pin index based on the register offset
988 * @pcs: pcs driver instance
989 * @offset: register offset from the base
991 * Note that this is OK as long as the pins are in a static array.
993 static int pcs_get_pin_by_offset(struct pcs_device
*pcs
, unsigned offset
)
997 if (offset
>= pcs
->size
) {
998 dev_err(pcs
->dev
, "mux offset out of range: 0x%x (0x%x)\n",
1003 if (pcs
->bits_per_mux
)
1004 index
= (offset
* BITS_PER_BYTE
) / pcs
->bits_per_pin
;
1006 index
= offset
/ (pcs
->width
/ BITS_PER_BYTE
);
1012 * check whether data matches enable bits or disable bits
1013 * Return value: 1 for matching enable bits, 0 for matching disable bits,
1014 * and negative value for matching failure.
1016 static int pcs_config_match(unsigned data
, unsigned enable
, unsigned disable
)
1022 else if (data
== disable
)
1027 static void add_config(struct pcs_conf_vals
**conf
, enum pin_config_param param
,
1028 unsigned value
, unsigned enable
, unsigned disable
,
1031 (*conf
)->param
= param
;
1032 (*conf
)->val
= value
;
1033 (*conf
)->enable
= enable
;
1034 (*conf
)->disable
= disable
;
1035 (*conf
)->mask
= mask
;
1039 static void add_setting(unsigned long **setting
, enum pin_config_param param
,
1042 **setting
= pinconf_to_config_packed(param
, arg
);
1046 /* add pinconf setting with 2 parameters */
1047 static void pcs_add_conf2(struct pcs_device
*pcs
, struct device_node
*np
,
1048 const char *name
, enum pin_config_param param
,
1049 struct pcs_conf_vals
**conf
, unsigned long **settings
)
1051 unsigned value
[2], shift
;
1054 ret
= of_property_read_u32_array(np
, name
, value
, 2);
1057 /* set value & mask */
1058 value
[0] &= value
[1];
1059 shift
= ffs(value
[1]) - 1;
1060 /* skip enable & disable */
1061 add_config(conf
, param
, value
[0], 0, 0, value
[1]);
1062 add_setting(settings
, param
, value
[0] >> shift
);
1065 /* add pinconf setting with 4 parameters */
1066 static void pcs_add_conf4(struct pcs_device
*pcs
, struct device_node
*np
,
1067 const char *name
, enum pin_config_param param
,
1068 struct pcs_conf_vals
**conf
, unsigned long **settings
)
1073 /* value to set, enable, disable, mask */
1074 ret
= of_property_read_u32_array(np
, name
, value
, 4);
1078 dev_err(pcs
->dev
, "mask field of the property can't be 0\n");
1081 value
[0] &= value
[3];
1082 value
[1] &= value
[3];
1083 value
[2] &= value
[3];
1084 ret
= pcs_config_match(value
[0], value
[1], value
[2]);
1086 dev_dbg(pcs
->dev
, "failed to match enable or disable bits\n");
1087 add_config(conf
, param
, value
[0], value
[1], value
[2], value
[3]);
1088 add_setting(settings
, param
, ret
);
1091 static int pcs_parse_pinconf(struct pcs_device
*pcs
, struct device_node
*np
,
1092 struct pcs_function
*func
,
1093 struct pinctrl_map
**map
)
1096 struct pinctrl_map
*m
= *map
;
1097 int i
= 0, nconfs
= 0;
1098 unsigned long *settings
= NULL
, *s
= NULL
;
1099 struct pcs_conf_vals
*conf
= NULL
;
1100 struct pcs_conf_type prop2
[] = {
1101 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH
, },
1102 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE
, },
1103 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT
, },
1105 struct pcs_conf_type prop4
[] = {
1106 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP
, },
1107 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN
, },
1108 { "pinctrl-single,input-schmitt-enable",
1109 PIN_CONFIG_INPUT_SCHMITT_ENABLE
, },
1112 /* If pinconf isn't supported, don't parse properties in below. */
1113 if (!PCS_HAS_PINCONF
)
1116 /* cacluate how much properties are supported in current node */
1117 for (i
= 0; i
< ARRAY_SIZE(prop2
); i
++) {
1118 if (of_find_property(np
, prop2
[i
].name
, NULL
))
1121 for (i
= 0; i
< ARRAY_SIZE(prop4
); i
++) {
1122 if (of_find_property(np
, prop4
[i
].name
, NULL
))
1128 func
->conf
= devm_kzalloc(pcs
->dev
,
1129 sizeof(struct pcs_conf_vals
) * nconfs
,
1133 func
->nconfs
= nconfs
;
1134 conf
= &(func
->conf
[0]);
1136 settings
= devm_kzalloc(pcs
->dev
, sizeof(unsigned long) * nconfs
,
1142 for (i
= 0; i
< ARRAY_SIZE(prop2
); i
++)
1143 pcs_add_conf2(pcs
, np
, prop2
[i
].name
, prop2
[i
].param
,
1145 for (i
= 0; i
< ARRAY_SIZE(prop4
); i
++)
1146 pcs_add_conf4(pcs
, np
, prop4
[i
].name
, prop4
[i
].param
,
1148 m
->type
= PIN_MAP_TYPE_CONFIGS_GROUP
;
1149 m
->data
.configs
.group_or_pin
= np
->name
;
1150 m
->data
.configs
.configs
= settings
;
1151 m
->data
.configs
.num_configs
= nconfs
;
1155 static void pcs_free_pingroups(struct pcs_device
*pcs
);
1158 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
1159 * @pcs: pinctrl driver instance
1160 * @np: device node of the mux entry
1162 * @num_maps: number of map
1163 * @pgnames: pingroup names
1165 * Note that this binding currently supports only sets of one register + value.
1167 * Also note that this driver tries to avoid understanding pin and function
1168 * names because of the extra bloat they would cause especially in the case of
1169 * a large number of pins. This driver just sets what is specified for the board
1170 * in the .dts file. Further user space debugging tools can be developed to
1171 * decipher the pin and function names using debugfs.
1173 * If you are concerned about the boot time, set up the static pins in
1174 * the bootloader, and only set up selected pins as device tree entries.
1176 static int pcs_parse_one_pinctrl_entry(struct pcs_device
*pcs
,
1177 struct device_node
*np
,
1178 struct pinctrl_map
**map
,
1180 const char **pgnames
)
1182 struct pcs_func_vals
*vals
;
1184 int size
, rows
, *pins
, index
= 0, found
= 0, res
= -ENOMEM
;
1185 struct pcs_function
*function
;
1187 mux
= of_get_property(np
, PCS_MUX_PINS_NAME
, &size
);
1188 if ((!mux
) || (size
< sizeof(*mux
) * 2)) {
1189 dev_err(pcs
->dev
, "bad data for mux %s\n",
1194 size
/= sizeof(*mux
); /* Number of elements in array */
1197 vals
= devm_kzalloc(pcs
->dev
, sizeof(*vals
) * rows
, GFP_KERNEL
);
1201 pins
= devm_kzalloc(pcs
->dev
, sizeof(*pins
) * rows
, GFP_KERNEL
);
1205 while (index
< size
) {
1206 unsigned offset
, val
;
1209 offset
= be32_to_cpup(mux
+ index
++);
1210 val
= be32_to_cpup(mux
+ index
++);
1211 vals
[found
].reg
= pcs
->base
+ offset
;
1212 vals
[found
].val
= val
;
1214 pin
= pcs_get_pin_by_offset(pcs
, offset
);
1217 "could not add functions for %s %ux\n",
1221 pins
[found
++] = pin
;
1224 pgnames
[0] = np
->name
;
1225 function
= pcs_add_function(pcs
, np
, np
->name
, vals
, found
, pgnames
, 1);
1229 res
= pcs_add_pingroup(pcs
, np
, np
->name
, pins
, found
);
1233 (*map
)->type
= PIN_MAP_TYPE_MUX_GROUP
;
1234 (*map
)->data
.mux
.group
= np
->name
;
1235 (*map
)->data
.mux
.function
= np
->name
;
1237 if (PCS_HAS_PINCONF
) {
1238 res
= pcs_parse_pinconf(pcs
, np
, function
, map
);
1240 goto free_pingroups
;
1248 pcs_free_pingroups(pcs
);
1251 pcs_remove_function(pcs
, function
);
1254 devm_kfree(pcs
->dev
, pins
);
1257 devm_kfree(pcs
->dev
, vals
);
1262 #define PARAMS_FOR_BITS_PER_MUX 3
1264 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device
*pcs
,
1265 struct device_node
*np
,
1266 struct pinctrl_map
**map
,
1268 const char **pgnames
)
1270 struct pcs_func_vals
*vals
;
1272 int size
, rows
, *pins
, index
= 0, found
= 0, res
= -ENOMEM
;
1274 struct pcs_function
*function
;
1276 mux
= of_get_property(np
, PCS_MUX_BITS_NAME
, &size
);
1279 dev_err(pcs
->dev
, "no valid property for %s\n", np
->name
);
1283 if (size
< (sizeof(*mux
) * PARAMS_FOR_BITS_PER_MUX
)) {
1284 dev_err(pcs
->dev
, "bad data for %s\n", np
->name
);
1288 /* Number of elements in array */
1289 size
/= sizeof(*mux
);
1291 rows
= size
/ PARAMS_FOR_BITS_PER_MUX
;
1292 npins_in_row
= pcs
->width
/ pcs
->bits_per_pin
;
1294 vals
= devm_kzalloc(pcs
->dev
, sizeof(*vals
) * rows
* npins_in_row
,
1299 pins
= devm_kzalloc(pcs
->dev
, sizeof(*pins
) * rows
* npins_in_row
,
1304 while (index
< size
) {
1305 unsigned offset
, val
;
1306 unsigned mask
, bit_pos
, val_pos
, mask_pos
, submask
;
1307 unsigned pin_num_from_lsb
;
1310 offset
= be32_to_cpup(mux
+ index
++);
1311 val
= be32_to_cpup(mux
+ index
++);
1312 mask
= be32_to_cpup(mux
+ index
++);
1314 /* Parse pins in each row from LSB */
1316 bit_pos
= ffs(mask
);
1317 pin_num_from_lsb
= bit_pos
/ pcs
->bits_per_pin
;
1318 mask_pos
= ((pcs
->fmask
) << (bit_pos
- 1));
1319 val_pos
= val
& mask_pos
;
1320 submask
= mask
& mask_pos
;
1322 if ((mask
& mask_pos
) == 0) {
1324 "Invalid mask for %s at 0x%x\n",
1331 if (submask
!= mask_pos
) {
1333 "Invalid submask 0x%x for %s at 0x%x\n",
1334 submask
, np
->name
, offset
);
1338 vals
[found
].mask
= submask
;
1339 vals
[found
].reg
= pcs
->base
+ offset
;
1340 vals
[found
].val
= val_pos
;
1342 pin
= pcs_get_pin_by_offset(pcs
, offset
);
1345 "could not add functions for %s %ux\n",
1349 pins
[found
++] = pin
+ pin_num_from_lsb
;
1353 pgnames
[0] = np
->name
;
1354 function
= pcs_add_function(pcs
, np
, np
->name
, vals
, found
, pgnames
, 1);
1358 res
= pcs_add_pingroup(pcs
, np
, np
->name
, pins
, found
);
1362 (*map
)->type
= PIN_MAP_TYPE_MUX_GROUP
;
1363 (*map
)->data
.mux
.group
= np
->name
;
1364 (*map
)->data
.mux
.function
= np
->name
;
1366 if (PCS_HAS_PINCONF
) {
1367 dev_err(pcs
->dev
, "pinconf not supported\n");
1368 goto free_pingroups
;
1375 pcs_free_pingroups(pcs
);
1378 pcs_remove_function(pcs
, function
);
1381 devm_kfree(pcs
->dev
, pins
);
1384 devm_kfree(pcs
->dev
, vals
);
1389 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1390 * @pctldev: pinctrl instance
1391 * @np_config: device tree pinmux entry
1392 * @map: array of map entries
1393 * @num_maps: number of maps
1395 static int pcs_dt_node_to_map(struct pinctrl_dev
*pctldev
,
1396 struct device_node
*np_config
,
1397 struct pinctrl_map
**map
, unsigned *num_maps
)
1399 struct pcs_device
*pcs
;
1400 const char **pgnames
;
1403 pcs
= pinctrl_dev_get_drvdata(pctldev
);
1405 /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1406 *map
= devm_kzalloc(pcs
->dev
, sizeof(**map
) * 2, GFP_KERNEL
);
1412 pgnames
= devm_kzalloc(pcs
->dev
, sizeof(*pgnames
), GFP_KERNEL
);
1418 if (pcs
->bits_per_mux
) {
1419 ret
= pcs_parse_bits_in_pinctrl_entry(pcs
, np_config
, map
,
1422 dev_err(pcs
->dev
, "no pins entries for %s\n",
1427 ret
= pcs_parse_one_pinctrl_entry(pcs
, np_config
, map
,
1430 dev_err(pcs
->dev
, "no pins entries for %s\n",
1439 devm_kfree(pcs
->dev
, pgnames
);
1441 devm_kfree(pcs
->dev
, *map
);
1447 * pcs_free_funcs() - free memory used by functions
1448 * @pcs: pcs driver instance
1450 static void pcs_free_funcs(struct pcs_device
*pcs
)
1452 struct list_head
*pos
, *tmp
;
1455 mutex_lock(&pcs
->mutex
);
1456 for (i
= 0; i
< pcs
->nfuncs
; i
++) {
1457 struct pcs_function
*func
;
1459 func
= radix_tree_lookup(&pcs
->ftree
, i
);
1462 radix_tree_delete(&pcs
->ftree
, i
);
1464 list_for_each_safe(pos
, tmp
, &pcs
->functions
) {
1465 struct pcs_function
*function
;
1467 function
= list_entry(pos
, struct pcs_function
, node
);
1468 list_del(&function
->node
);
1470 mutex_unlock(&pcs
->mutex
);
1474 * pcs_free_pingroups() - free memory used by pingroups
1475 * @pcs: pcs driver instance
1477 static void pcs_free_pingroups(struct pcs_device
*pcs
)
1479 struct list_head
*pos
, *tmp
;
1482 mutex_lock(&pcs
->mutex
);
1483 for (i
= 0; i
< pcs
->ngroups
; i
++) {
1484 struct pcs_pingroup
*pingroup
;
1486 pingroup
= radix_tree_lookup(&pcs
->pgtree
, i
);
1489 radix_tree_delete(&pcs
->pgtree
, i
);
1491 list_for_each_safe(pos
, tmp
, &pcs
->pingroups
) {
1492 struct pcs_pingroup
*pingroup
;
1494 pingroup
= list_entry(pos
, struct pcs_pingroup
, node
);
1495 list_del(&pingroup
->node
);
1497 mutex_unlock(&pcs
->mutex
);
1501 * pcs_irq_free() - free interrupt
1502 * @pcs: pcs driver instance
1504 static void pcs_irq_free(struct pcs_device
*pcs
)
1506 struct pcs_soc_data
*pcs_soc
= &pcs
->socdata
;
1508 if (pcs_soc
->irq
< 0)
1512 irq_domain_remove(pcs
->domain
);
1514 if (PCS_QUIRK_HAS_SHARED_IRQ
)
1515 free_irq(pcs_soc
->irq
, pcs_soc
);
1517 irq_set_chained_handler(pcs_soc
->irq
, NULL
);
1521 * pcs_free_resources() - free memory used by this driver
1522 * @pcs: pcs driver instance
1524 static void pcs_free_resources(struct pcs_device
*pcs
)
1529 pinctrl_unregister(pcs
->pctl
);
1531 pcs_free_funcs(pcs
);
1532 pcs_free_pingroups(pcs
);
1535 #define PCS_GET_PROP_U32(name, reg, err) \
1537 ret = of_property_read_u32(np, name, reg); \
1539 dev_err(pcs->dev, err); \
1544 static struct of_device_id pcs_of_match
[];
1546 static int pcs_add_gpio_func(struct device_node
*node
, struct pcs_device
*pcs
)
1548 const char *propname
= "pinctrl-single,gpio-range";
1549 const char *cellname
= "#pinctrl-single,gpio-range-cells";
1550 struct of_phandle_args gpiospec
;
1551 struct pcs_gpiofunc_range
*range
;
1554 for (i
= 0; ; i
++) {
1555 ret
= of_parse_phandle_with_args(node
, propname
, cellname
,
1557 /* Do not treat it as error. Only treat it as end condition. */
1562 range
= devm_kzalloc(pcs
->dev
, sizeof(*range
), GFP_KERNEL
);
1567 range
->offset
= gpiospec
.args
[0];
1568 range
->npins
= gpiospec
.args
[1];
1569 range
->gpiofunc
= gpiospec
.args
[2];
1570 mutex_lock(&pcs
->mutex
);
1571 list_add_tail(&range
->node
, &pcs
->gpiofuncs
);
1572 mutex_unlock(&pcs
->mutex
);
1577 * @reg: virtual address of interrupt register
1578 * @hwirq: hardware irq number
1579 * @irq: virtual irq number
1582 struct pcs_interrupt
{
1584 irq_hw_number_t hwirq
;
1586 struct list_head node
;
1590 * pcs_irq_set() - enables or disables an interrupt
1592 * Note that this currently assumes one interrupt per pinctrl
1593 * register that is typically used for wake-up events.
1595 static inline void pcs_irq_set(struct pcs_soc_data
*pcs_soc
,
1596 int irq
, const bool enable
)
1598 struct pcs_device
*pcs
;
1599 struct list_head
*pos
;
1602 pcs
= container_of(pcs_soc
, struct pcs_device
, socdata
);
1603 list_for_each(pos
, &pcs
->irqs
) {
1604 struct pcs_interrupt
*pcswi
;
1607 pcswi
= list_entry(pos
, struct pcs_interrupt
, node
);
1608 if (irq
!= pcswi
->irq
)
1611 soc_mask
= pcs_soc
->irq_enable_mask
;
1612 raw_spin_lock(&pcs
->lock
);
1613 mask
= pcs
->read(pcswi
->reg
);
1618 pcs
->write(mask
, pcswi
->reg
);
1619 raw_spin_unlock(&pcs
->lock
);
1627 * pcs_irq_mask() - mask pinctrl interrupt
1628 * @d: interrupt data
1630 static void pcs_irq_mask(struct irq_data
*d
)
1632 struct pcs_soc_data
*pcs_soc
= irq_data_get_irq_chip_data(d
);
1634 pcs_irq_set(pcs_soc
, d
->irq
, false);
1638 * pcs_irq_unmask() - unmask pinctrl interrupt
1639 * @d: interrupt data
1641 static void pcs_irq_unmask(struct irq_data
*d
)
1643 struct pcs_soc_data
*pcs_soc
= irq_data_get_irq_chip_data(d
);
1645 pcs_irq_set(pcs_soc
, d
->irq
, true);
1649 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1650 * @d: interrupt data
1651 * @state: wake-up state
1653 * Note that this should be called only for suspend and resume.
1654 * For runtime PM, the wake-up events should be enabled by default.
1656 static int pcs_irq_set_wake(struct irq_data
*d
, unsigned int state
)
1667 * pcs_irq_handle() - common interrupt handler
1668 * @pcs_irq: interrupt data
1670 * Note that this currently assumes we have one interrupt bit per
1671 * mux register. This interrupt is typically used for wake-up events.
1672 * For more complex interrupts different handlers can be specified.
1674 static int pcs_irq_handle(struct pcs_soc_data
*pcs_soc
)
1676 struct pcs_device
*pcs
;
1677 struct list_head
*pos
;
1680 pcs
= container_of(pcs_soc
, struct pcs_device
, socdata
);
1681 list_for_each(pos
, &pcs
->irqs
) {
1682 struct pcs_interrupt
*pcswi
;
1685 pcswi
= list_entry(pos
, struct pcs_interrupt
, node
);
1686 raw_spin_lock(&pcs
->lock
);
1687 mask
= pcs
->read(pcswi
->reg
);
1688 raw_spin_unlock(&pcs
->lock
);
1689 if (mask
& pcs_soc
->irq_status_mask
) {
1690 generic_handle_irq(irq_find_mapping(pcs
->domain
,
1700 * pcs_irq_handler() - handler for the shared interrupt case
1704 * Use this for cases where multiple instances of
1705 * pinctrl-single share a single interrupt like on omaps.
1707 static irqreturn_t
pcs_irq_handler(int irq
, void *d
)
1709 struct pcs_soc_data
*pcs_soc
= d
;
1711 return pcs_irq_handle(pcs_soc
) ? IRQ_HANDLED
: IRQ_NONE
;
1715 * pcs_irq_handle() - handler for the dedicated chained interrupt case
1717 * @desc: interrupt descriptor
1719 * Use this if you have a separate interrupt for each
1720 * pinctrl-single instance.
1722 static void pcs_irq_chain_handler(unsigned int irq
, struct irq_desc
*desc
)
1724 struct pcs_soc_data
*pcs_soc
= irq_desc_get_handler_data(desc
);
1725 struct irq_chip
*chip
;
1728 chip
= irq_get_chip(irq
);
1729 chained_irq_enter(chip
, desc
);
1730 res
= pcs_irq_handle(pcs_soc
);
1731 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1732 chained_irq_exit(chip
, desc
);
1737 static int pcs_irqdomain_map(struct irq_domain
*d
, unsigned int irq
,
1738 irq_hw_number_t hwirq
)
1740 struct pcs_soc_data
*pcs_soc
= d
->host_data
;
1741 struct pcs_device
*pcs
;
1742 struct pcs_interrupt
*pcswi
;
1744 pcs
= container_of(pcs_soc
, struct pcs_device
, socdata
);
1745 pcswi
= devm_kzalloc(pcs
->dev
, sizeof(*pcswi
), GFP_KERNEL
);
1749 pcswi
->reg
= pcs
->base
+ hwirq
;
1750 pcswi
->hwirq
= hwirq
;
1753 mutex_lock(&pcs
->mutex
);
1754 list_add_tail(&pcswi
->node
, &pcs
->irqs
);
1755 mutex_unlock(&pcs
->mutex
);
1757 irq_set_chip_data(irq
, pcs_soc
);
1758 irq_set_chip_and_handler(irq
, &pcs
->chip
,
1762 set_irq_flags(irq
, IRQF_VALID
);
1764 irq_set_noprobe(irq
);
1770 static struct irq_domain_ops pcs_irqdomain_ops
= {
1771 .map
= pcs_irqdomain_map
,
1772 .xlate
= irq_domain_xlate_onecell
,
1776 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1777 * @pcs: pcs driver instance
1778 * @np: device node pointer
1780 static int pcs_irq_init_chained_handler(struct pcs_device
*pcs
,
1781 struct device_node
*np
)
1783 struct pcs_soc_data
*pcs_soc
= &pcs
->socdata
;
1784 const char *name
= "pinctrl";
1787 if (!pcs_soc
->irq_enable_mask
||
1788 !pcs_soc
->irq_status_mask
) {
1793 INIT_LIST_HEAD(&pcs
->irqs
);
1794 pcs
->chip
.name
= name
;
1795 pcs
->chip
.irq_ack
= pcs_irq_mask
;
1796 pcs
->chip
.irq_mask
= pcs_irq_mask
;
1797 pcs
->chip
.irq_unmask
= pcs_irq_unmask
;
1798 pcs
->chip
.irq_set_wake
= pcs_irq_set_wake
;
1800 if (PCS_QUIRK_HAS_SHARED_IRQ
) {
1803 res
= request_irq(pcs_soc
->irq
, pcs_irq_handler
,
1804 IRQF_SHARED
| IRQF_NO_SUSPEND
,
1811 irq_set_handler_data(pcs_soc
->irq
, pcs_soc
);
1812 irq_set_chained_handler(pcs_soc
->irq
,
1813 pcs_irq_chain_handler
);
1817 * We can use the register offset as the hardirq
1818 * number as irq_domain_add_simple maps them lazily.
1819 * This way we can easily support more than one
1820 * interrupt per function if needed.
1822 num_irqs
= pcs
->size
;
1824 pcs
->domain
= irq_domain_add_simple(np
, num_irqs
, 0,
1828 irq_set_chained_handler(pcs_soc
->irq
, NULL
);
1836 static int pinctrl_single_suspend(struct platform_device
*pdev
,
1839 struct pcs_device
*pcs
;
1841 pcs
= platform_get_drvdata(pdev
);
1845 return pinctrl_force_sleep(pcs
->pctl
);
1848 static int pinctrl_single_resume(struct platform_device
*pdev
)
1850 struct pcs_device
*pcs
;
1852 pcs
= platform_get_drvdata(pdev
);
1856 return pinctrl_force_default(pcs
->pctl
);
1860 static int pcs_probe(struct platform_device
*pdev
)
1862 struct device_node
*np
= pdev
->dev
.of_node
;
1863 const struct of_device_id
*match
;
1864 struct pcs_pdata
*pdata
;
1865 struct resource
*res
;
1866 struct pcs_device
*pcs
;
1867 const struct pcs_soc_data
*soc
;
1870 match
= of_match_device(pcs_of_match
, &pdev
->dev
);
1874 pcs
= devm_kzalloc(&pdev
->dev
, sizeof(*pcs
), GFP_KERNEL
);
1876 dev_err(&pdev
->dev
, "could not allocate\n");
1879 pcs
->dev
= &pdev
->dev
;
1880 raw_spin_lock_init(&pcs
->lock
);
1881 mutex_init(&pcs
->mutex
);
1882 INIT_LIST_HEAD(&pcs
->pingroups
);
1883 INIT_LIST_HEAD(&pcs
->functions
);
1884 INIT_LIST_HEAD(&pcs
->gpiofuncs
);
1886 pcs
->flags
= soc
->flags
;
1887 memcpy(&pcs
->socdata
, soc
, sizeof(*soc
));
1889 PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs
->width
,
1890 "register width not specified\n");
1892 ret
= of_property_read_u32(np
, "pinctrl-single,function-mask",
1895 pcs
->fshift
= ffs(pcs
->fmask
) - 1;
1896 pcs
->fmax
= pcs
->fmask
>> pcs
->fshift
;
1898 /* If mask property doesn't exist, function mux is invalid. */
1904 ret
= of_property_read_u32(np
, "pinctrl-single,function-off",
1907 pcs
->foff
= PCS_OFF_DISABLED
;
1909 pcs
->bits_per_mux
= of_property_read_bool(np
,
1910 "pinctrl-single,bit-per-mux");
1912 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1914 dev_err(pcs
->dev
, "could not get resource\n");
1918 pcs
->res
= devm_request_mem_region(pcs
->dev
, res
->start
,
1919 resource_size(res
), DRIVER_NAME
);
1921 dev_err(pcs
->dev
, "could not get mem_region\n");
1925 pcs
->size
= resource_size(pcs
->res
);
1926 pcs
->base
= devm_ioremap(pcs
->dev
, pcs
->res
->start
, pcs
->size
);
1928 dev_err(pcs
->dev
, "could not ioremap\n");
1932 INIT_RADIX_TREE(&pcs
->pgtree
, GFP_KERNEL
);
1933 INIT_RADIX_TREE(&pcs
->ftree
, GFP_KERNEL
);
1934 platform_set_drvdata(pdev
, pcs
);
1936 switch (pcs
->width
) {
1938 pcs
->read
= pcs_readb
;
1939 pcs
->write
= pcs_writeb
;
1942 pcs
->read
= pcs_readw
;
1943 pcs
->write
= pcs_writew
;
1946 pcs
->read
= pcs_readl
;
1947 pcs
->write
= pcs_writel
;
1953 pcs
->desc
.name
= DRIVER_NAME
;
1954 pcs
->desc
.pctlops
= &pcs_pinctrl_ops
;
1955 pcs
->desc
.pmxops
= &pcs_pinmux_ops
;
1956 if (PCS_HAS_PINCONF
)
1957 pcs
->desc
.confops
= &pcs_pinconf_ops
;
1958 pcs
->desc
.owner
= THIS_MODULE
;
1960 ret
= pcs_allocate_pin_table(pcs
);
1964 pcs
->pctl
= pinctrl_register(&pcs
->desc
, pcs
->dev
, pcs
);
1966 dev_err(pcs
->dev
, "could not register single pinctrl driver\n");
1971 ret
= pcs_add_gpio_func(np
, pcs
);
1975 pcs
->socdata
.irq
= irq_of_parse_and_map(np
, 0);
1976 if (pcs
->socdata
.irq
)
1977 pcs
->flags
|= PCS_FEAT_IRQ
;
1979 /* We still need auxdata for some omaps for PRM interrupts */
1980 pdata
= dev_get_platdata(&pdev
->dev
);
1983 pcs
->socdata
.rearm
= pdata
->rearm
;
1985 pcs
->socdata
.irq
= pdata
->irq
;
1986 pcs
->flags
|= PCS_FEAT_IRQ
;
1991 ret
= pcs_irq_init_chained_handler(pcs
, np
);
1993 dev_warn(pcs
->dev
, "initialized with no interrupts\n");
1996 dev_info(pcs
->dev
, "%i pins at pa %p size %u\n",
1997 pcs
->desc
.npins
, pcs
->base
, pcs
->size
);
2002 pcs_free_resources(pcs
);
2007 static int pcs_remove(struct platform_device
*pdev
)
2009 struct pcs_device
*pcs
= platform_get_drvdata(pdev
);
2014 pcs_free_resources(pcs
);
2019 static const struct pcs_soc_data pinctrl_single_omap_wkup
= {
2020 .flags
= PCS_QUIRK_SHARED_IRQ
,
2021 .irq_enable_mask
= (1 << 14), /* OMAP_WAKEUP_EN */
2022 .irq_status_mask
= (1 << 15), /* OMAP_WAKEUP_EVENT */
2025 static const struct pcs_soc_data pinctrl_single
= {
2028 static const struct pcs_soc_data pinconf_single
= {
2029 .flags
= PCS_FEAT_PINCONF
,
2032 static struct of_device_id pcs_of_match
[] = {
2033 { .compatible
= "ti,omap3-padconf", .data
= &pinctrl_single_omap_wkup
},
2034 { .compatible
= "ti,omap4-padconf", .data
= &pinctrl_single_omap_wkup
},
2035 { .compatible
= "ti,omap5-padconf", .data
= &pinctrl_single_omap_wkup
},
2036 { .compatible
= "pinctrl-single", .data
= &pinctrl_single
},
2037 { .compatible
= "pinconf-single", .data
= &pinconf_single
},
2040 MODULE_DEVICE_TABLE(of
, pcs_of_match
);
2042 static struct platform_driver pcs_driver
= {
2044 .remove
= pcs_remove
,
2046 .owner
= THIS_MODULE
,
2047 .name
= DRIVER_NAME
,
2048 .of_match_table
= pcs_of_match
,
2051 .suspend
= pinctrl_single_suspend
,
2052 .resume
= pinctrl_single_resume
,
2056 module_platform_driver(pcs_driver
);
2058 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
2059 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
2060 MODULE_LICENSE("GPL v2");