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x86, cpufeature: If we disable CLFLUSH, we should disable CLFLUSHOPT
[linux/fpc-iii.git] / drivers / scsi / mpt2sas / mpi / mpi2_ioc.h
blobd159c5f24aab8fffe8f4406e4930ae19d7943aff
1 /*
2 * Copyright (c) 2000-2013 LSI Corporation.
3 *
4 *
5 * Name: mpi2_ioc.h
6 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
7 * Creation Date: October 11, 2006
8 *
9 * mpi2_ioc.h Version: 02.00.22
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
18 * MaxTargets.
19 * Added TotalImageSize field to FWDownload Request.
20 * Added reserved words to FWUpload Request.
21 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
22 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
23 * request and replaced it with
24 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
25 * Replaced the MinReplyQueueDepth field of the IOCFacts
26 * reply with MaxReplyDescriptorPostQueueDepth.
27 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
28 * depth for the Reply Descriptor Post Queue.
29 * Added SASAddress field to Initiator Device Table
30 * Overflow Event data.
31 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
32 * for SAS Initiator Device Status Change Event data.
33 * Modified Reason Code defines for SAS Topology Change
34 * List Event data, including adding a bit for PHY Vacant
35 * status, and adding a mask for the Reason Code.
36 * Added define for
37 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
38 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
39 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
40 * the IOCFacts Reply.
41 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
42 * Moved MPI2_VERSION_UNION to mpi2.h.
43 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
44 * instead of enables, and added SASBroadcastPrimitiveMasks
45 * field.
46 * Added Log Entry Added Event and related structure.
47 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
48 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
49 * Added MaxVolumes and MaxPersistentEntries fields to
50 * IOCFacts reply.
51 * Added ProtocalFlags and IOCCapabilities fields to
52 * MPI2_FW_IMAGE_HEADER.
53 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
54 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
55 * a U16 (from a U32).
56 * Removed extra 's' from EventMasks name.
57 * 06-27-08 02.00.08 Fixed an offset in a comment.
58 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
59 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
60 * renamed MinReplyFrameSize to ReplyFrameSize.
61 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
62 * Added two new RAIDOperation values for Integrated RAID
63 * Operations Status Event data.
64 * Added four new IR Configuration Change List Event data
65 * ReasonCode values.
66 * Added two new ReasonCode defines for SAS Device Status
67 * Change Event data.
68 * Added three new DiscoveryStatus bits for the SAS
69 * Discovery event data.
70 * Added Multiplexing Status Change bit to the PhyStatus
71 * field of the SAS Topology Change List event data.
72 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
73 * BootFlags are now product-specific.
74 * Added defines for the indivdual signature bytes
75 * for MPI2_INIT_IMAGE_FOOTER.
76 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
77 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
78 * define.
79 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
80 * define.
81 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
82 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
83 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
84 * Added two new reason codes for SAS Device Status Change
85 * Event.
86 * Added new event: SAS PHY Counter.
87 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
88 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
89 * Added new product id family for 2208.
90 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
91 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
92 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
93 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
94 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
95 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
96 * Added Host Based Discovery Phy Event data.
97 * Added defines for ProductID Product field
98 * (MPI2_FW_HEADER_PID_).
99 * Modified values for SAS ProductID Family
100 * (MPI2_FW_HEADER_PID_FAMILY_).
101 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
102 * Added PowerManagementControl Request structures and
103 * defines.
104 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
105 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
106 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
107 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added
108 * SASNotifyPrimitiveMasks field to
109 * MPI2_EVENT_NOTIFICATION_REQUEST.
110 * Added Temperature Threshold Event.
111 * Added Host Message Event.
112 * Added Send Host Message request and reply.
113 * 05-25-11 02.00.18 For Extended Image Header, added
114 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
115 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
116 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
117 * 08-24-11 02.00.19 Added PhysicalPort field to
118 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
119 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
120 * 03-29-12 02.00.21 Added a product specific range to event values.
121 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
122 * Added ElapsedSeconds field to
123 * MPI2_EVENT_DATA_IR_OPERATION_STATUS.
124 * --------------------------------------------------------------------------
125 */
126
127 #ifndef MPI2_IOC_H
128 #define MPI2_IOC_H
129
130 /*****************************************************************************
131 *
132 * IOC Messages
133 *
134 *****************************************************************************/
135
136 /****************************************************************************
137 * IOCInit message
138 ****************************************************************************/
139
140 /* IOCInit Request message */
141 typedef struct _MPI2_IOC_INIT_REQUEST
142 {
143 U8 WhoInit; /* 0x00 */
144 U8 Reserved1; /* 0x01 */
145 U8 ChainOffset; /* 0x02 */
146 U8 Function; /* 0x03 */
147 U16 Reserved2; /* 0x04 */
148 U8 Reserved3; /* 0x06 */
149 U8 MsgFlags; /* 0x07 */
150 U8 VP_ID; /* 0x08 */
151 U8 VF_ID; /* 0x09 */
152 U16 Reserved4; /* 0x0A */
153 U16 MsgVersion; /* 0x0C */
154 U16 HeaderVersion; /* 0x0E */
155 U32 Reserved5; /* 0x10 */
156 U16 Reserved6; /* 0x14 */
157 U8 Reserved7; /* 0x16 */
158 U8 HostMSIxVectors; /* 0x17 */
159 U16 Reserved8; /* 0x18 */
160 U16 SystemRequestFrameSize; /* 0x1A */
161 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
162 U16 ReplyFreeQueueDepth; /* 0x1E */
163 U32 SenseBufferAddressHigh; /* 0x20 */
164 U32 SystemReplyAddressHigh; /* 0x24 */
165 U64 SystemRequestFrameBaseAddress; /* 0x28 */
166 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
167 U64 ReplyFreeQueueAddress; /* 0x38 */
168 U64 TimeStamp; /* 0x40 */
169 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
170 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
171
172 /* WhoInit values */
173 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
174 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
175 #define MPI2_WHOINIT_ROM_BIOS (0x02)
176 #define MPI2_WHOINIT_PCI_PEER (0x03)
177 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
178 #define MPI2_WHOINIT_MANUFACTURER (0x05)
179
180 /* MsgVersion */
181 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
182 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
183 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
184 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
185
186 /* HeaderVersion */
187 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
188 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
189 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
190 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
191
192 /* minimum depth for the Reply Descriptor Post Queue */
193 #define MPI2_RDPQ_DEPTH_MIN (16)
194
195
196 /* IOCInit Reply message */
197 typedef struct _MPI2_IOC_INIT_REPLY
198 {
199 U8 WhoInit; /* 0x00 */
200 U8 Reserved1; /* 0x01 */
201 U8 MsgLength; /* 0x02 */
202 U8 Function; /* 0x03 */
203 U16 Reserved2; /* 0x04 */
204 U8 Reserved3; /* 0x06 */
205 U8 MsgFlags; /* 0x07 */
206 U8 VP_ID; /* 0x08 */
207 U8 VF_ID; /* 0x09 */
208 U16 Reserved4; /* 0x0A */
209 U16 Reserved5; /* 0x0C */
210 U16 IOCStatus; /* 0x0E */
211 U32 IOCLogInfo; /* 0x10 */
212 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
213 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
214
215
216 /****************************************************************************
217 * IOCFacts message
218 ****************************************************************************/
219
220 /* IOCFacts Request message */
221 typedef struct _MPI2_IOC_FACTS_REQUEST
222 {
223 U16 Reserved1; /* 0x00 */
224 U8 ChainOffset; /* 0x02 */
225 U8 Function; /* 0x03 */
226 U16 Reserved2; /* 0x04 */
227 U8 Reserved3; /* 0x06 */
228 U8 MsgFlags; /* 0x07 */
229 U8 VP_ID; /* 0x08 */
230 U8 VF_ID; /* 0x09 */
231 U16 Reserved4; /* 0x0A */
232 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
233 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
234
235
236 /* IOCFacts Reply message */
237 typedef struct _MPI2_IOC_FACTS_REPLY
238 {
239 U16 MsgVersion; /* 0x00 */
240 U8 MsgLength; /* 0x02 */
241 U8 Function; /* 0x03 */
242 U16 HeaderVersion; /* 0x04 */
243 U8 IOCNumber; /* 0x06 */
244 U8 MsgFlags; /* 0x07 */
245 U8 VP_ID; /* 0x08 */
246 U8 VF_ID; /* 0x09 */
247 U16 Reserved1; /* 0x0A */
248 U16 IOCExceptions; /* 0x0C */
249 U16 IOCStatus; /* 0x0E */
250 U32 IOCLogInfo; /* 0x10 */
251 U8 MaxChainDepth; /* 0x14 */
252 U8 WhoInit; /* 0x15 */
253 U8 NumberOfPorts; /* 0x16 */
254 U8 MaxMSIxVectors; /* 0x17 */
255 U16 RequestCredit; /* 0x18 */
256 U16 ProductID; /* 0x1A */
257 U32 IOCCapabilities; /* 0x1C */
258 MPI2_VERSION_UNION FWVersion; /* 0x20 */
259 U16 IOCRequestFrameSize; /* 0x24 */
260 U16 Reserved3; /* 0x26 */
261 U16 MaxInitiators; /* 0x28 */
262 U16 MaxTargets; /* 0x2A */
263 U16 MaxSasExpanders; /* 0x2C */
264 U16 MaxEnclosures; /* 0x2E */
265 U16 ProtocolFlags; /* 0x30 */
266 U16 HighPriorityCredit; /* 0x32 */
267 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
268 U8 ReplyFrameSize; /* 0x36 */
269 U8 MaxVolumes; /* 0x37 */
270 U16 MaxDevHandle; /* 0x38 */
271 U16 MaxPersistentEntries; /* 0x3A */
272 U16 MinDevHandle; /* 0x3C */
273 U16 Reserved4; /* 0x3E */
274 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
275 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
276
277 /* MsgVersion */
278 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
279 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
280 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
281 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
282
283 /* HeaderVersion */
284 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
285 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
286 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
287 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
288
289 /* IOCExceptions */
290 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200)
291 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
292
293 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
294 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
295 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
296 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
297 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
298
299 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
300 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
301 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
302 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
303 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
304
305 /* defines for WhoInit field are after the IOCInit Request */
306
307 /* ProductID field uses MPI2_FW_HEADER_PID_ */
308
309 /* IOCCapabilities */
310 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
311 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
312 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
313 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
314 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
315 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
316 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
317 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
318 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
319 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
320 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
321 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
322 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
323
324 /* ProtocolFlags */
325 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
326 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
327
328
329 /****************************************************************************
330 * PortFacts message
331 ****************************************************************************/
332
333 /* PortFacts Request message */
334 typedef struct _MPI2_PORT_FACTS_REQUEST
335 {
336 U16 Reserved1; /* 0x00 */
337 U8 ChainOffset; /* 0x02 */
338 U8 Function; /* 0x03 */
339 U16 Reserved2; /* 0x04 */
340 U8 PortNumber; /* 0x06 */
341 U8 MsgFlags; /* 0x07 */
342 U8 VP_ID; /* 0x08 */
343 U8 VF_ID; /* 0x09 */
344 U16 Reserved3; /* 0x0A */
345 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
346 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
347
348 /* PortFacts Reply message */
349 typedef struct _MPI2_PORT_FACTS_REPLY
350 {
351 U16 Reserved1; /* 0x00 */
352 U8 MsgLength; /* 0x02 */
353 U8 Function; /* 0x03 */
354 U16 Reserved2; /* 0x04 */
355 U8 PortNumber; /* 0x06 */
356 U8 MsgFlags; /* 0x07 */
357 U8 VP_ID; /* 0x08 */
358 U8 VF_ID; /* 0x09 */
359 U16 Reserved3; /* 0x0A */
360 U16 Reserved4; /* 0x0C */
361 U16 IOCStatus; /* 0x0E */
362 U32 IOCLogInfo; /* 0x10 */
363 U8 Reserved5; /* 0x14 */
364 U8 PortType; /* 0x15 */
365 U16 Reserved6; /* 0x16 */
366 U16 MaxPostedCmdBuffers; /* 0x18 */
367 U16 Reserved7; /* 0x1A */
368 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
369 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
370
371 /* PortType values */
372 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
373 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
374 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
375 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
376 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
377
378
379 /****************************************************************************
380 * PortEnable message
381 ****************************************************************************/
382
383 /* PortEnable Request message */
384 typedef struct _MPI2_PORT_ENABLE_REQUEST
385 {
386 U16 Reserved1; /* 0x00 */
387 U8 ChainOffset; /* 0x02 */
388 U8 Function; /* 0x03 */
389 U8 Reserved2; /* 0x04 */
390 U8 PortFlags; /* 0x05 */
391 U8 Reserved3; /* 0x06 */
392 U8 MsgFlags; /* 0x07 */
393 U8 VP_ID; /* 0x08 */
394 U8 VF_ID; /* 0x09 */
395 U16 Reserved4; /* 0x0A */
396 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
397 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
398
399
400 /* PortEnable Reply message */
401 typedef struct _MPI2_PORT_ENABLE_REPLY
402 {
403 U16 Reserved1; /* 0x00 */
404 U8 MsgLength; /* 0x02 */
405 U8 Function; /* 0x03 */
406 U8 Reserved2; /* 0x04 */
407 U8 PortFlags; /* 0x05 */
408 U8 Reserved3; /* 0x06 */
409 U8 MsgFlags; /* 0x07 */
410 U8 VP_ID; /* 0x08 */
411 U8 VF_ID; /* 0x09 */
412 U16 Reserved4; /* 0x0A */
413 U16 Reserved5; /* 0x0C */
414 U16 IOCStatus; /* 0x0E */
415 U32 IOCLogInfo; /* 0x10 */
416 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
417 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
418
419
420 /****************************************************************************
421 * EventNotification message
422 ****************************************************************************/
423
424 /* EventNotification Request message */
425 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
426
427 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
428 {
429 U16 Reserved1; /* 0x00 */
430 U8 ChainOffset; /* 0x02 */
431 U8 Function; /* 0x03 */
432 U16 Reserved2; /* 0x04 */
433 U8 Reserved3; /* 0x06 */
434 U8 MsgFlags; /* 0x07 */
435 U8 VP_ID; /* 0x08 */
436 U8 VF_ID; /* 0x09 */
437 U16 Reserved4; /* 0x0A */
438 U32 Reserved5; /* 0x0C */
439 U32 Reserved6; /* 0x10 */
440 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
441 U16 SASBroadcastPrimitiveMasks; /* 0x24 */
442 U16 SASNotifyPrimitiveMasks; /* 0x26 */
443 U32 Reserved8; /* 0x28 */
444 } MPI2_EVENT_NOTIFICATION_REQUEST,
445 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
446 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
447
448
449 /* EventNotification Reply message */
450 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
451 {
452 U16 EventDataLength; /* 0x00 */
453 U8 MsgLength; /* 0x02 */
454 U8 Function; /* 0x03 */
455 U16 Reserved1; /* 0x04 */
456 U8 AckRequired; /* 0x06 */
457 U8 MsgFlags; /* 0x07 */
458 U8 VP_ID; /* 0x08 */
459 U8 VF_ID; /* 0x09 */
460 U16 Reserved2; /* 0x0A */
461 U16 Reserved3; /* 0x0C */
462 U16 IOCStatus; /* 0x0E */
463 U32 IOCLogInfo; /* 0x10 */
464 U16 Event; /* 0x14 */
465 U16 Reserved4; /* 0x16 */
466 U32 EventContext; /* 0x18 */
467 U32 EventData[1]; /* 0x1C */
468 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
469 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
470
471 /* AckRequired */
472 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
473 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
474
475 /* Event */
476 #define MPI2_EVENT_LOG_DATA (0x0001)
477 #define MPI2_EVENT_STATE_CHANGE (0x0002)
478 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
479 #define MPI2_EVENT_EVENT_CHANGE (0x000A)
480 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */
481 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
482 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
483 #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
484 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
485 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
486 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
487 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
488 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
489 #define MPI2_EVENT_IR_VOLUME (0x001E)
490 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
491 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
492 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
493 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
494 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
495 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
496 #define MPI2_EVENT_SAS_QUIESCE (0x0025)
497 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)
498 #define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
499 #define MPI2_EVENT_HOST_MESSAGE (0x0028)
500 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)
501 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)
502
503 /* Log Entry Added Event data */
504
505 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
506 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
507
508 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
509 {
510 U64 TimeStamp; /* 0x00 */
511 U32 Reserved1; /* 0x08 */
512 U16 LogSequence; /* 0x0C */
513 U16 LogEntryQualifier; /* 0x0E */
514 U8 VP_ID; /* 0x10 */
515 U8 VF_ID; /* 0x11 */
516 U16 Reserved2; /* 0x12 */
517 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
518 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
519 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
520 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
521
522 /* GPIO Interrupt Event data */
523
524 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
525 U8 GPIONum; /* 0x00 */
526 U8 Reserved1; /* 0x01 */
527 U16 Reserved2; /* 0x02 */
528 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
529 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
530 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
531
532 /* Temperature Threshold Event data */
533
534 typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
535 U16 Status; /* 0x00 */
536 U8 SensorNum; /* 0x02 */
537 U8 Reserved1; /* 0x03 */
538 U16 CurrentTemperature; /* 0x04 */
539 U16 Reserved2; /* 0x06 */
540 U32 Reserved3; /* 0x08 */
541 U32 Reserved4; /* 0x0C */
542 } MPI2_EVENT_DATA_TEMPERATURE,
543 MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE,
544 Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t;
545
546 /* Temperature Threshold Event data Status bits */
547 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008)
548 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004)
549 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002)
550 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001)
551
552
553 /* Host Message Event data */
554
555 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
556 U8 SourceVF_ID; /* 0x00 */
557 U8 Reserved1; /* 0x01 */
558 U16 Reserved2; /* 0x02 */
559 U32 Reserved3; /* 0x04 */
560 U32 HostData[1]; /* 0x08 */
561 } MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
562 Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t;
563
564
565 /* Hard Reset Received Event data */
566
567 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
568 {
569 U8 Reserved1; /* 0x00 */
570 U8 Port; /* 0x01 */
571 U16 Reserved2; /* 0x02 */
572 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
573 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
574 Mpi2EventDataHardResetReceived_t,
575 MPI2_POINTER pMpi2EventDataHardResetReceived_t;
576
577 /* Task Set Full Event data */
578 /* this event is obsolete */
579
580 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
581 {
582 U16 DevHandle; /* 0x00 */
583 U16 CurrentDepth; /* 0x02 */
584 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
585 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
586
587
588 /* SAS Device Status Change Event data */
589
590 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
591 {
592 U16 TaskTag; /* 0x00 */
593 U8 ReasonCode; /* 0x02 */
594 U8 PhysicalPort; /* 0x03 */
595 U8 ASC; /* 0x04 */
596 U8 ASCQ; /* 0x05 */
597 U16 DevHandle; /* 0x06 */
598 U32 Reserved2; /* 0x08 */
599 U64 SASAddress; /* 0x0C */
600 U8 LUN[8]; /* 0x14 */
601 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
602 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
603 Mpi2EventDataSasDeviceStatusChange_t,
604 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
605
606 /* SAS Device Status Change Event data ReasonCode values */
607 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
608 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
609 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
610 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
611 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
612 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
613 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
614 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
615 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
616 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
617 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
618 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
619 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
620
621
622 /* Integrated RAID Operation Status Event data */
623
624 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
625 {
626 U16 VolDevHandle; /* 0x00 */
627 U16 Reserved1; /* 0x02 */
628 U8 RAIDOperation; /* 0x04 */
629 U8 PercentComplete; /* 0x05 */
630 U16 Reserved2; /* 0x06 */
631 U32 ElapsedSeconds; /* 0x08 */
632 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
633 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
634 Mpi2EventDataIrOperationStatus_t,
635 MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
636
637 /* Integrated RAID Operation Status Event data RAIDOperation values */
638 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
639 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
640 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
641 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
642 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
643
644
645 /* Integrated RAID Volume Event data */
646
647 typedef struct _MPI2_EVENT_DATA_IR_VOLUME
648 {
649 U16 VolDevHandle; /* 0x00 */
650 U8 ReasonCode; /* 0x02 */
651 U8 Reserved1; /* 0x03 */
652 U32 NewValue; /* 0x04 */
653 U32 PreviousValue; /* 0x08 */
654 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
655 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
656
657 /* Integrated RAID Volume Event data ReasonCode values */
658 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
659 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
660 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
661
662
663 /* Integrated RAID Physical Disk Event data */
664
665 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
666 {
667 U16 Reserved1; /* 0x00 */
668 U8 ReasonCode; /* 0x02 */
669 U8 PhysDiskNum; /* 0x03 */
670 U16 PhysDiskDevHandle; /* 0x04 */
671 U16 Reserved2; /* 0x06 */
672 U16 Slot; /* 0x08 */
673 U16 EnclosureHandle; /* 0x0A */
674 U32 NewValue; /* 0x0C */
675 U32 PreviousValue; /* 0x10 */
676 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
677 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
678 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
679
680 /* Integrated RAID Physical Disk Event data ReasonCode values */
681 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
682 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
683 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
684
685
686 /* Integrated RAID Configuration Change List Event data */
687
688 /*
689 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
690 * one and check NumElements at runtime.
691 */
692 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
693 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
694 #endif
695
696 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
697 {
698 U16 ElementFlags; /* 0x00 */
699 U16 VolDevHandle; /* 0x02 */
700 U8 ReasonCode; /* 0x04 */
701 U8 PhysDiskNum; /* 0x05 */
702 U16 PhysDiskDevHandle; /* 0x06 */
703 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
704 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
705
706 /* IR Configuration Change List Event data ElementFlags values */
707 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
708 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
709 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
710 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
711
712 /* IR Configuration Change List Event data ReasonCode values */
713 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
714 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
715 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
716 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
717 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
718 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
719 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
720 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
721 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
722
723 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
724 {
725 U8 NumElements; /* 0x00 */
726 U8 Reserved1; /* 0x01 */
727 U8 Reserved2; /* 0x02 */
728 U8 ConfigNum; /* 0x03 */
729 U32 Flags; /* 0x04 */
730 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */
731 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
732 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
733 Mpi2EventDataIrConfigChangeList_t,
734 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
735
736 /* IR Configuration Change List Event data Flags values */
737 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
738
739
740 /* SAS Discovery Event data */
741
742 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
743 {
744 U8 Flags; /* 0x00 */
745 U8 ReasonCode; /* 0x01 */
746 U8 PhysicalPort; /* 0x02 */
747 U8 Reserved1; /* 0x03 */
748 U32 DiscoveryStatus; /* 0x04 */
749 } MPI2_EVENT_DATA_SAS_DISCOVERY,
750 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
751 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
752
753 /* SAS Discovery Event data Flags values */
754 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
755 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
756
757 /* SAS Discovery Event data ReasonCode values */
758 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
759 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
760
761 /* SAS Discovery Event data DiscoveryStatus values */
762 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
763 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
764 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
765 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
766 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
767 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
768 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
769 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
770 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
771 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
772 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
773 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
774 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
775 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
776 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
777 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
778 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
779 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
780 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
781 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
782
783
784 /* SAS Broadcast Primitive Event data */
785
786 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
787 {
788 U8 PhyNum; /* 0x00 */
789 U8 Port; /* 0x01 */
790 U8 PortWidth; /* 0x02 */
791 U8 Primitive; /* 0x03 */
792 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
793 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
794 Mpi2EventDataSasBroadcastPrimitive_t,
795 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
796
797 /* defines for the Primitive field */
798 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
799 #define MPI2_EVENT_PRIMITIVE_SES (0x02)
800 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
801 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
802 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
803 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
804 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
805 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
806
807 /* SAS Notify Primitive Event data */
808
809 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
810 U8 PhyNum; /* 0x00 */
811 U8 Port; /* 0x01 */
812 U8 Reserved1; /* 0x02 */
813 U8 Primitive; /* 0x03 */
814 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
815 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
816 Mpi2EventDataSasNotifyPrimitive_t,
817 MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t;
818
819 /* defines for the Primitive field */
820 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01)
821 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02)
822 #define MPI2_EVENT_NOTIFY_RESERVED1 (0x03)
823 #define MPI2_EVENT_NOTIFY_RESERVED2 (0x04)
824
825
826 /* SAS Initiator Device Status Change Event data */
827
828 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
829 {
830 U8 ReasonCode; /* 0x00 */
831 U8 PhysicalPort; /* 0x01 */
832 U16 DevHandle; /* 0x02 */
833 U64 SASAddress; /* 0x04 */
834 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
835 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
836 Mpi2EventDataSasInitDevStatusChange_t,
837 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
838
839 /* SAS Initiator Device Status Change event ReasonCode values */
840 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
841 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
842
843
844 /* SAS Initiator Device Table Overflow Event data */
845
846 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
847 {
848 U16 MaxInit; /* 0x00 */
849 U16 CurrentInit; /* 0x02 */
850 U64 SASAddress; /* 0x04 */
851 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
852 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
853 Mpi2EventDataSasInitTableOverflow_t,
854 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
855
856
857 /* SAS Topology Change List Event data */
858
859 /*
860 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
861 * one and check NumEntries at runtime.
862 */
863 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
864 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
865 #endif
866
867 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
868 {
869 U16 AttachedDevHandle; /* 0x00 */
870 U8 LinkRate; /* 0x02 */
871 U8 PhyStatus; /* 0x03 */
872 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
873 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
874
875 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
876 {
877 U16 EnclosureHandle; /* 0x00 */
878 U16 ExpanderDevHandle; /* 0x02 */
879 U8 NumPhys; /* 0x04 */
880 U8 Reserved1; /* 0x05 */
881 U16 Reserved2; /* 0x06 */
882 U8 NumEntries; /* 0x08 */
883 U8 StartPhyNum; /* 0x09 */
884 U8 ExpStatus; /* 0x0A */
885 U8 PhysicalPort; /* 0x0B */
886 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
887 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
888 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
889 Mpi2EventDataSasTopologyChangeList_t,
890 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
891
892 /* values for the ExpStatus field */
893 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
894 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
895 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
896 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
897 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
898
899 /* defines for the LinkRate field */
900 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
901 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
902 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
903 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
904
905 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
906 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
907 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
908 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
909 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
910 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
911 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
912 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
913 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
914 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
915
916 /* values for the PhyStatus field */
917 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
918 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
919 /* values for the PhyStatus ReasonCode sub-field */
920 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
921 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
922 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
923 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
924 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
925 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
926
927
928 /* SAS Enclosure Device Status Change Event data */
929
930 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
931 {
932 U16 EnclosureHandle; /* 0x00 */
933 U8 ReasonCode; /* 0x02 */
934 U8 PhysicalPort; /* 0x03 */
935 U64 EnclosureLogicalID; /* 0x04 */
936 U16 NumSlots; /* 0x0C */
937 U16 StartSlot; /* 0x0E */
938 U32 PhyBits; /* 0x10 */
939 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
940 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
941 Mpi2EventDataSasEnclDevStatusChange_t,
942 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
943
944 /* SAS Enclosure Device Status Change event ReasonCode values */
945 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
946 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
947
948
949 /* SAS PHY Counter Event data */
950
951 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
952 U64 TimeStamp; /* 0x00 */
953 U32 Reserved1; /* 0x08 */
954 U8 PhyEventCode; /* 0x0C */
955 U8 PhyNum; /* 0x0D */
956 U16 Reserved2; /* 0x0E */
957 U32 PhyEventInfo; /* 0x10 */
958 U8 CounterType; /* 0x14 */
959 U8 ThresholdWindow; /* 0x15 */
960 U8 TimeUnits; /* 0x16 */
961 U8 Reserved3; /* 0x17 */
962 U32 EventThreshold; /* 0x18 */
963 U16 ThresholdFlags; /* 0x1C */
964 U16 Reserved4; /* 0x1E */
965 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
966 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
967 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
968
969 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the
970 * PhyEventCode field
971 * use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the
972 * CounterType field
973 * use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the
974 * TimeUnits field
975 * use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the
976 * ThresholdFlags field
977 * */
978
979
980 /* SAS Quiesce Event data */
981
982 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
983 U8 ReasonCode; /* 0x00 */
984 U8 Reserved1; /* 0x01 */
985 U16 Reserved2; /* 0x02 */
986 U32 Reserved3; /* 0x04 */
987 } MPI2_EVENT_DATA_SAS_QUIESCE,
988 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
989 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
990
991 /* SAS Quiesce Event data ReasonCode values */
992 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
993 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
994
995
996 /* Host Based Discovery Phy Event data */
997
998 typedef struct _MPI2_EVENT_HBD_PHY_SAS {
999 U8 Flags; /* 0x00 */
1000 U8 NegotiatedLinkRate; /* 0x01 */
1001 U8 PhyNum; /* 0x02 */
1002 U8 PhysicalPort; /* 0x03 */
1003 U32 Reserved1; /* 0x04 */
1004 U8 InitialFrame[28]; /* 0x08 */
1005 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
1006 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
1007
1008 /* values for the Flags field */
1009 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
1010 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
1011
1012 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for
1013 * the NegotiatedLinkRate field */
1014
1015 typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1016 MPI2_EVENT_HBD_PHY_SAS Sas;
1017 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1018 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
1019
1020 typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1021 U8 DescriptorType; /* 0x00 */
1022 U8 Reserved1; /* 0x01 */
1023 U16 Reserved2; /* 0x02 */
1024 U32 Reserved3; /* 0x04 */
1025 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */
1026 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
1027 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
1028
1029 /* values for the DescriptorType field */
1030 #define MPI2_EVENT_HBD_DT_SAS (0x01)
1031
1032
1033
1034 /****************************************************************************
1035 * EventAck message
1036 ****************************************************************************/
1037
1038 /* EventAck Request message */
1039 typedef struct _MPI2_EVENT_ACK_REQUEST
1040 {
1041 U16 Reserved1; /* 0x00 */
1042 U8 ChainOffset; /* 0x02 */
1043 U8 Function; /* 0x03 */
1044 U16 Reserved2; /* 0x04 */
1045 U8 Reserved3; /* 0x06 */
1046 U8 MsgFlags; /* 0x07 */
1047 U8 VP_ID; /* 0x08 */
1048 U8 VF_ID; /* 0x09 */
1049 U16 Reserved4; /* 0x0A */
1050 U16 Event; /* 0x0C */
1051 U16 Reserved5; /* 0x0E */
1052 U32 EventContext; /* 0x10 */
1053 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
1054 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
1055
1056
1057 /* EventAck Reply message */
1058 typedef struct _MPI2_EVENT_ACK_REPLY
1059 {
1060 U16 Reserved1; /* 0x00 */
1061 U8 MsgLength; /* 0x02 */
1062 U8 Function; /* 0x03 */
1063 U16 Reserved2; /* 0x04 */
1064 U8 Reserved3; /* 0x06 */
1065 U8 MsgFlags; /* 0x07 */
1066 U8 VP_ID; /* 0x08 */
1067 U8 VF_ID; /* 0x09 */
1068 U16 Reserved4; /* 0x0A */
1069 U16 Reserved5; /* 0x0C */
1070 U16 IOCStatus; /* 0x0E */
1071 U32 IOCLogInfo; /* 0x10 */
1072 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
1073 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
1074
1075
1076 /****************************************************************************
1077 * SendHostMessage message
1078 ****************************************************************************/
1079
1080 /* SendHostMessage Request message */
1081 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1082 U16 HostDataLength; /* 0x00 */
1083 U8 ChainOffset; /* 0x02 */
1084 U8 Function; /* 0x03 */
1085 U16 Reserved1; /* 0x04 */
1086 U8 Reserved2; /* 0x06 */
1087 U8 MsgFlags; /* 0x07 */
1088 U8 VP_ID; /* 0x08 */
1089 U8 VF_ID; /* 0x09 */
1090 U16 Reserved3; /* 0x0A */
1091 U8 Reserved4; /* 0x0C */
1092 U8 DestVF_ID; /* 0x0D */
1093 U16 Reserved5; /* 0x0E */
1094 U32 Reserved6; /* 0x10 */
1095 U32 Reserved7; /* 0x14 */
1096 U32 Reserved8; /* 0x18 */
1097 U32 Reserved9; /* 0x1C */
1098 U32 Reserved10; /* 0x20 */
1099 U32 HostData[1]; /* 0x24 */
1100 } MPI2_SEND_HOST_MESSAGE_REQUEST,
1101 MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1102 Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t;
1103
1104
1105 /* SendHostMessage Reply message */
1106 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1107 U16 HostDataLength; /* 0x00 */
1108 U8 MsgLength; /* 0x02 */
1109 U8 Function; /* 0x03 */
1110 U16 Reserved1; /* 0x04 */
1111 U8 Reserved2; /* 0x06 */
1112 U8 MsgFlags; /* 0x07 */
1113 U8 VP_ID; /* 0x08 */
1114 U8 VF_ID; /* 0x09 */
1115 U16 Reserved3; /* 0x0A */
1116 U16 Reserved4; /* 0x0C */
1117 U16 IOCStatus; /* 0x0E */
1118 U32 IOCLogInfo; /* 0x10 */
1119 } MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1120 Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t;
1121
1122
1123 /****************************************************************************
1124 * FWDownload message
1125 ****************************************************************************/
1126
1127 /* FWDownload Request message */
1128 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
1129 {
1130 U8 ImageType; /* 0x00 */
1131 U8 Reserved1; /* 0x01 */
1132 U8 ChainOffset; /* 0x02 */
1133 U8 Function; /* 0x03 */
1134 U16 Reserved2; /* 0x04 */
1135 U8 Reserved3; /* 0x06 */
1136 U8 MsgFlags; /* 0x07 */
1137 U8 VP_ID; /* 0x08 */
1138 U8 VF_ID; /* 0x09 */
1139 U16 Reserved4; /* 0x0A */
1140 U32 TotalImageSize; /* 0x0C */
1141 U32 Reserved5; /* 0x10 */
1142 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1143 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
1144 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
1145
1146 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1147
1148 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1149 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1150 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1151 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1152 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1153 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1154 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1155 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1156 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1157
1158 /* FWDownload TransactionContext Element */
1159 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1160 {
1161 U8 Reserved1; /* 0x00 */
1162 U8 ContextSize; /* 0x01 */
1163 U8 DetailsLength; /* 0x02 */
1164 U8 Flags; /* 0x03 */
1165 U32 Reserved2; /* 0x04 */
1166 U32 ImageOffset; /* 0x08 */
1167 U32 ImageSize; /* 0x0C */
1168 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1169 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1170
1171 /* FWDownload Reply message */
1172 typedef struct _MPI2_FW_DOWNLOAD_REPLY
1173 {
1174 U8 ImageType; /* 0x00 */
1175 U8 Reserved1; /* 0x01 */
1176 U8 MsgLength; /* 0x02 */
1177 U8 Function; /* 0x03 */
1178 U16 Reserved2; /* 0x04 */
1179 U8 Reserved3; /* 0x06 */
1180 U8 MsgFlags; /* 0x07 */
1181 U8 VP_ID; /* 0x08 */
1182 U8 VF_ID; /* 0x09 */
1183 U16 Reserved4; /* 0x0A */
1184 U16 Reserved5; /* 0x0C */
1185 U16 IOCStatus; /* 0x0E */
1186 U32 IOCLogInfo; /* 0x10 */
1187 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1188 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1189
1190
1191 /****************************************************************************
1192 * FWUpload message
1193 ****************************************************************************/
1194
1195 /* FWUpload Request message */
1196 typedef struct _MPI2_FW_UPLOAD_REQUEST
1197 {
1198 U8 ImageType; /* 0x00 */
1199 U8 Reserved1; /* 0x01 */
1200 U8 ChainOffset; /* 0x02 */
1201 U8 Function; /* 0x03 */
1202 U16 Reserved2; /* 0x04 */
1203 U8 Reserved3; /* 0x06 */
1204 U8 MsgFlags; /* 0x07 */
1205 U8 VP_ID; /* 0x08 */
1206 U8 VF_ID; /* 0x09 */
1207 U16 Reserved4; /* 0x0A */
1208 U32 Reserved5; /* 0x0C */
1209 U32 Reserved6; /* 0x10 */
1210 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1211 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1212 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1213
1214 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1215 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1216 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1217 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1218 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1219 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1220 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1221 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1222 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1223 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1224
1225 typedef struct _MPI2_FW_UPLOAD_TCSGE
1226 {
1227 U8 Reserved1; /* 0x00 */
1228 U8 ContextSize; /* 0x01 */
1229 U8 DetailsLength; /* 0x02 */
1230 U8 Flags; /* 0x03 */
1231 U32 Reserved2; /* 0x04 */
1232 U32 ImageOffset; /* 0x08 */
1233 U32 ImageSize; /* 0x0C */
1234 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1235 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1236
1237 /* FWUpload Reply message */
1238 typedef struct _MPI2_FW_UPLOAD_REPLY
1239 {
1240 U8 ImageType; /* 0x00 */
1241 U8 Reserved1; /* 0x01 */
1242 U8 MsgLength; /* 0x02 */
1243 U8 Function; /* 0x03 */
1244 U16 Reserved2; /* 0x04 */
1245 U8 Reserved3; /* 0x06 */
1246 U8 MsgFlags; /* 0x07 */
1247 U8 VP_ID; /* 0x08 */
1248 U8 VF_ID; /* 0x09 */
1249 U16 Reserved4; /* 0x0A */
1250 U16 Reserved5; /* 0x0C */
1251 U16 IOCStatus; /* 0x0E */
1252 U32 IOCLogInfo; /* 0x10 */
1253 U32 ActualImageSize; /* 0x14 */
1254 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1255 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1256
1257
1258 /* FW Image Header */
1259 typedef struct _MPI2_FW_IMAGE_HEADER
1260 {
1261 U32 Signature; /* 0x00 */
1262 U32 Signature0; /* 0x04 */
1263 U32 Signature1; /* 0x08 */
1264 U32 Signature2; /* 0x0C */
1265 MPI2_VERSION_UNION MPIVersion; /* 0x10 */
1266 MPI2_VERSION_UNION FWVersion; /* 0x14 */
1267 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */
1268 MPI2_VERSION_UNION PackageVersion; /* 0x1C */
1269 U16 VendorID; /* 0x20 */
1270 U16 ProductID; /* 0x22 */
1271 U16 ProtocolFlags; /* 0x24 */
1272 U16 Reserved26; /* 0x26 */
1273 U32 IOCCapabilities; /* 0x28 */
1274 U32 ImageSize; /* 0x2C */
1275 U32 NextImageHeaderOffset; /* 0x30 */
1276 U32 Checksum; /* 0x34 */
1277 U32 Reserved38; /* 0x38 */
1278 U32 Reserved3C; /* 0x3C */
1279 U32 Reserved40; /* 0x40 */
1280 U32 Reserved44; /* 0x44 */
1281 U32 Reserved48; /* 0x48 */
1282 U32 Reserved4C; /* 0x4C */
1283 U32 Reserved50; /* 0x50 */
1284 U32 Reserved54; /* 0x54 */
1285 U32 Reserved58; /* 0x58 */
1286 U32 Reserved5C; /* 0x5C */
1287 U32 Reserved60; /* 0x60 */
1288 U32 FirmwareVersionNameWhat; /* 0x64 */
1289 U8 FirmwareVersionName[32]; /* 0x68 */
1290 U32 VendorNameWhat; /* 0x88 */
1291 U8 VendorName[32]; /* 0x8C */
1292 U32 PackageNameWhat; /* 0x88 */
1293 U8 PackageName[32]; /* 0x8C */
1294 U32 ReservedD0; /* 0xD0 */
1295 U32 ReservedD4; /* 0xD4 */
1296 U32 ReservedD8; /* 0xD8 */
1297 U32 ReservedDC; /* 0xDC */
1298 U32 ReservedE0; /* 0xE0 */
1299 U32 ReservedE4; /* 0xE4 */
1300 U32 ReservedE8; /* 0xE8 */
1301 U32 ReservedEC; /* 0xEC */
1302 U32 ReservedF0; /* 0xF0 */
1303 U32 ReservedF4; /* 0xF4 */
1304 U32 ReservedF8; /* 0xF8 */
1305 U32 ReservedFC; /* 0xFC */
1306 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1307 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1308
1309 /* Signature field */
1310 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1311 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1312 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1313
1314 /* Signature0 field */
1315 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1316 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1317
1318 /* Signature1 field */
1319 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1320 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1321
1322 /* Signature2 field */
1323 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1324 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1325
1326
1327 /* defines for using the ProductID field */
1328 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1329 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1330
1331 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1332 #define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1333 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1334 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1335
1336
1337 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1338 /* SAS */
1339 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1340 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1341
1342 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1343
1344 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1345
1346
1347 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1348 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1349 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1350
1351 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1352
1353 #define MPI2_FW_HEADER_SIZE (0x100)
1354
1355
1356 /* Extended Image Header */
1357 typedef struct _MPI2_EXT_IMAGE_HEADER
1358
1359 {
1360 U8 ImageType; /* 0x00 */
1361 U8 Reserved1; /* 0x01 */
1362 U16 Reserved2; /* 0x02 */
1363 U32 Checksum; /* 0x04 */
1364 U32 ImageSize; /* 0x08 */
1365 U32 NextImageHeaderOffset; /* 0x0C */
1366 U32 PackageVersion; /* 0x10 */
1367 U32 Reserved3; /* 0x14 */
1368 U32 Reserved4; /* 0x18 */
1369 U32 Reserved5; /* 0x1C */
1370 U8 IdentifyString[32]; /* 0x20 */
1371 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
1372 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
1373
1374 /* useful offsets */
1375 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1376 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1377 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1378
1379 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1380
1381 /* defines for the ImageType field */
1382 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1383 #define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1384 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1385 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1386 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1387 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1388 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1389 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1390 #define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80)
1391 #define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF)
1392 #define MPI2_EXT_IMAGE_TYPE_MAX \
1393 (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC) /* deprecated */
1394
1395
1396
1397 /* FLASH Layout Extended Image Data */
1398
1399 /*
1400 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1401 * one and check RegionsPerLayout at runtime.
1402 */
1403 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1404 #define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1405 #endif
1406
1407 /*
1408 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1409 * one and check NumberOfLayouts at runtime.
1410 */
1411 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1412 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1413 #endif
1414
1415 typedef struct _MPI2_FLASH_REGION
1416 {
1417 U8 RegionType; /* 0x00 */
1418 U8 Reserved1; /* 0x01 */
1419 U16 Reserved2; /* 0x02 */
1420 U32 RegionOffset; /* 0x04 */
1421 U32 RegionSize; /* 0x08 */
1422 U32 Reserved3; /* 0x0C */
1423 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
1424 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
1425
1426 typedef struct _MPI2_FLASH_LAYOUT
1427 {
1428 U32 FlashSize; /* 0x00 */
1429 U32 Reserved1; /* 0x04 */
1430 U32 Reserved2; /* 0x08 */
1431 U32 Reserved3; /* 0x0C */
1432 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1433 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
1434 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
1435
1436 typedef struct _MPI2_FLASH_LAYOUT_DATA
1437 {
1438 U8 ImageRevision; /* 0x00 */
1439 U8 Reserved1; /* 0x01 */
1440 U8 SizeOfRegion; /* 0x02 */
1441 U8 Reserved2; /* 0x03 */
1442 U16 NumberOfLayouts; /* 0x04 */
1443 U16 RegionsPerLayout; /* 0x06 */
1444 U16 MinimumSectorAlignment; /* 0x08 */
1445 U16 Reserved3; /* 0x0A */
1446 U32 Reserved4; /* 0x0C */
1447 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1448 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
1449 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
1450
1451 /* defines for the RegionType field */
1452 #define MPI2_FLASH_REGION_UNUSED (0x00)
1453 #define MPI2_FLASH_REGION_FIRMWARE (0x01)
1454 #define MPI2_FLASH_REGION_BIOS (0x02)
1455 #define MPI2_FLASH_REGION_NVDATA (0x03)
1456 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1457 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1458 #define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1459 #define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1460 #define MPI2_FLASH_REGION_MEGARAID (0x09)
1461 #define MPI2_FLASH_REGION_INIT (0x0A)
1462
1463 /* ImageRevision */
1464 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1465
1466
1467
1468 /* Supported Devices Extended Image Data */
1469
1470 /*
1471 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1472 * one and check NumberOfDevices at runtime.
1473 */
1474 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1475 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1476 #endif
1477
1478 typedef struct _MPI2_SUPPORTED_DEVICE
1479 {
1480 U16 DeviceID; /* 0x00 */
1481 U16 VendorID; /* 0x02 */
1482 U16 DeviceIDMask; /* 0x04 */
1483 U16 Reserved1; /* 0x06 */
1484 U8 LowPCIRev; /* 0x08 */
1485 U8 HighPCIRev; /* 0x09 */
1486 U16 Reserved2; /* 0x0A */
1487 U32 Reserved3; /* 0x0C */
1488 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
1489 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
1490
1491 typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1492 {
1493 U8 ImageRevision; /* 0x00 */
1494 U8 Reserved1; /* 0x01 */
1495 U8 NumberOfDevices; /* 0x02 */
1496 U8 Reserved2; /* 0x03 */
1497 U32 Reserved3; /* 0x04 */
1498 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1499 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
1500 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
1501
1502 /* ImageRevision */
1503 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1504
1505
1506 /* Init Extended Image Data */
1507
1508 typedef struct _MPI2_INIT_IMAGE_FOOTER
1509
1510 {
1511 U32 BootFlags; /* 0x00 */
1512 U32 ImageSize; /* 0x04 */
1513 U32 Signature0; /* 0x08 */
1514 U32 Signature1; /* 0x0C */
1515 U32 Signature2; /* 0x10 */
1516 U32 ResetVector; /* 0x14 */
1517 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
1518 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
1519
1520 /* defines for the BootFlags field */
1521 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1522
1523 /* defines for the ImageSize field */
1524 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1525
1526 /* defines for the Signature0 field */
1527 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1528 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1529
1530 /* defines for the Signature1 field */
1531 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1532 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1533
1534 /* defines for the Signature2 field */
1535 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1536 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1537
1538 /* Signature fields as individual bytes */
1539 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1540 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1541 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1542 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1543
1544 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1545 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1546 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1547 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1548
1549 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1550 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1551 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1552 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1553
1554 /* defines for the ResetVector field */
1555 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1556
1557
1558 /****************************************************************************
1559 * PowerManagementControl message
1560 ****************************************************************************/
1561
1562 /* PowerManagementControl Request message */
1563 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1564 U8 Feature; /* 0x00 */
1565 U8 Reserved1; /* 0x01 */
1566 U8 ChainOffset; /* 0x02 */
1567 U8 Function; /* 0x03 */
1568 U16 Reserved2; /* 0x04 */
1569 U8 Reserved3; /* 0x06 */
1570 U8 MsgFlags; /* 0x07 */
1571 U8 VP_ID; /* 0x08 */
1572 U8 VF_ID; /* 0x09 */
1573 U16 Reserved4; /* 0x0A */
1574 U8 Parameter1; /* 0x0C */
1575 U8 Parameter2; /* 0x0D */
1576 U8 Parameter3; /* 0x0E */
1577 U8 Parameter4; /* 0x0F */
1578 U32 Reserved5; /* 0x10 */
1579 U32 Reserved6; /* 0x14 */
1580 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1581 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
1582
1583 /* defines for the Feature field */
1584 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1585 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1586 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /* obsolete */
1587 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1588 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1589 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1590
1591 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1592 /* Parameter1 contains a PHY number */
1593 /* Parameter2 indicates power condition action using these defines */
1594 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1595 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1596 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1597 /* Parameter3 and Parameter4 are reserved */
1598
1599 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1600 * Feature */
1601 /* Parameter1 contains SAS port width modulation group number */
1602 /* Parameter2 indicates IOC action using these defines */
1603 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1604 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1605 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1606 /* Parameter3 indicates desired modulation level using these defines */
1607 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1608 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1609 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
1610 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
1611 /* Parameter4 is reserved */
1612
1613 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1614 /* Parameter1 indicates desired PCIe link speed using these defines */
1615 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /* obsolete */
1616 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /* obsolete */
1617 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /* obsolete */
1618 /* Parameter2 indicates desired PCIe link width using these defines */
1619 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /* obsolete */
1620 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /* obsolete */
1621 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /* obsolete */
1622 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /* obsolete */
1623 /* Parameter3 and Parameter4 are reserved */
1624
1625 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1626 /* Parameter1 indicates desired IOC hardware clock speed using these defines */
1627 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
1628 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
1629 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
1630 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
1631 /* Parameter2, Parameter3, and Parameter4 are reserved */
1632
1633
1634 /* PowerManagementControl Reply message */
1635 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1636 U8 Feature; /* 0x00 */
1637 U8 Reserved1; /* 0x01 */
1638 U8 MsgLength; /* 0x02 */
1639 U8 Function; /* 0x03 */
1640 U16 Reserved2; /* 0x04 */
1641 U8 Reserved3; /* 0x06 */
1642 U8 MsgFlags; /* 0x07 */
1643 U8 VP_ID; /* 0x08 */
1644 U8 VF_ID; /* 0x09 */
1645 U16 Reserved4; /* 0x0A */
1646 U16 Reserved5; /* 0x0C */
1647 U16 IOCStatus; /* 0x0E */
1648 U32 IOCLogInfo; /* 0x10 */
1649 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1650 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
1651
1652
1653 #endif
1654
Linux with added FPC-III support