drivers/scsi/qla2xxx/qla_nx2.h

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7
   8 #ifndef __QLA_NX2_H
   9 #define __QLA_NX2_H
  10
  11 #define QSNT_ACK_TOV                            30
  12 #define INTENT_TO_RECOVER                       0x01
  13 #define PROCEED_TO_RECOVER                      0x02
  14 #define IDC_LOCK_RECOVERY_OWNER_MASK            0x3C
  15 #define IDC_LOCK_RECOVERY_STATE_MASK            0x3
  16 #define IDC_LOCK_RECOVERY_STATE_SHIFT_BITS      2
  17
  18 #define QLA8044_DRV_LOCK_MSLEEP         200
  19 #define QLA8044_ADDR_DDR_NET            (0x0000000000000000ULL)
  20 #define QLA8044_ADDR_DDR_NET_MAX        (0x000000000fffffffULL)
  21
  22 #define MD_MIU_TEST_AGT_WRDATA_LO               0x410000A0
  23 #define MD_MIU_TEST_AGT_WRDATA_HI               0x410000A4
  24 #define MD_MIU_TEST_AGT_WRDATA_ULO              0x410000B0
  25 #define MD_MIU_TEST_AGT_WRDATA_UHI              0x410000B4
  26 #define MD_MIU_TEST_AGT_RDDATA_LO               0x410000A8
  27 #define MD_MIU_TEST_AGT_RDDATA_HI               0x410000AC
  28 #define MD_MIU_TEST_AGT_RDDATA_ULO              0x410000B8
  29 #define MD_MIU_TEST_AGT_RDDATA_UHI              0x410000BC
  30
  31 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
  32 #define MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE)
  33 #define MIU_TA_CTL_WRITE_START  (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE | \
  34                                  MIU_TA_CTL_START)
  35 #define MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE)
  36
  37 /* Imbus address bit used to indicate a host address. This bit is
  38  * eliminated by the pcie bar and bar select before presentation
  39  * over pcie. */
  40 /* host memory via IMBUS */
  41 #define QLA8044_P2_ADDR_PCIE    (0x0000000800000000ULL)
  42 #define QLA8044_P3_ADDR_PCIE    (0x0000008000000000ULL)
  43 #define QLA8044_ADDR_PCIE_MAX   (0x0000000FFFFFFFFFULL)
  44 #define QLA8044_ADDR_OCM0       (0x0000000200000000ULL)
  45 #define QLA8044_ADDR_OCM0_MAX   (0x00000002000fffffULL)
  46 #define QLA8044_ADDR_OCM1       (0x0000000200400000ULL)
  47 #define QLA8044_ADDR_OCM1_MAX   (0x00000002004fffffULL)
  48 #define QLA8044_ADDR_QDR_NET    (0x0000000300000000ULL)
  49 #define QLA8044_P2_ADDR_QDR_NET_MAX     (0x00000003001fffffULL)
  50 #define QLA8044_P3_ADDR_QDR_NET_MAX     (0x0000000303ffffffULL)
  51 #define QLA8044_ADDR_QDR_NET_MAX        (0x0000000307ffffffULL)
  52 #define QLA8044_PCI_CRBSPACE            ((unsigned long)0x06000000)
  53 #define QLA8044_PCI_DIRECT_CRB          ((unsigned long)0x04400000)
  54 #define QLA8044_PCI_CAMQM               ((unsigned long)0x04800000)
  55 #define QLA8044_PCI_CAMQM_MAX           ((unsigned long)0x04ffffff)
  56 #define QLA8044_PCI_DDR_NET             ((unsigned long)0x00000000)
  57 #define QLA8044_PCI_QDR_NET             ((unsigned long)0x04000000)
  58 #define QLA8044_PCI_QDR_NET_MAX         ((unsigned long)0x043fffff)
  59
  60 /*  PCI Windowing for DDR regions.  */
  61 #define QLA8044_ADDR_IN_RANGE(addr, low, high)          \
  62         (((addr) <= (high)) && ((addr) >= (low)))
  63
  64 /* Indirectly Mapped Registers */
  65 #define QLA8044_FLASH_SPI_STATUS        0x2808E010
  66 #define QLA8044_FLASH_SPI_CONTROL       0x2808E014
  67 #define QLA8044_FLASH_STATUS            0x42100004
  68 #define QLA8044_FLASH_CONTROL           0x42110004
  69 #define QLA8044_FLASH_ADDR              0x42110008
  70 #define QLA8044_FLASH_WRDATA            0x4211000C
  71 #define QLA8044_FLASH_RDDATA            0x42110018
  72 #define QLA8044_FLASH_DIRECT_WINDOW     0x42110030
  73 #define QLA8044_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
  74
  75 /* Flash access regs */
  76 #define QLA8044_FLASH_LOCK              0x3850
  77 #define QLA8044_FLASH_UNLOCK            0x3854
  78 #define QLA8044_FLASH_LOCK_ID           0x3500
  79
  80 /* Driver Lock regs */
  81 #define QLA8044_DRV_LOCK                0x3868
  82 #define QLA8044_DRV_UNLOCK              0x386C
  83 #define QLA8044_DRV_LOCK_ID             0x3504
  84 #define QLA8044_DRV_LOCKRECOVERY        0x379C
  85
  86 /* IDC version */
  87 #define QLA8044_IDC_VER_MAJ_VALUE       0x1
  88 #define QLA8044_IDC_VER_MIN_VALUE       0x0
  89
  90 /* IDC Registers : Driver Coexistence Defines */
  91 #define QLA8044_CRB_IDC_VER_MAJOR       0x3780
  92 #define QLA8044_CRB_IDC_VER_MINOR       0x3798
  93 #define QLA8044_IDC_DRV_AUDIT           0x3794
  94 #define QLA8044_SRE_SHIM_CONTROL        0x0D200284
  95 #define QLA8044_PORT0_RXB_PAUSE_THRS    0x0B2003A4
  96 #define QLA8044_PORT1_RXB_PAUSE_THRS    0x0B2013A4
  97 #define QLA8044_PORT0_RXB_TC_MAX_CELL   0x0B200388
  98 #define QLA8044_PORT1_RXB_TC_MAX_CELL   0x0B201388
  99 #define QLA8044_PORT0_RXB_TC_STATS      0x0B20039C
 100 #define QLA8044_PORT1_RXB_TC_STATS      0x0B20139C
 101 #define QLA8044_PORT2_IFB_PAUSE_THRS    0x0B200704
 102 #define QLA8044_PORT3_IFB_PAUSE_THRS    0x0B201704
 103
 104 /* set value to pause threshold value */
 105 #define QLA8044_SET_PAUSE_VAL           0x0
 106 #define QLA8044_SET_TC_MAX_CELL_VAL     0x03FF03FF
 107 #define QLA8044_PEG_HALT_STATUS1        0x34A8
 108 #define QLA8044_PEG_HALT_STATUS2        0x34AC
 109 #define QLA8044_PEG_ALIVE_COUNTER       0x34B0 /* FW_HEARTBEAT */
 110 #define QLA8044_FW_CAPABILITIES         0x3528
 111 #define QLA8044_CRB_DRV_ACTIVE          0x3788 /* IDC_DRV_PRESENCE */
 112 #define QLA8044_CRB_DEV_STATE           0x3784 /* IDC_DEV_STATE */
 113 #define QLA8044_CRB_DRV_STATE           0x378C /* IDC_DRV_ACK */
 114 #define QLA8044_CRB_DRV_SCRATCH         0x3548
 115 #define QLA8044_CRB_DEV_PART_INFO1      0x37E0
 116 #define QLA8044_CRB_DEV_PART_INFO2      0x37E4
 117 #define QLA8044_FW_VER_MAJOR            0x3550
 118 #define QLA8044_FW_VER_MINOR            0x3554
 119 #define QLA8044_FW_VER_SUB              0x3558
 120 #define QLA8044_NPAR_STATE              0x359C
 121 #define QLA8044_FW_IMAGE_VALID          0x35FC
 122 #define QLA8044_CMDPEG_STATE            0x3650
 123 #define QLA8044_ASIC_TEMP               0x37B4
 124 #define QLA8044_FW_API                  0x356C
 125 #define QLA8044_DRV_OP_MODE             0x3570
 126 #define QLA8044_CRB_WIN_BASE            0x3800
 127 #define QLA8044_CRB_WIN_FUNC(f)         (QLA8044_CRB_WIN_BASE+((f)*4))
 128 #define QLA8044_SEM_LOCK_BASE           0x3840
 129 #define QLA8044_SEM_UNLOCK_BASE         0x3844
 130 #define QLA8044_SEM_LOCK_FUNC(f)        (QLA8044_SEM_LOCK_BASE+((f)*8))
 131 #define QLA8044_SEM_UNLOCK_FUNC(f)      (QLA8044_SEM_UNLOCK_BASE+((f)*8))
 132 #define QLA8044_LINK_STATE(f)           (0x3698+((f) > 7 ? 4 : 0))
 133 #define QLA8044_LINK_SPEED(f)           (0x36E0+(((f) >> 2) * 4))
 134 #define QLA8044_MAX_LINK_SPEED(f)       (0x36F0+(((f) / 4) * 4))
 135 #define QLA8044_LINK_SPEED_FACTOR       10
 136
 137 /* FLASH API Defines */
 138 #define QLA8044_FLASH_MAX_WAIT_USEC     100
 139 #define QLA8044_FLASH_LOCK_TIMEOUT      10000
 140 #define QLA8044_FLASH_SECTOR_SIZE       65536
 141 #define QLA8044_DRV_LOCK_TIMEOUT        2000
 142 #define QLA8044_FLASH_SECTOR_ERASE_CMD  0xdeadbeef
 143 #define QLA8044_FLASH_WRITE_CMD         0xdacdacda
 144 #define QLA8044_FLASH_BUFFER_WRITE_CMD  0xcadcadca
 145 #define QLA8044_FLASH_READ_RETRY_COUNT  2000
 146 #define QLA8044_FLASH_STATUS_READY      0x6
 147 #define QLA8044_FLASH_BUFFER_WRITE_MIN  2
 148 #define QLA8044_FLASH_BUFFER_WRITE_MAX  64
 149 #define QLA8044_FLASH_STATUS_REG_POLL_DELAY 1
 150 #define QLA8044_ERASE_MODE              1
 151 #define QLA8044_WRITE_MODE              2
 152 #define QLA8044_DWORD_WRITE_MODE        3
 153 #define QLA8044_GLOBAL_RESET            0x38CC
 154 #define QLA8044_WILDCARD                0x38F0
 155 #define QLA8044_INFORMANT               0x38FC
 156 #define QLA8044_HOST_MBX_CTRL           0x3038
 157 #define QLA8044_FW_MBX_CTRL             0x303C
 158 #define QLA8044_BOOTLOADER_ADDR         0x355C
 159 #define QLA8044_BOOTLOADER_SIZE         0x3560
 160 #define QLA8044_FW_IMAGE_ADDR           0x3564
 161 #define QLA8044_MBX_INTR_ENABLE         0x1000
 162 #define QLA8044_MBX_INTR_MASK           0x1200
 163
 164 /* IDC Control Register bit defines */
 165 #define DONTRESET_BIT0          0x1
 166 #define GRACEFUL_RESET_BIT1     0x2
 167
 168 /* ISP8044 PEG_HALT_STATUS1 bits */
 169 #define QLA8044_HALT_STATUS_INFORMATIONAL (0x1 << 29)
 170 #define QLA8044_HALT_STATUS_FW_RESET      (0x2 << 29)
 171 #define QLA8044_HALT_STATUS_UNRECOVERABLE (0x4 << 29)
 172
 173 /* Firmware image definitions */
 174 #define QLA8044_BOOTLOADER_FLASH_ADDR   0x10000
 175 #define QLA8044_BOOT_FROM_FLASH         0
 176 #define QLA8044_IDC_PARAM_ADDR          0x3e8020
 177
 178 /* FLASH related definitions */
 179 #define QLA8044_OPTROM_BURST_SIZE               0x100
 180 #define QLA8044_MAX_OPTROM_BURST_DWORDS         (QLA8044_OPTROM_BURST_SIZE / 4)
 181 #define QLA8044_MIN_OPTROM_BURST_DWORDS         2
 182 #define QLA8044_SECTOR_SIZE                     (64 * 1024)
 183
 184 #define QLA8044_FLASH_SPI_CTL                   0x4
 185 #define QLA8044_FLASH_FIRST_TEMP_VAL            0x00800000
 186 #define QLA8044_FLASH_SECOND_TEMP_VAL           0x00800001
 187 #define QLA8044_FLASH_FIRST_MS_PATTERN          0x43
 188 #define QLA8044_FLASH_SECOND_MS_PATTERN         0x7F
 189 #define QLA8044_FLASH_LAST_MS_PATTERN           0x7D
 190 #define QLA8044_FLASH_STATUS_WRITE_DEF_SIG      0xFD0100
 191 #define QLA8044_FLASH_SECOND_ERASE_MS_VAL       0x5
 192 #define QLA8044_FLASH_ERASE_SIG                 0xFD0300
 193 #define QLA8044_FLASH_LAST_ERASE_MS_VAL         0x3D
 194
 195 /* Reset template definitions */
 196 #define QLA8044_MAX_RESET_SEQ_ENTRIES   16
 197 #define QLA8044_RESTART_TEMPLATE_SIZE   0x2000
 198 #define QLA8044_RESET_TEMPLATE_ADDR     0x4F0000
 199 #define QLA8044_RESET_SEQ_VERSION       0x0101
 200
 201 /* Reset template entry opcodes */
 202 #define OPCODE_NOP                      0x0000
 203 #define OPCODE_WRITE_LIST               0x0001
 204 #define OPCODE_READ_WRITE_LIST          0x0002
 205 #define OPCODE_POLL_LIST                0x0004
 206 #define OPCODE_POLL_WRITE_LIST          0x0008
 207 #define OPCODE_READ_MODIFY_WRITE        0x0010
 208 #define OPCODE_SEQ_PAUSE                0x0020
 209 #define OPCODE_SEQ_END                  0x0040
 210 #define OPCODE_TMPL_END                 0x0080
 211 #define OPCODE_POLL_READ_LIST           0x0100
 212
 213 /* Template Header */
 214 #define RESET_TMPLT_HDR_SIGNATURE       0xCAFE
 215 #define QLA8044_IDC_DRV_CTRL            0x3790
 216 #define AF_8044_NO_FW_DUMP              27 /* 0x08000000 */
 217
 218 #define MINIDUMP_SIZE_36K               36864
 219
 220 struct qla8044_reset_template_hdr {
 221         uint16_t        version;
 222         uint16_t        signature;
 223         uint16_t        size;
 224         uint16_t        entries;
 225         uint16_t        hdr_size;
 226         uint16_t        checksum;
 227         uint16_t        init_seq_offset;
 228         uint16_t        start_seq_offset;
 229 } __packed;
 230
 231 /* Common Entry Header. */
 232 struct qla8044_reset_entry_hdr {
 233         uint16_t cmd;
 234         uint16_t size;
 235         uint16_t count;
 236         uint16_t delay;
 237 } __packed;
 238
 239 /* Generic poll entry type. */
 240 struct qla8044_poll {
 241         uint32_t  test_mask;
 242         uint32_t  test_value;
 243 } __packed;
 244
 245 /* Read modify write entry type. */
 246 struct qla8044_rmw {
 247         uint32_t test_mask;
 248         uint32_t xor_value;
 249         uint32_t  or_value;
 250         uint8_t shl;
 251         uint8_t shr;
 252         uint8_t index_a;
 253         uint8_t rsvd;
 254 } __packed;
 255
 256 /* Generic Entry Item with 2 DWords. */
 257 struct qla8044_entry {
 258         uint32_t arg1;
 259         uint32_t arg2;
 260 } __packed;
 261
 262 /* Generic Entry Item with 4 DWords.*/
 263 struct qla8044_quad_entry {
 264         uint32_t dr_addr;
 265         uint32_t dr_value;
 266         uint32_t ar_addr;
 267         uint32_t ar_value;
 268 } __packed;
 269
 270 struct qla8044_reset_template {
 271         int seq_index;
 272         int seq_error;
 273         int array_index;
 274         uint32_t array[QLA8044_MAX_RESET_SEQ_ENTRIES];
 275         uint8_t *buff;
 276         uint8_t *stop_offset;
 277         uint8_t *start_offset;
 278         uint8_t *init_offset;
 279         struct qla8044_reset_template_hdr *hdr;
 280         uint8_t seq_end;
 281         uint8_t template_end;
 282 };
 283
 284 /* Driver_code is for driver to write some info about the entry
 285  * currently not used.
 286  */
 287 struct qla8044_minidump_entry_hdr {
 288         uint32_t entry_type;
 289         uint32_t entry_size;
 290         uint32_t entry_capture_size;
 291         struct {
 292                 uint8_t entry_capture_mask;
 293                 uint8_t entry_code;
 294                 uint8_t driver_code;
 295                 uint8_t driver_flags;
 296         } d_ctrl;
 297 } __packed;
 298
 299 /*  Read CRB entry header */
 300 struct qla8044_minidump_entry_crb {
 301         struct qla8044_minidump_entry_hdr h;
 302         uint32_t addr;
 303         struct {
 304                 uint8_t addr_stride;
 305                 uint8_t state_index_a;
 306                 uint16_t poll_timeout;
 307         } crb_strd;
 308         uint32_t data_size;
 309         uint32_t op_count;
 310
 311         struct {
 312                 uint8_t opcode;
 313                 uint8_t state_index_v;
 314                 uint8_t shl;
 315                 uint8_t shr;
 316         } crb_ctrl;
 317
 318         uint32_t value_1;
 319         uint32_t value_2;
 320         uint32_t value_3;
 321 } __packed;
 322
 323 struct qla8044_minidump_entry_cache {
 324         struct qla8044_minidump_entry_hdr h;
 325         uint32_t tag_reg_addr;
 326         struct {
 327                 uint16_t tag_value_stride;
 328                 uint16_t init_tag_value;
 329         } addr_ctrl;
 330         uint32_t data_size;
 331         uint32_t op_count;
 332         uint32_t control_addr;
 333         struct {
 334                 uint16_t write_value;
 335                 uint8_t poll_mask;
 336                 uint8_t poll_wait;
 337         } cache_ctrl;
 338         uint32_t read_addr;
 339         struct {
 340                 uint8_t read_addr_stride;
 341                 uint8_t read_addr_cnt;
 342                 uint16_t rsvd_1;
 343         } read_ctrl;
 344 } __packed;
 345
 346 /* Read OCM */
 347 struct qla8044_minidump_entry_rdocm {
 348         struct qla8044_minidump_entry_hdr h;
 349         uint32_t rsvd_0;
 350         uint32_t rsvd_1;
 351         uint32_t data_size;
 352         uint32_t op_count;
 353         uint32_t rsvd_2;
 354         uint32_t rsvd_3;
 355         uint32_t read_addr;
 356         uint32_t read_addr_stride;
 357 } __packed;
 358
 359 /* Read Memory */
 360 struct qla8044_minidump_entry_rdmem {
 361         struct qla8044_minidump_entry_hdr h;
 362         uint32_t rsvd[6];
 363         uint32_t read_addr;
 364         uint32_t read_data_size;
 365 };
 366
 367 /* Read Memory: For Pex-DMA */
 368 struct qla8044_minidump_entry_rdmem_pex_dma {
 369         struct qla8044_minidump_entry_hdr h;
 370         uint32_t desc_card_addr;
 371         uint16_t dma_desc_cmd;
 372         uint8_t rsvd[2];
 373         uint32_t start_dma_cmd;
 374         uint8_t rsvd2[12];
 375         uint32_t read_addr;
 376         uint32_t read_data_size;
 377 } __packed;
 378
 379 /* Read ROM */
 380 struct qla8044_minidump_entry_rdrom {
 381         struct qla8044_minidump_entry_hdr h;
 382         uint32_t rsvd[6];
 383         uint32_t read_addr;
 384         uint32_t read_data_size;
 385 } __packed;
 386
 387 /* Mux entry */
 388 struct qla8044_minidump_entry_mux {
 389         struct qla8044_minidump_entry_hdr h;
 390         uint32_t select_addr;
 391         uint32_t rsvd_0;
 392         uint32_t data_size;
 393         uint32_t op_count;
 394         uint32_t select_value;
 395         uint32_t select_value_stride;
 396         uint32_t read_addr;
 397         uint32_t rsvd_1;
 398 } __packed;
 399
 400 /* Queue entry */
 401 struct qla8044_minidump_entry_queue {
 402         struct qla8044_minidump_entry_hdr h;
 403         uint32_t select_addr;
 404         struct {
 405                 uint16_t queue_id_stride;
 406                 uint16_t rsvd_0;
 407         } q_strd;
 408         uint32_t data_size;
 409         uint32_t op_count;
 410         uint32_t rsvd_1;
 411         uint32_t rsvd_2;
 412         uint32_t read_addr;
 413         struct {
 414                 uint8_t read_addr_stride;
 415                 uint8_t read_addr_cnt;
 416                 uint16_t rsvd_3;
 417         } rd_strd;
 418 } __packed;
 419
 420 /* POLLRD Entry */
 421 struct qla8044_minidump_entry_pollrd {
 422         struct qla8044_minidump_entry_hdr h;
 423         uint32_t select_addr;
 424         uint32_t read_addr;
 425         uint32_t select_value;
 426         uint16_t select_value_stride;
 427         uint16_t op_count;
 428         uint32_t poll_wait;
 429         uint32_t poll_mask;
 430         uint32_t data_size;
 431         uint32_t rsvd_1;
 432 } __packed;
 433
 434 /* RDMUX2 Entry */
 435 struct qla8044_minidump_entry_rdmux2 {
 436         struct qla8044_minidump_entry_hdr h;
 437         uint32_t select_addr_1;
 438         uint32_t select_addr_2;
 439         uint32_t select_value_1;
 440         uint32_t select_value_2;
 441         uint32_t op_count;
 442         uint32_t select_value_mask;
 443         uint32_t read_addr;
 444         uint8_t select_value_stride;
 445         uint8_t data_size;
 446         uint8_t rsvd[2];
 447 } __packed;
 448
 449 /* POLLRDMWR Entry */
 450 struct qla8044_minidump_entry_pollrdmwr {
 451         struct qla8044_minidump_entry_hdr h;
 452         uint32_t addr_1;
 453         uint32_t addr_2;
 454         uint32_t value_1;
 455         uint32_t value_2;
 456         uint32_t poll_wait;
 457         uint32_t poll_mask;
 458         uint32_t modify_mask;
 459         uint32_t data_size;
 460 } __packed;
 461
 462 /* IDC additional information */
 463 struct qla8044_idc_information {
 464         uint32_t request_desc;  /* IDC request descriptor */
 465         uint32_t info1; /* IDC additional info */
 466         uint32_t info2; /* IDC additional info */
 467         uint32_t info3; /* IDC additional info */
 468 } __packed;
 469
 470 enum qla_regs {
 471         QLA8044_PEG_HALT_STATUS1_INDEX = 0,
 472         QLA8044_PEG_HALT_STATUS2_INDEX,
 473         QLA8044_PEG_ALIVE_COUNTER_INDEX,
 474         QLA8044_CRB_DRV_ACTIVE_INDEX,
 475         QLA8044_CRB_DEV_STATE_INDEX,
 476         QLA8044_CRB_DRV_STATE_INDEX,
 477         QLA8044_CRB_DRV_SCRATCH_INDEX,
 478         QLA8044_CRB_DEV_PART_INFO_INDEX,
 479         QLA8044_CRB_DRV_IDC_VERSION_INDEX,
 480         QLA8044_FW_VERSION_MAJOR_INDEX,
 481         QLA8044_FW_VERSION_MINOR_INDEX,
 482         QLA8044_FW_VERSION_SUB_INDEX,
 483         QLA8044_CRB_CMDPEG_STATE_INDEX,
 484         QLA8044_CRB_TEMP_STATE_INDEX,
 485 } __packed;
 486
 487 #define CRB_REG_INDEX_MAX       14
 488 #define CRB_CMDPEG_CHECK_RETRY_COUNT    60
 489 #define CRB_CMDPEG_CHECK_DELAY          500
 490
 491 static const uint32_t qla8044_reg_tbl[] = {
 492         QLA8044_PEG_HALT_STATUS1,
 493         QLA8044_PEG_HALT_STATUS2,
 494         QLA8044_PEG_ALIVE_COUNTER,
 495         QLA8044_CRB_DRV_ACTIVE,
 496         QLA8044_CRB_DEV_STATE,
 497         QLA8044_CRB_DRV_STATE,
 498         QLA8044_CRB_DRV_SCRATCH,
 499         QLA8044_CRB_DEV_PART_INFO1,
 500         QLA8044_CRB_IDC_VER_MAJOR,
 501         QLA8044_FW_VER_MAJOR,
 502         QLA8044_FW_VER_MINOR,
 503         QLA8044_FW_VER_SUB,
 504         QLA8044_CMDPEG_STATE,
 505         QLA8044_ASIC_TEMP,
 506 };
 507
 508 /* MiniDump Structures */
 509
 510 /* Driver_code is for driver to write some info about the entry
 511  * currently not used.
 512  */
 513 #define QLA8044_SS_OCM_WNDREG_INDEX             3
 514 #define QLA8044_DBG_STATE_ARRAY_LEN             16
 515 #define QLA8044_DBG_CAP_SIZE_ARRAY_LEN          8
 516 #define QLA8044_DBG_RSVD_ARRAY_LEN              8
 517 #define QLA8044_DBG_OCM_WNDREG_ARRAY_LEN        16
 518 #define QLA8044_SS_PCI_INDEX                    0
 519
 520 struct qla8044_minidump_template_hdr {
 521         uint32_t entry_type;
 522         uint32_t first_entry_offset;
 523         uint32_t size_of_template;
 524         uint32_t capture_debug_level;
 525         uint32_t num_of_entries;
 526         uint32_t version;
 527         uint32_t driver_timestamp;
 528         uint32_t checksum;
 529
 530         uint32_t driver_capture_mask;
 531         uint32_t driver_info_word2;
 532         uint32_t driver_info_word3;
 533         uint32_t driver_info_word4;
 534
 535         uint32_t saved_state_array[QLA8044_DBG_STATE_ARRAY_LEN];
 536         uint32_t capture_size_array[QLA8044_DBG_CAP_SIZE_ARRAY_LEN];
 537         uint32_t ocm_window_reg[QLA8044_DBG_OCM_WNDREG_ARRAY_LEN];
 538 };
 539
 540 struct qla8044_pex_dma_descriptor {
 541         struct {
 542                 uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */
 543                 uint8_t rsvd[2];
 544                 uint16_t dma_desc_cmd;
 545         } cmd;
 546         uint64_t src_addr;
 547         uint64_t dma_bus_addr; /*0-3: desc-cmd, 4-7: pci-func, 8-15: desc-cmd*/
 548         uint8_t rsvd[24];
 549 } __packed;
 550
 551 #endif