2 * Support for the Tundra Universe I/II VME-PCI Bridge Chips
4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
10 * Derived from ca91c042.c by Michael Wyrick
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/module.h>
20 #include <linux/types.h>
21 #include <linux/errno.h>
22 #include <linux/pci.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/poll.h>
25 #include <linux/interrupt.h>
26 #include <linux/spinlock.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/time.h>
31 #include <linux/uaccess.h>
32 #include <linux/vme.h>
34 #include "../vme_bridge.h"
35 #include "vme_ca91cx42.h"
37 static int ca91cx42_probe(struct pci_dev
*, const struct pci_device_id
*);
38 static void ca91cx42_remove(struct pci_dev
*);
40 /* Module parameters */
43 static const char driver_name
[] = "vme_ca91cx42";
45 static const struct pci_device_id ca91cx42_ids
[] = {
46 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA
, PCI_DEVICE_ID_TUNDRA_CA91C142
) },
50 static struct pci_driver ca91cx42_driver
= {
52 .id_table
= ca91cx42_ids
,
53 .probe
= ca91cx42_probe
,
54 .remove
= ca91cx42_remove
,
57 static u32
ca91cx42_DMA_irqhandler(struct ca91cx42_driver
*bridge
)
59 wake_up(&bridge
->dma_queue
);
61 return CA91CX42_LINT_DMA
;
64 static u32
ca91cx42_LM_irqhandler(struct ca91cx42_driver
*bridge
, u32 stat
)
69 for (i
= 0; i
< 4; i
++) {
70 if (stat
& CA91CX42_LINT_LM
[i
]) {
71 /* We only enable interrupts if the callback is set */
72 bridge
->lm_callback
[i
](i
);
73 serviced
|= CA91CX42_LINT_LM
[i
];
80 /* XXX This needs to be split into 4 queues */
81 static u32
ca91cx42_MB_irqhandler(struct ca91cx42_driver
*bridge
, int mbox_mask
)
83 wake_up(&bridge
->mbox_queue
);
85 return CA91CX42_LINT_MBOX
;
88 static u32
ca91cx42_IACK_irqhandler(struct ca91cx42_driver
*bridge
)
90 wake_up(&bridge
->iack_queue
);
92 return CA91CX42_LINT_SW_IACK
;
95 static u32
ca91cx42_VERR_irqhandler(struct vme_bridge
*ca91cx42_bridge
)
98 struct ca91cx42_driver
*bridge
;
100 bridge
= ca91cx42_bridge
->driver_priv
;
102 val
= ioread32(bridge
->base
+ DGCS
);
104 if (!(val
& 0x00000800)) {
105 dev_err(ca91cx42_bridge
->parent
, "ca91cx42_VERR_irqhandler DMA "
106 "Read Error DGCS=%08X\n", val
);
109 return CA91CX42_LINT_VERR
;
112 static u32
ca91cx42_LERR_irqhandler(struct vme_bridge
*ca91cx42_bridge
)
115 struct ca91cx42_driver
*bridge
;
117 bridge
= ca91cx42_bridge
->driver_priv
;
119 val
= ioread32(bridge
->base
+ DGCS
);
121 if (!(val
& 0x00000800))
122 dev_err(ca91cx42_bridge
->parent
, "ca91cx42_LERR_irqhandler DMA "
123 "Read Error DGCS=%08X\n", val
);
125 return CA91CX42_LINT_LERR
;
129 static u32
ca91cx42_VIRQ_irqhandler(struct vme_bridge
*ca91cx42_bridge
,
132 int vec
, i
, serviced
= 0;
133 struct ca91cx42_driver
*bridge
;
135 bridge
= ca91cx42_bridge
->driver_priv
;
138 for (i
= 7; i
> 0; i
--) {
139 if (stat
& (1 << i
)) {
140 vec
= ioread32(bridge
->base
+
141 CA91CX42_V_STATID
[i
]) & 0xff;
143 vme_irq_handler(ca91cx42_bridge
, i
, vec
);
145 serviced
|= (1 << i
);
152 static irqreturn_t
ca91cx42_irqhandler(int irq
, void *ptr
)
154 u32 stat
, enable
, serviced
= 0;
155 struct vme_bridge
*ca91cx42_bridge
;
156 struct ca91cx42_driver
*bridge
;
158 ca91cx42_bridge
= ptr
;
160 bridge
= ca91cx42_bridge
->driver_priv
;
162 enable
= ioread32(bridge
->base
+ LINT_EN
);
163 stat
= ioread32(bridge
->base
+ LINT_STAT
);
165 /* Only look at unmasked interrupts */
171 if (stat
& CA91CX42_LINT_DMA
)
172 serviced
|= ca91cx42_DMA_irqhandler(bridge
);
173 if (stat
& (CA91CX42_LINT_LM0
| CA91CX42_LINT_LM1
| CA91CX42_LINT_LM2
|
175 serviced
|= ca91cx42_LM_irqhandler(bridge
, stat
);
176 if (stat
& CA91CX42_LINT_MBOX
)
177 serviced
|= ca91cx42_MB_irqhandler(bridge
, stat
);
178 if (stat
& CA91CX42_LINT_SW_IACK
)
179 serviced
|= ca91cx42_IACK_irqhandler(bridge
);
180 if (stat
& CA91CX42_LINT_VERR
)
181 serviced
|= ca91cx42_VERR_irqhandler(ca91cx42_bridge
);
182 if (stat
& CA91CX42_LINT_LERR
)
183 serviced
|= ca91cx42_LERR_irqhandler(ca91cx42_bridge
);
184 if (stat
& (CA91CX42_LINT_VIRQ1
| CA91CX42_LINT_VIRQ2
|
185 CA91CX42_LINT_VIRQ3
| CA91CX42_LINT_VIRQ4
|
186 CA91CX42_LINT_VIRQ5
| CA91CX42_LINT_VIRQ6
|
187 CA91CX42_LINT_VIRQ7
))
188 serviced
|= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge
, stat
);
190 /* Clear serviced interrupts */
191 iowrite32(serviced
, bridge
->base
+ LINT_STAT
);
196 static int ca91cx42_irq_init(struct vme_bridge
*ca91cx42_bridge
)
199 struct pci_dev
*pdev
;
200 struct ca91cx42_driver
*bridge
;
202 bridge
= ca91cx42_bridge
->driver_priv
;
205 pdev
= container_of(ca91cx42_bridge
->parent
, struct pci_dev
, dev
);
207 /* Initialise list for VME bus errors */
208 INIT_LIST_HEAD(&ca91cx42_bridge
->vme_errors
);
210 mutex_init(&ca91cx42_bridge
->irq_mtx
);
212 /* Disable interrupts from PCI to VME */
213 iowrite32(0, bridge
->base
+ VINT_EN
);
215 /* Disable PCI interrupts */
216 iowrite32(0, bridge
->base
+ LINT_EN
);
217 /* Clear Any Pending PCI Interrupts */
218 iowrite32(0x00FFFFFF, bridge
->base
+ LINT_STAT
);
220 result
= request_irq(pdev
->irq
, ca91cx42_irqhandler
, IRQF_SHARED
,
221 driver_name
, ca91cx42_bridge
);
223 dev_err(&pdev
->dev
, "Can't get assigned pci irq vector %02X\n",
228 /* Ensure all interrupts are mapped to PCI Interrupt 0 */
229 iowrite32(0, bridge
->base
+ LINT_MAP0
);
230 iowrite32(0, bridge
->base
+ LINT_MAP1
);
231 iowrite32(0, bridge
->base
+ LINT_MAP2
);
233 /* Enable DMA, mailbox & LM Interrupts */
234 tmp
= CA91CX42_LINT_MBOX3
| CA91CX42_LINT_MBOX2
| CA91CX42_LINT_MBOX1
|
235 CA91CX42_LINT_MBOX0
| CA91CX42_LINT_SW_IACK
|
236 CA91CX42_LINT_VERR
| CA91CX42_LINT_LERR
| CA91CX42_LINT_DMA
;
238 iowrite32(tmp
, bridge
->base
+ LINT_EN
);
243 static void ca91cx42_irq_exit(struct ca91cx42_driver
*bridge
,
244 struct pci_dev
*pdev
)
246 struct vme_bridge
*ca91cx42_bridge
;
248 /* Disable interrupts from PCI to VME */
249 iowrite32(0, bridge
->base
+ VINT_EN
);
251 /* Disable PCI interrupts */
252 iowrite32(0, bridge
->base
+ LINT_EN
);
253 /* Clear Any Pending PCI Interrupts */
254 iowrite32(0x00FFFFFF, bridge
->base
+ LINT_STAT
);
256 ca91cx42_bridge
= container_of((void *)bridge
, struct vme_bridge
,
258 free_irq(pdev
->irq
, ca91cx42_bridge
);
261 static int ca91cx42_iack_received(struct ca91cx42_driver
*bridge
, int level
)
265 tmp
= ioread32(bridge
->base
+ LINT_STAT
);
267 if (tmp
& (1 << level
))
274 * Set up an VME interrupt
276 static void ca91cx42_irq_set(struct vme_bridge
*ca91cx42_bridge
, int level
,
280 struct pci_dev
*pdev
;
282 struct ca91cx42_driver
*bridge
;
284 bridge
= ca91cx42_bridge
->driver_priv
;
286 /* Enable IRQ level */
287 tmp
= ioread32(bridge
->base
+ LINT_EN
);
290 tmp
&= ~CA91CX42_LINT_VIRQ
[level
];
292 tmp
|= CA91CX42_LINT_VIRQ
[level
];
294 iowrite32(tmp
, bridge
->base
+ LINT_EN
);
296 if ((state
== 0) && (sync
!= 0)) {
297 pdev
= container_of(ca91cx42_bridge
->parent
, struct pci_dev
,
300 synchronize_irq(pdev
->irq
);
304 static int ca91cx42_irq_generate(struct vme_bridge
*ca91cx42_bridge
, int level
,
308 struct ca91cx42_driver
*bridge
;
310 bridge
= ca91cx42_bridge
->driver_priv
;
312 /* Universe can only generate even vectors */
316 mutex_lock(&bridge
->vme_int
);
318 tmp
= ioread32(bridge
->base
+ VINT_EN
);
321 iowrite32(statid
<< 24, bridge
->base
+ STATID
);
323 /* Assert VMEbus IRQ */
324 tmp
= tmp
| (1 << (level
+ 24));
325 iowrite32(tmp
, bridge
->base
+ VINT_EN
);
328 wait_event_interruptible(bridge
->iack_queue
,
329 ca91cx42_iack_received(bridge
, level
));
331 /* Return interrupt to low state */
332 tmp
= ioread32(bridge
->base
+ VINT_EN
);
333 tmp
= tmp
& ~(1 << (level
+ 24));
334 iowrite32(tmp
, bridge
->base
+ VINT_EN
);
336 mutex_unlock(&bridge
->vme_int
);
341 static int ca91cx42_slave_set(struct vme_slave_resource
*image
, int enabled
,
342 unsigned long long vme_base
, unsigned long long size
,
343 dma_addr_t pci_base
, u32 aspace
, u32 cycle
)
345 unsigned int i
, addr
= 0, granularity
;
346 unsigned int temp_ctl
= 0;
347 unsigned int vme_bound
, pci_offset
;
348 struct vme_bridge
*ca91cx42_bridge
;
349 struct ca91cx42_driver
*bridge
;
351 ca91cx42_bridge
= image
->parent
;
353 bridge
= ca91cx42_bridge
->driver_priv
;
359 addr
|= CA91CX42_VSI_CTL_VAS_A16
;
362 addr
|= CA91CX42_VSI_CTL_VAS_A24
;
365 addr
|= CA91CX42_VSI_CTL_VAS_A32
;
368 addr
|= CA91CX42_VSI_CTL_VAS_USER1
;
371 addr
|= CA91CX42_VSI_CTL_VAS_USER2
;
378 dev_err(ca91cx42_bridge
->parent
, "Invalid address space\n");
384 * Bound address is a valid address for the window, adjust
387 vme_bound
= vme_base
+ size
;
388 pci_offset
= pci_base
- vme_base
;
390 if ((i
== 0) || (i
== 4))
391 granularity
= 0x1000;
393 granularity
= 0x10000;
395 if (vme_base
& (granularity
- 1)) {
396 dev_err(ca91cx42_bridge
->parent
, "Invalid VME base "
400 if (vme_bound
& (granularity
- 1)) {
401 dev_err(ca91cx42_bridge
->parent
, "Invalid VME bound "
405 if (pci_offset
& (granularity
- 1)) {
406 dev_err(ca91cx42_bridge
->parent
, "Invalid PCI Offset "
411 /* Disable while we are mucking around */
412 temp_ctl
= ioread32(bridge
->base
+ CA91CX42_VSI_CTL
[i
]);
413 temp_ctl
&= ~CA91CX42_VSI_CTL_EN
;
414 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_VSI_CTL
[i
]);
417 iowrite32(vme_base
, bridge
->base
+ CA91CX42_VSI_BS
[i
]);
418 iowrite32(vme_bound
, bridge
->base
+ CA91CX42_VSI_BD
[i
]);
419 iowrite32(pci_offset
, bridge
->base
+ CA91CX42_VSI_TO
[i
]);
421 /* Setup address space */
422 temp_ctl
&= ~CA91CX42_VSI_CTL_VAS_M
;
425 /* Setup cycle types */
426 temp_ctl
&= ~(CA91CX42_VSI_CTL_PGM_M
| CA91CX42_VSI_CTL_SUPER_M
);
427 if (cycle
& VME_SUPER
)
428 temp_ctl
|= CA91CX42_VSI_CTL_SUPER_SUPR
;
429 if (cycle
& VME_USER
)
430 temp_ctl
|= CA91CX42_VSI_CTL_SUPER_NPRIV
;
431 if (cycle
& VME_PROG
)
432 temp_ctl
|= CA91CX42_VSI_CTL_PGM_PGM
;
433 if (cycle
& VME_DATA
)
434 temp_ctl
|= CA91CX42_VSI_CTL_PGM_DATA
;
436 /* Write ctl reg without enable */
437 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_VSI_CTL
[i
]);
440 temp_ctl
|= CA91CX42_VSI_CTL_EN
;
442 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_VSI_CTL
[i
]);
447 static int ca91cx42_slave_get(struct vme_slave_resource
*image
, int *enabled
,
448 unsigned long long *vme_base
, unsigned long long *size
,
449 dma_addr_t
*pci_base
, u32
*aspace
, u32
*cycle
)
451 unsigned int i
, granularity
= 0, ctl
= 0;
452 unsigned long long vme_bound
, pci_offset
;
453 struct ca91cx42_driver
*bridge
;
455 bridge
= image
->parent
->driver_priv
;
459 if ((i
== 0) || (i
== 4))
460 granularity
= 0x1000;
462 granularity
= 0x10000;
465 ctl
= ioread32(bridge
->base
+ CA91CX42_VSI_CTL
[i
]);
467 *vme_base
= ioread32(bridge
->base
+ CA91CX42_VSI_BS
[i
]);
468 vme_bound
= ioread32(bridge
->base
+ CA91CX42_VSI_BD
[i
]);
469 pci_offset
= ioread32(bridge
->base
+ CA91CX42_VSI_TO
[i
]);
471 *pci_base
= (dma_addr_t
)vme_base
+ pci_offset
;
472 *size
= (unsigned long long)((vme_bound
- *vme_base
) + granularity
);
478 if (ctl
& CA91CX42_VSI_CTL_EN
)
481 if ((ctl
& CA91CX42_VSI_CTL_VAS_M
) == CA91CX42_VSI_CTL_VAS_A16
)
483 if ((ctl
& CA91CX42_VSI_CTL_VAS_M
) == CA91CX42_VSI_CTL_VAS_A24
)
485 if ((ctl
& CA91CX42_VSI_CTL_VAS_M
) == CA91CX42_VSI_CTL_VAS_A32
)
487 if ((ctl
& CA91CX42_VSI_CTL_VAS_M
) == CA91CX42_VSI_CTL_VAS_USER1
)
489 if ((ctl
& CA91CX42_VSI_CTL_VAS_M
) == CA91CX42_VSI_CTL_VAS_USER2
)
492 if (ctl
& CA91CX42_VSI_CTL_SUPER_SUPR
)
494 if (ctl
& CA91CX42_VSI_CTL_SUPER_NPRIV
)
496 if (ctl
& CA91CX42_VSI_CTL_PGM_PGM
)
498 if (ctl
& CA91CX42_VSI_CTL_PGM_DATA
)
505 * Allocate and map PCI Resource
507 static int ca91cx42_alloc_resource(struct vme_master_resource
*image
,
508 unsigned long long size
)
510 unsigned long long existing_size
;
512 struct pci_dev
*pdev
;
513 struct vme_bridge
*ca91cx42_bridge
;
515 ca91cx42_bridge
= image
->parent
;
517 /* Find pci_dev container of dev */
518 if (ca91cx42_bridge
->parent
== NULL
) {
519 dev_err(ca91cx42_bridge
->parent
, "Dev entry NULL\n");
522 pdev
= container_of(ca91cx42_bridge
->parent
, struct pci_dev
, dev
);
524 existing_size
= (unsigned long long)(image
->bus_resource
.end
-
525 image
->bus_resource
.start
);
527 /* If the existing size is OK, return */
528 if (existing_size
== (size
- 1))
531 if (existing_size
!= 0) {
532 iounmap(image
->kern_base
);
533 image
->kern_base
= NULL
;
534 kfree(image
->bus_resource
.name
);
535 release_resource(&image
->bus_resource
);
536 memset(&image
->bus_resource
, 0, sizeof(struct resource
));
539 if (image
->bus_resource
.name
== NULL
) {
540 image
->bus_resource
.name
= kmalloc(VMENAMSIZ
+3, GFP_ATOMIC
);
541 if (image
->bus_resource
.name
== NULL
) {
542 dev_err(ca91cx42_bridge
->parent
, "Unable to allocate "
543 "memory for resource name\n");
549 sprintf((char *)image
->bus_resource
.name
, "%s.%d",
550 ca91cx42_bridge
->name
, image
->number
);
552 image
->bus_resource
.start
= 0;
553 image
->bus_resource
.end
= (unsigned long)size
;
554 image
->bus_resource
.flags
= IORESOURCE_MEM
;
556 retval
= pci_bus_alloc_resource(pdev
->bus
,
557 &image
->bus_resource
, size
, size
, PCIBIOS_MIN_MEM
,
560 dev_err(ca91cx42_bridge
->parent
, "Failed to allocate mem "
561 "resource for window %d size 0x%lx start 0x%lx\n",
562 image
->number
, (unsigned long)size
,
563 (unsigned long)image
->bus_resource
.start
);
567 image
->kern_base
= ioremap_nocache(
568 image
->bus_resource
.start
, size
);
569 if (image
->kern_base
== NULL
) {
570 dev_err(ca91cx42_bridge
->parent
, "Failed to remap resource\n");
578 release_resource(&image
->bus_resource
);
580 kfree(image
->bus_resource
.name
);
581 memset(&image
->bus_resource
, 0, sizeof(struct resource
));
587 * Free and unmap PCI Resource
589 static void ca91cx42_free_resource(struct vme_master_resource
*image
)
591 iounmap(image
->kern_base
);
592 image
->kern_base
= NULL
;
593 release_resource(&image
->bus_resource
);
594 kfree(image
->bus_resource
.name
);
595 memset(&image
->bus_resource
, 0, sizeof(struct resource
));
599 static int ca91cx42_master_set(struct vme_master_resource
*image
, int enabled
,
600 unsigned long long vme_base
, unsigned long long size
, u32 aspace
,
601 u32 cycle
, u32 dwidth
)
604 unsigned int i
, granularity
= 0;
605 unsigned int temp_ctl
= 0;
606 unsigned long long pci_bound
, vme_offset
, pci_base
;
607 struct vme_bridge
*ca91cx42_bridge
;
608 struct ca91cx42_driver
*bridge
;
610 ca91cx42_bridge
= image
->parent
;
612 bridge
= ca91cx42_bridge
->driver_priv
;
616 if ((i
== 0) || (i
== 4))
617 granularity
= 0x1000;
619 granularity
= 0x10000;
621 /* Verify input data */
622 if (vme_base
& (granularity
- 1)) {
623 dev_err(ca91cx42_bridge
->parent
, "Invalid VME Window "
628 if (size
& (granularity
- 1)) {
629 dev_err(ca91cx42_bridge
->parent
, "Invalid VME Window "
635 spin_lock(&image
->lock
);
638 * Let's allocate the resource here rather than further up the stack as
639 * it avoids pushing loads of bus dependent stuff up the stack
641 retval
= ca91cx42_alloc_resource(image
, size
);
643 spin_unlock(&image
->lock
);
644 dev_err(ca91cx42_bridge
->parent
, "Unable to allocate memory "
645 "for resource name\n");
650 pci_base
= (unsigned long long)image
->bus_resource
.start
;
653 * Bound address is a valid address for the window, adjust
654 * according to window granularity.
656 pci_bound
= pci_base
+ size
;
657 vme_offset
= vme_base
- pci_base
;
659 /* Disable while we are mucking around */
660 temp_ctl
= ioread32(bridge
->base
+ CA91CX42_LSI_CTL
[i
]);
661 temp_ctl
&= ~CA91CX42_LSI_CTL_EN
;
662 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_LSI_CTL
[i
]);
664 /* Setup cycle types */
665 temp_ctl
&= ~CA91CX42_LSI_CTL_VCT_M
;
667 temp_ctl
|= CA91CX42_LSI_CTL_VCT_BLT
;
668 if (cycle
& VME_MBLT
)
669 temp_ctl
|= CA91CX42_LSI_CTL_VCT_MBLT
;
671 /* Setup data width */
672 temp_ctl
&= ~CA91CX42_LSI_CTL_VDW_M
;
675 temp_ctl
|= CA91CX42_LSI_CTL_VDW_D8
;
678 temp_ctl
|= CA91CX42_LSI_CTL_VDW_D16
;
681 temp_ctl
|= CA91CX42_LSI_CTL_VDW_D32
;
684 temp_ctl
|= CA91CX42_LSI_CTL_VDW_D64
;
687 spin_unlock(&image
->lock
);
688 dev_err(ca91cx42_bridge
->parent
, "Invalid data width\n");
694 /* Setup address space */
695 temp_ctl
&= ~CA91CX42_LSI_CTL_VAS_M
;
698 temp_ctl
|= CA91CX42_LSI_CTL_VAS_A16
;
701 temp_ctl
|= CA91CX42_LSI_CTL_VAS_A24
;
704 temp_ctl
|= CA91CX42_LSI_CTL_VAS_A32
;
707 temp_ctl
|= CA91CX42_LSI_CTL_VAS_CRCSR
;
710 temp_ctl
|= CA91CX42_LSI_CTL_VAS_USER1
;
713 temp_ctl
|= CA91CX42_LSI_CTL_VAS_USER2
;
719 spin_unlock(&image
->lock
);
720 dev_err(ca91cx42_bridge
->parent
, "Invalid address space\n");
726 temp_ctl
&= ~(CA91CX42_LSI_CTL_PGM_M
| CA91CX42_LSI_CTL_SUPER_M
);
727 if (cycle
& VME_SUPER
)
728 temp_ctl
|= CA91CX42_LSI_CTL_SUPER_SUPR
;
729 if (cycle
& VME_PROG
)
730 temp_ctl
|= CA91CX42_LSI_CTL_PGM_PGM
;
733 iowrite32(pci_base
, bridge
->base
+ CA91CX42_LSI_BS
[i
]);
734 iowrite32(pci_bound
, bridge
->base
+ CA91CX42_LSI_BD
[i
]);
735 iowrite32(vme_offset
, bridge
->base
+ CA91CX42_LSI_TO
[i
]);
737 /* Write ctl reg without enable */
738 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_LSI_CTL
[i
]);
741 temp_ctl
|= CA91CX42_LSI_CTL_EN
;
743 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_LSI_CTL
[i
]);
745 spin_unlock(&image
->lock
);
750 ca91cx42_free_resource(image
);
756 static int __ca91cx42_master_get(struct vme_master_resource
*image
,
757 int *enabled
, unsigned long long *vme_base
, unsigned long long *size
,
758 u32
*aspace
, u32
*cycle
, u32
*dwidth
)
761 unsigned long long pci_base
, pci_bound
, vme_offset
;
762 struct ca91cx42_driver
*bridge
;
764 bridge
= image
->parent
->driver_priv
;
768 ctl
= ioread32(bridge
->base
+ CA91CX42_LSI_CTL
[i
]);
770 pci_base
= ioread32(bridge
->base
+ CA91CX42_LSI_BS
[i
]);
771 vme_offset
= ioread32(bridge
->base
+ CA91CX42_LSI_TO
[i
]);
772 pci_bound
= ioread32(bridge
->base
+ CA91CX42_LSI_BD
[i
]);
774 *vme_base
= pci_base
+ vme_offset
;
775 *size
= (unsigned long long)(pci_bound
- pci_base
);
782 if (ctl
& CA91CX42_LSI_CTL_EN
)
785 /* Setup address space */
786 switch (ctl
& CA91CX42_LSI_CTL_VAS_M
) {
787 case CA91CX42_LSI_CTL_VAS_A16
:
790 case CA91CX42_LSI_CTL_VAS_A24
:
793 case CA91CX42_LSI_CTL_VAS_A32
:
796 case CA91CX42_LSI_CTL_VAS_CRCSR
:
799 case CA91CX42_LSI_CTL_VAS_USER1
:
802 case CA91CX42_LSI_CTL_VAS_USER2
:
807 /* XXX Not sure howto check for MBLT */
808 /* Setup cycle types */
809 if (ctl
& CA91CX42_LSI_CTL_VCT_BLT
)
814 if (ctl
& CA91CX42_LSI_CTL_SUPER_SUPR
)
819 if (ctl
& CA91CX42_LSI_CTL_PGM_PGM
)
824 /* Setup data width */
825 switch (ctl
& CA91CX42_LSI_CTL_VDW_M
) {
826 case CA91CX42_LSI_CTL_VDW_D8
:
829 case CA91CX42_LSI_CTL_VDW_D16
:
832 case CA91CX42_LSI_CTL_VDW_D32
:
835 case CA91CX42_LSI_CTL_VDW_D64
:
843 static int ca91cx42_master_get(struct vme_master_resource
*image
, int *enabled
,
844 unsigned long long *vme_base
, unsigned long long *size
, u32
*aspace
,
845 u32
*cycle
, u32
*dwidth
)
849 spin_lock(&image
->lock
);
851 retval
= __ca91cx42_master_get(image
, enabled
, vme_base
, size
, aspace
,
854 spin_unlock(&image
->lock
);
859 static ssize_t
ca91cx42_master_read(struct vme_master_resource
*image
,
860 void *buf
, size_t count
, loff_t offset
)
863 void __iomem
*addr
= image
->kern_base
+ offset
;
864 unsigned int done
= 0;
865 unsigned int count32
;
870 spin_lock(&image
->lock
);
872 /* The following code handles VME address alignment problem
873 * in order to assure the maximal data width cycle.
874 * We cannot use memcpy_xxx directly here because it
875 * may cut data transfer in 8-bits cycles, thus making
876 * D16 cycle impossible.
877 * From the other hand, the bridge itself assures that
878 * maximal configured data cycle is used and splits it
879 * automatically for non-aligned addresses.
881 if ((uintptr_t)addr
& 0x1) {
882 *(u8
*)buf
= ioread8(addr
);
887 if ((uintptr_t)(addr
+ done
) & 0x2) {
888 if ((count
- done
) < 2) {
889 *(u8
*)(buf
+ done
) = ioread8(addr
+ done
);
893 *(u16
*)(buf
+ done
) = ioread16(addr
+ done
);
898 count32
= (count
- done
) & ~0x3;
900 memcpy_fromio(buf
+ done
, addr
+ done
, (unsigned int)count
);
904 if ((count
- done
) & 0x2) {
905 *(u16
*)(buf
+ done
) = ioread16(addr
+ done
);
908 if ((count
- done
) & 0x1) {
909 *(u8
*)(buf
+ done
) = ioread8(addr
+ done
);
914 spin_unlock(&image
->lock
);
919 static ssize_t
ca91cx42_master_write(struct vme_master_resource
*image
,
920 void *buf
, size_t count
, loff_t offset
)
923 void __iomem
*addr
= image
->kern_base
+ offset
;
924 unsigned int done
= 0;
925 unsigned int count32
;
930 spin_lock(&image
->lock
);
932 /* Here we apply for the same strategy we do in master_read
933 * function in order to assure D16 cycle when required.
935 if ((uintptr_t)addr
& 0x1) {
936 iowrite8(*(u8
*)buf
, addr
);
941 if ((uintptr_t)(addr
+ done
) & 0x2) {
942 if ((count
- done
) < 2) {
943 iowrite8(*(u8
*)(buf
+ done
), addr
+ done
);
947 iowrite16(*(u16
*)(buf
+ done
), addr
+ done
);
952 count32
= (count
- done
) & ~0x3;
954 memcpy_toio(addr
+ done
, buf
+ done
, count32
);
958 if ((count
- done
) & 0x2) {
959 iowrite16(*(u16
*)(buf
+ done
), addr
+ done
);
962 if ((count
- done
) & 0x1) {
963 iowrite8(*(u8
*)(buf
+ done
), addr
+ done
);
969 spin_unlock(&image
->lock
);
974 static unsigned int ca91cx42_master_rmw(struct vme_master_resource
*image
,
975 unsigned int mask
, unsigned int compare
, unsigned int swap
,
981 struct ca91cx42_driver
*bridge
;
984 bridge
= image
->parent
->driver_priv
;
985 dev
= image
->parent
->parent
;
987 /* Find the PCI address that maps to the desired VME address */
990 /* Locking as we can only do one of these at a time */
991 mutex_lock(&bridge
->vme_rmw
);
994 spin_lock(&image
->lock
);
996 pci_addr
= (uintptr_t)image
->kern_base
+ offset
;
998 /* Address must be 4-byte aligned */
999 if (pci_addr
& 0x3) {
1000 dev_err(dev
, "RMW Address not 4-byte aligned\n");
1005 /* Ensure RMW Disabled whilst configuring */
1006 iowrite32(0, bridge
->base
+ SCYC_CTL
);
1008 /* Configure registers */
1009 iowrite32(mask
, bridge
->base
+ SCYC_EN
);
1010 iowrite32(compare
, bridge
->base
+ SCYC_CMP
);
1011 iowrite32(swap
, bridge
->base
+ SCYC_SWP
);
1012 iowrite32(pci_addr
, bridge
->base
+ SCYC_ADDR
);
1015 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW
, bridge
->base
+ SCYC_CTL
);
1017 /* Kick process off with a read to the required address. */
1018 result
= ioread32(image
->kern_base
+ offset
);
1021 iowrite32(0, bridge
->base
+ SCYC_CTL
);
1024 spin_unlock(&image
->lock
);
1026 mutex_unlock(&bridge
->vme_rmw
);
1031 static int ca91cx42_dma_list_add(struct vme_dma_list
*list
,
1032 struct vme_dma_attr
*src
, struct vme_dma_attr
*dest
, size_t count
)
1034 struct ca91cx42_dma_entry
*entry
, *prev
;
1035 struct vme_dma_pci
*pci_attr
;
1036 struct vme_dma_vme
*vme_attr
;
1037 dma_addr_t desc_ptr
;
1041 dev
= list
->parent
->parent
->parent
;
1043 /* XXX descriptor must be aligned on 64-bit boundaries */
1044 entry
= kmalloc(sizeof(struct ca91cx42_dma_entry
), GFP_KERNEL
);
1045 if (entry
== NULL
) {
1046 dev_err(dev
, "Failed to allocate memory for dma resource "
1052 /* Test descriptor alignment */
1053 if ((unsigned long)&entry
->descriptor
& CA91CX42_DCPP_M
) {
1054 dev_err(dev
, "Descriptor not aligned to 16 byte boundary as "
1055 "required: %p\n", &entry
->descriptor
);
1060 memset(&entry
->descriptor
, 0, sizeof(struct ca91cx42_dma_descriptor
));
1062 if (dest
->type
== VME_DMA_VME
) {
1063 entry
->descriptor
.dctl
|= CA91CX42_DCTL_L2V
;
1064 vme_attr
= dest
->private;
1065 pci_attr
= src
->private;
1067 vme_attr
= src
->private;
1068 pci_attr
= dest
->private;
1071 /* Check we can do fulfill required attributes */
1072 if ((vme_attr
->aspace
& ~(VME_A16
| VME_A24
| VME_A32
| VME_USER1
|
1075 dev_err(dev
, "Unsupported cycle type\n");
1080 if ((vme_attr
->cycle
& ~(VME_SCT
| VME_BLT
| VME_SUPER
| VME_USER
|
1081 VME_PROG
| VME_DATA
)) != 0) {
1083 dev_err(dev
, "Unsupported cycle type\n");
1088 /* Check to see if we can fulfill source and destination */
1089 if (!(((src
->type
== VME_DMA_PCI
) && (dest
->type
== VME_DMA_VME
)) ||
1090 ((src
->type
== VME_DMA_VME
) && (dest
->type
== VME_DMA_PCI
)))) {
1092 dev_err(dev
, "Cannot perform transfer with this "
1093 "source-destination combination\n");
1098 /* Setup cycle types */
1099 if (vme_attr
->cycle
& VME_BLT
)
1100 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VCT_BLT
;
1102 /* Setup data width */
1103 switch (vme_attr
->dwidth
) {
1105 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VDW_D8
;
1108 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VDW_D16
;
1111 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VDW_D32
;
1114 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VDW_D64
;
1117 dev_err(dev
, "Invalid data width\n");
1121 /* Setup address space */
1122 switch (vme_attr
->aspace
) {
1124 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VAS_A16
;
1127 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VAS_A24
;
1130 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VAS_A32
;
1133 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VAS_USER1
;
1136 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VAS_USER2
;
1139 dev_err(dev
, "Invalid address space\n");
1144 if (vme_attr
->cycle
& VME_SUPER
)
1145 entry
->descriptor
.dctl
|= CA91CX42_DCTL_SUPER_SUPR
;
1146 if (vme_attr
->cycle
& VME_PROG
)
1147 entry
->descriptor
.dctl
|= CA91CX42_DCTL_PGM_PGM
;
1149 entry
->descriptor
.dtbc
= count
;
1150 entry
->descriptor
.dla
= pci_attr
->address
;
1151 entry
->descriptor
.dva
= vme_attr
->address
;
1152 entry
->descriptor
.dcpp
= CA91CX42_DCPP_NULL
;
1155 list_add_tail(&entry
->list
, &list
->entries
);
1157 /* Fill out previous descriptors "Next Address" */
1158 if (entry
->list
.prev
!= &list
->entries
) {
1159 prev
= list_entry(entry
->list
.prev
, struct ca91cx42_dma_entry
,
1161 /* We need the bus address for the pointer */
1162 desc_ptr
= virt_to_bus(&entry
->descriptor
);
1163 prev
->descriptor
.dcpp
= desc_ptr
& ~CA91CX42_DCPP_M
;
1177 static int ca91cx42_dma_busy(struct vme_bridge
*ca91cx42_bridge
)
1180 struct ca91cx42_driver
*bridge
;
1182 bridge
= ca91cx42_bridge
->driver_priv
;
1184 tmp
= ioread32(bridge
->base
+ DGCS
);
1186 if (tmp
& CA91CX42_DGCS_ACT
)
1192 static int ca91cx42_dma_list_exec(struct vme_dma_list
*list
)
1194 struct vme_dma_resource
*ctrlr
;
1195 struct ca91cx42_dma_entry
*entry
;
1197 dma_addr_t bus_addr
;
1200 struct ca91cx42_driver
*bridge
;
1202 ctrlr
= list
->parent
;
1204 bridge
= ctrlr
->parent
->driver_priv
;
1205 dev
= ctrlr
->parent
->parent
;
1207 mutex_lock(&ctrlr
->mtx
);
1209 if (!(list_empty(&ctrlr
->running
))) {
1211 * XXX We have an active DMA transfer and currently haven't
1212 * sorted out the mechanism for "pending" DMA transfers.
1215 /* Need to add to pending here */
1216 mutex_unlock(&ctrlr
->mtx
);
1219 list_add(&list
->list
, &ctrlr
->running
);
1222 /* Get first bus address and write into registers */
1223 entry
= list_first_entry(&list
->entries
, struct ca91cx42_dma_entry
,
1226 bus_addr
= virt_to_bus(&entry
->descriptor
);
1228 mutex_unlock(&ctrlr
->mtx
);
1230 iowrite32(0, bridge
->base
+ DTBC
);
1231 iowrite32(bus_addr
& ~CA91CX42_DCPP_M
, bridge
->base
+ DCPP
);
1233 /* Start the operation */
1234 val
= ioread32(bridge
->base
+ DGCS
);
1236 /* XXX Could set VMEbus On and Off Counters here */
1237 val
&= (CA91CX42_DGCS_VON_M
| CA91CX42_DGCS_VOFF_M
);
1239 val
|= (CA91CX42_DGCS_CHAIN
| CA91CX42_DGCS_STOP
| CA91CX42_DGCS_HALT
|
1240 CA91CX42_DGCS_DONE
| CA91CX42_DGCS_LERR
| CA91CX42_DGCS_VERR
|
1241 CA91CX42_DGCS_PERR
);
1243 iowrite32(val
, bridge
->base
+ DGCS
);
1245 val
|= CA91CX42_DGCS_GO
;
1247 iowrite32(val
, bridge
->base
+ DGCS
);
1249 wait_event_interruptible(bridge
->dma_queue
,
1250 ca91cx42_dma_busy(ctrlr
->parent
));
1253 * Read status register, this register is valid until we kick off a
1256 val
= ioread32(bridge
->base
+ DGCS
);
1258 if (val
& (CA91CX42_DGCS_LERR
| CA91CX42_DGCS_VERR
|
1259 CA91CX42_DGCS_PERR
)) {
1261 dev_err(dev
, "ca91c042: DMA Error. DGCS=%08X\n", val
);
1262 val
= ioread32(bridge
->base
+ DCTL
);
1265 /* Remove list from running list */
1266 mutex_lock(&ctrlr
->mtx
);
1267 list_del(&list
->list
);
1268 mutex_unlock(&ctrlr
->mtx
);
1274 static int ca91cx42_dma_list_empty(struct vme_dma_list
*list
)
1276 struct list_head
*pos
, *temp
;
1277 struct ca91cx42_dma_entry
*entry
;
1279 /* detach and free each entry */
1280 list_for_each_safe(pos
, temp
, &list
->entries
) {
1282 entry
= list_entry(pos
, struct ca91cx42_dma_entry
, list
);
1290 * All 4 location monitors reside at the same base - this is therefore a
1291 * system wide configuration.
1293 * This does not enable the LM monitor - that should be done when the first
1294 * callback is attached and disabled when the last callback is removed.
1296 static int ca91cx42_lm_set(struct vme_lm_resource
*lm
,
1297 unsigned long long lm_base
, u32 aspace
, u32 cycle
)
1299 u32 temp_base
, lm_ctl
= 0;
1301 struct ca91cx42_driver
*bridge
;
1304 bridge
= lm
->parent
->driver_priv
;
1305 dev
= lm
->parent
->parent
;
1307 /* Check the alignment of the location monitor */
1308 temp_base
= (u32
)lm_base
;
1309 if (temp_base
& 0xffff) {
1310 dev_err(dev
, "Location monitor must be aligned to 64KB "
1315 mutex_lock(&lm
->mtx
);
1317 /* If we already have a callback attached, we can't move it! */
1318 for (i
= 0; i
< lm
->monitors
; i
++) {
1319 if (bridge
->lm_callback
[i
] != NULL
) {
1320 mutex_unlock(&lm
->mtx
);
1321 dev_err(dev
, "Location monitor callback attached, "
1329 lm_ctl
|= CA91CX42_LM_CTL_AS_A16
;
1332 lm_ctl
|= CA91CX42_LM_CTL_AS_A24
;
1335 lm_ctl
|= CA91CX42_LM_CTL_AS_A32
;
1338 mutex_unlock(&lm
->mtx
);
1339 dev_err(dev
, "Invalid address space\n");
1344 if (cycle
& VME_SUPER
)
1345 lm_ctl
|= CA91CX42_LM_CTL_SUPR
;
1346 if (cycle
& VME_USER
)
1347 lm_ctl
|= CA91CX42_LM_CTL_NPRIV
;
1348 if (cycle
& VME_PROG
)
1349 lm_ctl
|= CA91CX42_LM_CTL_PGM
;
1350 if (cycle
& VME_DATA
)
1351 lm_ctl
|= CA91CX42_LM_CTL_DATA
;
1353 iowrite32(lm_base
, bridge
->base
+ LM_BS
);
1354 iowrite32(lm_ctl
, bridge
->base
+ LM_CTL
);
1356 mutex_unlock(&lm
->mtx
);
1361 /* Get configuration of the callback monitor and return whether it is enabled
1364 static int ca91cx42_lm_get(struct vme_lm_resource
*lm
,
1365 unsigned long long *lm_base
, u32
*aspace
, u32
*cycle
)
1367 u32 lm_ctl
, enabled
= 0;
1368 struct ca91cx42_driver
*bridge
;
1370 bridge
= lm
->parent
->driver_priv
;
1372 mutex_lock(&lm
->mtx
);
1374 *lm_base
= (unsigned long long)ioread32(bridge
->base
+ LM_BS
);
1375 lm_ctl
= ioread32(bridge
->base
+ LM_CTL
);
1377 if (lm_ctl
& CA91CX42_LM_CTL_EN
)
1380 if ((lm_ctl
& CA91CX42_LM_CTL_AS_M
) == CA91CX42_LM_CTL_AS_A16
)
1382 if ((lm_ctl
& CA91CX42_LM_CTL_AS_M
) == CA91CX42_LM_CTL_AS_A24
)
1384 if ((lm_ctl
& CA91CX42_LM_CTL_AS_M
) == CA91CX42_LM_CTL_AS_A32
)
1388 if (lm_ctl
& CA91CX42_LM_CTL_SUPR
)
1389 *cycle
|= VME_SUPER
;
1390 if (lm_ctl
& CA91CX42_LM_CTL_NPRIV
)
1392 if (lm_ctl
& CA91CX42_LM_CTL_PGM
)
1394 if (lm_ctl
& CA91CX42_LM_CTL_DATA
)
1397 mutex_unlock(&lm
->mtx
);
1403 * Attach a callback to a specific location monitor.
1405 * Callback will be passed the monitor triggered.
1407 static int ca91cx42_lm_attach(struct vme_lm_resource
*lm
, int monitor
,
1408 void (*callback
)(int))
1411 struct ca91cx42_driver
*bridge
;
1414 bridge
= lm
->parent
->driver_priv
;
1415 dev
= lm
->parent
->parent
;
1417 mutex_lock(&lm
->mtx
);
1419 /* Ensure that the location monitor is configured - need PGM or DATA */
1420 lm_ctl
= ioread32(bridge
->base
+ LM_CTL
);
1421 if ((lm_ctl
& (CA91CX42_LM_CTL_PGM
| CA91CX42_LM_CTL_DATA
)) == 0) {
1422 mutex_unlock(&lm
->mtx
);
1423 dev_err(dev
, "Location monitor not properly configured\n");
1427 /* Check that a callback isn't already attached */
1428 if (bridge
->lm_callback
[monitor
] != NULL
) {
1429 mutex_unlock(&lm
->mtx
);
1430 dev_err(dev
, "Existing callback attached\n");
1434 /* Attach callback */
1435 bridge
->lm_callback
[monitor
] = callback
;
1437 /* Enable Location Monitor interrupt */
1438 tmp
= ioread32(bridge
->base
+ LINT_EN
);
1439 tmp
|= CA91CX42_LINT_LM
[monitor
];
1440 iowrite32(tmp
, bridge
->base
+ LINT_EN
);
1442 /* Ensure that global Location Monitor Enable set */
1443 if ((lm_ctl
& CA91CX42_LM_CTL_EN
) == 0) {
1444 lm_ctl
|= CA91CX42_LM_CTL_EN
;
1445 iowrite32(lm_ctl
, bridge
->base
+ LM_CTL
);
1448 mutex_unlock(&lm
->mtx
);
1454 * Detach a callback function forn a specific location monitor.
1456 static int ca91cx42_lm_detach(struct vme_lm_resource
*lm
, int monitor
)
1459 struct ca91cx42_driver
*bridge
;
1461 bridge
= lm
->parent
->driver_priv
;
1463 mutex_lock(&lm
->mtx
);
1465 /* Disable Location Monitor and ensure previous interrupts are clear */
1466 tmp
= ioread32(bridge
->base
+ LINT_EN
);
1467 tmp
&= ~CA91CX42_LINT_LM
[monitor
];
1468 iowrite32(tmp
, bridge
->base
+ LINT_EN
);
1470 iowrite32(CA91CX42_LINT_LM
[monitor
],
1471 bridge
->base
+ LINT_STAT
);
1473 /* Detach callback */
1474 bridge
->lm_callback
[monitor
] = NULL
;
1476 /* If all location monitors disabled, disable global Location Monitor */
1477 if ((tmp
& (CA91CX42_LINT_LM0
| CA91CX42_LINT_LM1
| CA91CX42_LINT_LM2
|
1478 CA91CX42_LINT_LM3
)) == 0) {
1479 tmp
= ioread32(bridge
->base
+ LM_CTL
);
1480 tmp
&= ~CA91CX42_LM_CTL_EN
;
1481 iowrite32(tmp
, bridge
->base
+ LM_CTL
);
1484 mutex_unlock(&lm
->mtx
);
1489 static int ca91cx42_slot_get(struct vme_bridge
*ca91cx42_bridge
)
1492 struct ca91cx42_driver
*bridge
;
1494 bridge
= ca91cx42_bridge
->driver_priv
;
1497 slot
= ioread32(bridge
->base
+ VCSR_BS
);
1498 slot
= ((slot
& CA91CX42_VCSR_BS_SLOT_M
) >> 27);
1506 static void *ca91cx42_alloc_consistent(struct device
*parent
, size_t size
,
1509 struct pci_dev
*pdev
;
1511 /* Find pci_dev container of dev */
1512 pdev
= container_of(parent
, struct pci_dev
, dev
);
1514 return pci_alloc_consistent(pdev
, size
, dma
);
1517 static void ca91cx42_free_consistent(struct device
*parent
, size_t size
,
1518 void *vaddr
, dma_addr_t dma
)
1520 struct pci_dev
*pdev
;
1522 /* Find pci_dev container of dev */
1523 pdev
= container_of(parent
, struct pci_dev
, dev
);
1525 pci_free_consistent(pdev
, size
, vaddr
, dma
);
1529 * Configure CR/CSR space
1531 * Access to the CR/CSR can be configured at power-up. The location of the
1532 * CR/CSR registers in the CR/CSR address space is determined by the boards
1533 * Auto-ID or Geographic address. This function ensures that the window is
1534 * enabled at an offset consistent with the boards geopgraphic address.
1536 static int ca91cx42_crcsr_init(struct vme_bridge
*ca91cx42_bridge
,
1537 struct pci_dev
*pdev
)
1539 unsigned int crcsr_addr
;
1541 struct ca91cx42_driver
*bridge
;
1543 bridge
= ca91cx42_bridge
->driver_priv
;
1545 slot
= ca91cx42_slot_get(ca91cx42_bridge
);
1547 /* Write CSR Base Address if slot ID is supplied as a module param */
1549 iowrite32(geoid
<< 27, bridge
->base
+ VCSR_BS
);
1551 dev_info(&pdev
->dev
, "CR/CSR Offset: %d\n", slot
);
1553 dev_err(&pdev
->dev
, "Slot number is unset, not configuring "
1558 /* Allocate mem for CR/CSR image */
1559 bridge
->crcsr_kernel
= pci_alloc_consistent(pdev
, VME_CRCSR_BUF_SIZE
,
1560 &bridge
->crcsr_bus
);
1561 if (bridge
->crcsr_kernel
== NULL
) {
1562 dev_err(&pdev
->dev
, "Failed to allocate memory for CR/CSR "
1567 memset(bridge
->crcsr_kernel
, 0, VME_CRCSR_BUF_SIZE
);
1569 crcsr_addr
= slot
* (512 * 1024);
1570 iowrite32(bridge
->crcsr_bus
- crcsr_addr
, bridge
->base
+ VCSR_TO
);
1572 tmp
= ioread32(bridge
->base
+ VCSR_CTL
);
1573 tmp
|= CA91CX42_VCSR_CTL_EN
;
1574 iowrite32(tmp
, bridge
->base
+ VCSR_CTL
);
1579 static void ca91cx42_crcsr_exit(struct vme_bridge
*ca91cx42_bridge
,
1580 struct pci_dev
*pdev
)
1583 struct ca91cx42_driver
*bridge
;
1585 bridge
= ca91cx42_bridge
->driver_priv
;
1587 /* Turn off CR/CSR space */
1588 tmp
= ioread32(bridge
->base
+ VCSR_CTL
);
1589 tmp
&= ~CA91CX42_VCSR_CTL_EN
;
1590 iowrite32(tmp
, bridge
->base
+ VCSR_CTL
);
1593 iowrite32(0, bridge
->base
+ VCSR_TO
);
1595 pci_free_consistent(pdev
, VME_CRCSR_BUF_SIZE
, bridge
->crcsr_kernel
,
1599 static int ca91cx42_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1603 struct list_head
*pos
= NULL
, *n
;
1604 struct vme_bridge
*ca91cx42_bridge
;
1605 struct ca91cx42_driver
*ca91cx42_device
;
1606 struct vme_master_resource
*master_image
;
1607 struct vme_slave_resource
*slave_image
;
1608 struct vme_dma_resource
*dma_ctrlr
;
1609 struct vme_lm_resource
*lm
;
1611 /* We want to support more than one of each bridge so we need to
1612 * dynamically allocate the bridge structure
1614 ca91cx42_bridge
= kzalloc(sizeof(struct vme_bridge
), GFP_KERNEL
);
1616 if (ca91cx42_bridge
== NULL
) {
1617 dev_err(&pdev
->dev
, "Failed to allocate memory for device "
1623 ca91cx42_device
= kzalloc(sizeof(struct ca91cx42_driver
), GFP_KERNEL
);
1625 if (ca91cx42_device
== NULL
) {
1626 dev_err(&pdev
->dev
, "Failed to allocate memory for device "
1632 ca91cx42_bridge
->driver_priv
= ca91cx42_device
;
1634 /* Enable the device */
1635 retval
= pci_enable_device(pdev
);
1637 dev_err(&pdev
->dev
, "Unable to enable device\n");
1642 retval
= pci_request_regions(pdev
, driver_name
);
1644 dev_err(&pdev
->dev
, "Unable to reserve resources\n");
1648 /* map registers in BAR 0 */
1649 ca91cx42_device
->base
= ioremap_nocache(pci_resource_start(pdev
, 0),
1651 if (!ca91cx42_device
->base
) {
1652 dev_err(&pdev
->dev
, "Unable to remap CRG region\n");
1657 /* Check to see if the mapping worked out */
1658 data
= ioread32(ca91cx42_device
->base
+ CA91CX42_PCI_ID
) & 0x0000FFFF;
1659 if (data
!= PCI_VENDOR_ID_TUNDRA
) {
1660 dev_err(&pdev
->dev
, "PCI_ID check failed\n");
1665 /* Initialize wait queues & mutual exclusion flags */
1666 init_waitqueue_head(&ca91cx42_device
->dma_queue
);
1667 init_waitqueue_head(&ca91cx42_device
->iack_queue
);
1668 mutex_init(&ca91cx42_device
->vme_int
);
1669 mutex_init(&ca91cx42_device
->vme_rmw
);
1671 ca91cx42_bridge
->parent
= &pdev
->dev
;
1672 strcpy(ca91cx42_bridge
->name
, driver_name
);
1675 retval
= ca91cx42_irq_init(ca91cx42_bridge
);
1677 dev_err(&pdev
->dev
, "Chip Initialization failed.\n");
1681 /* Add master windows to list */
1682 INIT_LIST_HEAD(&ca91cx42_bridge
->master_resources
);
1683 for (i
= 0; i
< CA91C142_MAX_MASTER
; i
++) {
1684 master_image
= kmalloc(sizeof(struct vme_master_resource
),
1686 if (master_image
== NULL
) {
1687 dev_err(&pdev
->dev
, "Failed to allocate memory for "
1688 "master resource structure\n");
1692 master_image
->parent
= ca91cx42_bridge
;
1693 spin_lock_init(&master_image
->lock
);
1694 master_image
->locked
= 0;
1695 master_image
->number
= i
;
1696 master_image
->address_attr
= VME_A16
| VME_A24
| VME_A32
|
1697 VME_CRCSR
| VME_USER1
| VME_USER2
;
1698 master_image
->cycle_attr
= VME_SCT
| VME_BLT
| VME_MBLT
|
1699 VME_SUPER
| VME_USER
| VME_PROG
| VME_DATA
;
1700 master_image
->width_attr
= VME_D8
| VME_D16
| VME_D32
| VME_D64
;
1701 memset(&master_image
->bus_resource
, 0,
1702 sizeof(struct resource
));
1703 master_image
->kern_base
= NULL
;
1704 list_add_tail(&master_image
->list
,
1705 &ca91cx42_bridge
->master_resources
);
1708 /* Add slave windows to list */
1709 INIT_LIST_HEAD(&ca91cx42_bridge
->slave_resources
);
1710 for (i
= 0; i
< CA91C142_MAX_SLAVE
; i
++) {
1711 slave_image
= kmalloc(sizeof(struct vme_slave_resource
),
1713 if (slave_image
== NULL
) {
1714 dev_err(&pdev
->dev
, "Failed to allocate memory for "
1715 "slave resource structure\n");
1719 slave_image
->parent
= ca91cx42_bridge
;
1720 mutex_init(&slave_image
->mtx
);
1721 slave_image
->locked
= 0;
1722 slave_image
->number
= i
;
1723 slave_image
->address_attr
= VME_A24
| VME_A32
| VME_USER1
|
1726 /* Only windows 0 and 4 support A16 */
1727 if (i
== 0 || i
== 4)
1728 slave_image
->address_attr
|= VME_A16
;
1730 slave_image
->cycle_attr
= VME_SCT
| VME_BLT
| VME_MBLT
|
1731 VME_SUPER
| VME_USER
| VME_PROG
| VME_DATA
;
1732 list_add_tail(&slave_image
->list
,
1733 &ca91cx42_bridge
->slave_resources
);
1736 /* Add dma engines to list */
1737 INIT_LIST_HEAD(&ca91cx42_bridge
->dma_resources
);
1738 for (i
= 0; i
< CA91C142_MAX_DMA
; i
++) {
1739 dma_ctrlr
= kmalloc(sizeof(struct vme_dma_resource
),
1741 if (dma_ctrlr
== NULL
) {
1742 dev_err(&pdev
->dev
, "Failed to allocate memory for "
1743 "dma resource structure\n");
1747 dma_ctrlr
->parent
= ca91cx42_bridge
;
1748 mutex_init(&dma_ctrlr
->mtx
);
1749 dma_ctrlr
->locked
= 0;
1750 dma_ctrlr
->number
= i
;
1751 dma_ctrlr
->route_attr
= VME_DMA_VME_TO_MEM
|
1753 INIT_LIST_HEAD(&dma_ctrlr
->pending
);
1754 INIT_LIST_HEAD(&dma_ctrlr
->running
);
1755 list_add_tail(&dma_ctrlr
->list
,
1756 &ca91cx42_bridge
->dma_resources
);
1759 /* Add location monitor to list */
1760 INIT_LIST_HEAD(&ca91cx42_bridge
->lm_resources
);
1761 lm
= kmalloc(sizeof(struct vme_lm_resource
), GFP_KERNEL
);
1763 dev_err(&pdev
->dev
, "Failed to allocate memory for "
1764 "location monitor resource structure\n");
1768 lm
->parent
= ca91cx42_bridge
;
1769 mutex_init(&lm
->mtx
);
1773 list_add_tail(&lm
->list
, &ca91cx42_bridge
->lm_resources
);
1775 ca91cx42_bridge
->slave_get
= ca91cx42_slave_get
;
1776 ca91cx42_bridge
->slave_set
= ca91cx42_slave_set
;
1777 ca91cx42_bridge
->master_get
= ca91cx42_master_get
;
1778 ca91cx42_bridge
->master_set
= ca91cx42_master_set
;
1779 ca91cx42_bridge
->master_read
= ca91cx42_master_read
;
1780 ca91cx42_bridge
->master_write
= ca91cx42_master_write
;
1781 ca91cx42_bridge
->master_rmw
= ca91cx42_master_rmw
;
1782 ca91cx42_bridge
->dma_list_add
= ca91cx42_dma_list_add
;
1783 ca91cx42_bridge
->dma_list_exec
= ca91cx42_dma_list_exec
;
1784 ca91cx42_bridge
->dma_list_empty
= ca91cx42_dma_list_empty
;
1785 ca91cx42_bridge
->irq_set
= ca91cx42_irq_set
;
1786 ca91cx42_bridge
->irq_generate
= ca91cx42_irq_generate
;
1787 ca91cx42_bridge
->lm_set
= ca91cx42_lm_set
;
1788 ca91cx42_bridge
->lm_get
= ca91cx42_lm_get
;
1789 ca91cx42_bridge
->lm_attach
= ca91cx42_lm_attach
;
1790 ca91cx42_bridge
->lm_detach
= ca91cx42_lm_detach
;
1791 ca91cx42_bridge
->slot_get
= ca91cx42_slot_get
;
1792 ca91cx42_bridge
->alloc_consistent
= ca91cx42_alloc_consistent
;
1793 ca91cx42_bridge
->free_consistent
= ca91cx42_free_consistent
;
1795 data
= ioread32(ca91cx42_device
->base
+ MISC_CTL
);
1796 dev_info(&pdev
->dev
, "Board is%s the VME system controller\n",
1797 (data
& CA91CX42_MISC_CTL_SYSCON
) ? "" : " not");
1798 dev_info(&pdev
->dev
, "Slot ID is %d\n",
1799 ca91cx42_slot_get(ca91cx42_bridge
));
1801 if (ca91cx42_crcsr_init(ca91cx42_bridge
, pdev
))
1802 dev_err(&pdev
->dev
, "CR/CSR configuration failed.\n");
1804 /* Need to save ca91cx42_bridge pointer locally in link list for use in
1807 retval
= vme_register_bridge(ca91cx42_bridge
);
1809 dev_err(&pdev
->dev
, "Chip Registration failed.\n");
1813 pci_set_drvdata(pdev
, ca91cx42_bridge
);
1818 ca91cx42_crcsr_exit(ca91cx42_bridge
, pdev
);
1820 /* resources are stored in link list */
1821 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->lm_resources
) {
1822 lm
= list_entry(pos
, struct vme_lm_resource
, list
);
1827 /* resources are stored in link list */
1828 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->dma_resources
) {
1829 dma_ctrlr
= list_entry(pos
, struct vme_dma_resource
, list
);
1834 /* resources are stored in link list */
1835 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->slave_resources
) {
1836 slave_image
= list_entry(pos
, struct vme_slave_resource
, list
);
1841 /* resources are stored in link list */
1842 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->master_resources
) {
1843 master_image
= list_entry(pos
, struct vme_master_resource
,
1846 kfree(master_image
);
1849 ca91cx42_irq_exit(ca91cx42_device
, pdev
);
1852 iounmap(ca91cx42_device
->base
);
1854 pci_release_regions(pdev
);
1856 pci_disable_device(pdev
);
1858 kfree(ca91cx42_device
);
1860 kfree(ca91cx42_bridge
);
1866 static void ca91cx42_remove(struct pci_dev
*pdev
)
1868 struct list_head
*pos
= NULL
, *n
;
1869 struct vme_master_resource
*master_image
;
1870 struct vme_slave_resource
*slave_image
;
1871 struct vme_dma_resource
*dma_ctrlr
;
1872 struct vme_lm_resource
*lm
;
1873 struct ca91cx42_driver
*bridge
;
1874 struct vme_bridge
*ca91cx42_bridge
= pci_get_drvdata(pdev
);
1876 bridge
= ca91cx42_bridge
->driver_priv
;
1880 iowrite32(0, bridge
->base
+ LINT_EN
);
1882 /* Turn off the windows */
1883 iowrite32(0x00800000, bridge
->base
+ LSI0_CTL
);
1884 iowrite32(0x00800000, bridge
->base
+ LSI1_CTL
);
1885 iowrite32(0x00800000, bridge
->base
+ LSI2_CTL
);
1886 iowrite32(0x00800000, bridge
->base
+ LSI3_CTL
);
1887 iowrite32(0x00800000, bridge
->base
+ LSI4_CTL
);
1888 iowrite32(0x00800000, bridge
->base
+ LSI5_CTL
);
1889 iowrite32(0x00800000, bridge
->base
+ LSI6_CTL
);
1890 iowrite32(0x00800000, bridge
->base
+ LSI7_CTL
);
1891 iowrite32(0x00F00000, bridge
->base
+ VSI0_CTL
);
1892 iowrite32(0x00F00000, bridge
->base
+ VSI1_CTL
);
1893 iowrite32(0x00F00000, bridge
->base
+ VSI2_CTL
);
1894 iowrite32(0x00F00000, bridge
->base
+ VSI3_CTL
);
1895 iowrite32(0x00F00000, bridge
->base
+ VSI4_CTL
);
1896 iowrite32(0x00F00000, bridge
->base
+ VSI5_CTL
);
1897 iowrite32(0x00F00000, bridge
->base
+ VSI6_CTL
);
1898 iowrite32(0x00F00000, bridge
->base
+ VSI7_CTL
);
1900 vme_unregister_bridge(ca91cx42_bridge
);
1902 ca91cx42_crcsr_exit(ca91cx42_bridge
, pdev
);
1904 /* resources are stored in link list */
1905 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->lm_resources
) {
1906 lm
= list_entry(pos
, struct vme_lm_resource
, list
);
1911 /* resources are stored in link list */
1912 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->dma_resources
) {
1913 dma_ctrlr
= list_entry(pos
, struct vme_dma_resource
, list
);
1918 /* resources are stored in link list */
1919 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->slave_resources
) {
1920 slave_image
= list_entry(pos
, struct vme_slave_resource
, list
);
1925 /* resources are stored in link list */
1926 list_for_each_safe(pos
, n
, &ca91cx42_bridge
->master_resources
) {
1927 master_image
= list_entry(pos
, struct vme_master_resource
,
1930 kfree(master_image
);
1933 ca91cx42_irq_exit(bridge
, pdev
);
1935 iounmap(bridge
->base
);
1937 pci_release_regions(pdev
);
1939 pci_disable_device(pdev
);
1941 kfree(ca91cx42_bridge
);
1944 module_pci_driver(ca91cx42_driver
);
1946 MODULE_PARM_DESC(geoid
, "Override geographical addressing");
1947 module_param(geoid
, int, 0);
1949 MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1950 MODULE_LICENSE("GPL");