2 * Freescale DMA ALSA SoC PCM driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
12 * This driver implements ASoC support for the Elo DMA controller, which is
13 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
14 * the PCM driver is what handles the DMA buffer.
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/delay.h>
23 #include <linux/gfp.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_platform.h>
27 #include <linux/list.h>
28 #include <linux/slab.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
38 #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */
41 * The formats that the DMA controller supports, which is anything
42 * that is 8, 16, or 32 bits.
44 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
45 SNDRV_PCM_FMTBIT_U8 | \
46 SNDRV_PCM_FMTBIT_S16_LE | \
47 SNDRV_PCM_FMTBIT_S16_BE | \
48 SNDRV_PCM_FMTBIT_U16_LE | \
49 SNDRV_PCM_FMTBIT_U16_BE | \
50 SNDRV_PCM_FMTBIT_S24_LE | \
51 SNDRV_PCM_FMTBIT_S24_BE | \
52 SNDRV_PCM_FMTBIT_U24_LE | \
53 SNDRV_PCM_FMTBIT_U24_BE | \
54 SNDRV_PCM_FMTBIT_S32_LE | \
55 SNDRV_PCM_FMTBIT_S32_BE | \
56 SNDRV_PCM_FMTBIT_U32_LE | \
57 SNDRV_PCM_FMTBIT_U32_BE)
59 struct snd_soc_platform_driver dai
;
60 dma_addr_t ssi_stx_phys
;
61 dma_addr_t ssi_srx_phys
;
62 unsigned int ssi_fifo_depth
;
63 struct ccsr_dma_channel __iomem
*channel
;
70 * The number of DMA links to use. Two is the bare minimum, but if you
71 * have really small links you might need more.
73 #define NUM_DMA_LINKS 2
75 /** fsl_dma_private: p-substream DMA data
77 * Each substream has a 1-to-1 association with a DMA channel.
79 * The link[] array is first because it needs to be aligned on a 32-byte
80 * boundary, so putting it first will ensure alignment without padding the
83 * @link[]: array of link descriptors
84 * @dma_channel: pointer to the DMA channel's registers
85 * @irq: IRQ for this DMA channel
86 * @substream: pointer to the substream object, needed by the ISR
87 * @ssi_sxx_phys: bus address of the STX or SRX register to use
88 * @ld_buf_phys: physical address of the LD buffer
89 * @current_link: index into link[] of the link currently being processed
90 * @dma_buf_phys: physical address of the DMA buffer
91 * @dma_buf_next: physical address of the next period to process
92 * @dma_buf_end: physical address of the byte after the end of the DMA
93 * @buffer period_size: the size of a single period
94 * @num_periods: the number of periods in the DMA buffer
96 struct fsl_dma_private
{
97 struct fsl_dma_link_descriptor link
[NUM_DMA_LINKS
];
98 struct ccsr_dma_channel __iomem
*dma_channel
;
100 struct snd_pcm_substream
*substream
;
101 dma_addr_t ssi_sxx_phys
;
102 unsigned int ssi_fifo_depth
;
103 dma_addr_t ld_buf_phys
;
104 unsigned int current_link
;
105 dma_addr_t dma_buf_phys
;
106 dma_addr_t dma_buf_next
;
107 dma_addr_t dma_buf_end
;
109 unsigned int num_periods
;
113 * fsl_dma_hardare: define characteristics of the PCM hardware.
115 * The PCM hardware is the Freescale DMA controller. This structure defines
116 * the capabilities of that hardware.
118 * Since the sampling rate and data format are not controlled by the DMA
119 * controller, we specify no limits for those values. The only exception is
120 * period_bytes_min, which is set to a reasonably low value to prevent the
121 * DMA controller from generating too many interrupts per second.
123 * Since each link descriptor has a 32-bit byte count field, we set
124 * period_bytes_max to the largest 32-bit number. We also have no maximum
127 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a
128 * limitation in the SSI driver requires the sample rates for playback and
129 * capture to be the same.
131 static const struct snd_pcm_hardware fsl_dma_hardware
= {
133 .info
= SNDRV_PCM_INFO_INTERLEAVED
|
134 SNDRV_PCM_INFO_MMAP
|
135 SNDRV_PCM_INFO_MMAP_VALID
|
136 SNDRV_PCM_INFO_JOINT_DUPLEX
|
137 SNDRV_PCM_INFO_PAUSE
,
138 .formats
= FSLDMA_PCM_FORMATS
,
139 .period_bytes_min
= 512, /* A reasonable limit */
140 .period_bytes_max
= (u32
) -1,
141 .periods_min
= NUM_DMA_LINKS
,
142 .periods_max
= (unsigned int) -1,
143 .buffer_bytes_max
= 128 * 1024, /* A reasonable limit */
147 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted
149 * This function should be called by the ISR whenever the DMA controller
150 * halts data transfer.
152 static void fsl_dma_abort_stream(struct snd_pcm_substream
*substream
)
156 snd_pcm_stream_lock_irqsave(substream
, flags
);
158 if (snd_pcm_running(substream
))
159 snd_pcm_stop(substream
, SNDRV_PCM_STATE_XRUN
);
161 snd_pcm_stream_unlock_irqrestore(substream
, flags
);
165 * fsl_dma_update_pointers - update LD pointers to point to the next period
167 * As each period is completed, this function changes the the link
168 * descriptor pointers for that period to point to the next period.
170 static void fsl_dma_update_pointers(struct fsl_dma_private
*dma_private
)
172 struct fsl_dma_link_descriptor
*link
=
173 &dma_private
->link
[dma_private
->current_link
];
175 /* Update our link descriptors to point to the next period. On a 36-bit
176 * system, we also need to update the ESAD bits. We also set (keep) the
177 * snoop bits. See the comments in fsl_dma_hw_params() about snooping.
179 if (dma_private
->substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
180 link
->source_addr
= cpu_to_be32(dma_private
->dma_buf_next
);
181 #ifdef CONFIG_PHYS_64BIT
182 link
->source_attr
= cpu_to_be32(CCSR_DMA_ATR_SNOOP
|
183 upper_32_bits(dma_private
->dma_buf_next
));
186 link
->dest_addr
= cpu_to_be32(dma_private
->dma_buf_next
);
187 #ifdef CONFIG_PHYS_64BIT
188 link
->dest_attr
= cpu_to_be32(CCSR_DMA_ATR_SNOOP
|
189 upper_32_bits(dma_private
->dma_buf_next
));
193 /* Update our variables for next time */
194 dma_private
->dma_buf_next
+= dma_private
->period_size
;
196 if (dma_private
->dma_buf_next
>= dma_private
->dma_buf_end
)
197 dma_private
->dma_buf_next
= dma_private
->dma_buf_phys
;
199 if (++dma_private
->current_link
>= NUM_DMA_LINKS
)
200 dma_private
->current_link
= 0;
204 * fsl_dma_isr: interrupt handler for the DMA controller
206 * @irq: IRQ of the DMA channel
207 * @dev_id: pointer to the dma_private structure for this DMA channel
209 static irqreturn_t
fsl_dma_isr(int irq
, void *dev_id
)
211 struct fsl_dma_private
*dma_private
= dev_id
;
212 struct snd_pcm_substream
*substream
= dma_private
->substream
;
213 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
214 struct device
*dev
= rtd
->platform
->dev
;
215 struct ccsr_dma_channel __iomem
*dma_channel
= dma_private
->dma_channel
;
216 irqreturn_t ret
= IRQ_NONE
;
219 /* We got an interrupt, so read the status register to see what we
220 were interrupted for.
222 sr
= in_be32(&dma_channel
->sr
);
224 if (sr
& CCSR_DMA_SR_TE
) {
225 dev_err(dev
, "dma transmit error\n");
226 fsl_dma_abort_stream(substream
);
227 sr2
|= CCSR_DMA_SR_TE
;
231 if (sr
& CCSR_DMA_SR_CH
)
234 if (sr
& CCSR_DMA_SR_PE
) {
235 dev_err(dev
, "dma programming error\n");
236 fsl_dma_abort_stream(substream
);
237 sr2
|= CCSR_DMA_SR_PE
;
241 if (sr
& CCSR_DMA_SR_EOLNI
) {
242 sr2
|= CCSR_DMA_SR_EOLNI
;
246 if (sr
& CCSR_DMA_SR_CB
)
249 if (sr
& CCSR_DMA_SR_EOSI
) {
250 /* Tell ALSA we completed a period. */
251 snd_pcm_period_elapsed(substream
);
254 * Update our link descriptors to point to the next period. We
255 * only need to do this if the number of periods is not equal to
256 * the number of links.
258 if (dma_private
->num_periods
!= NUM_DMA_LINKS
)
259 fsl_dma_update_pointers(dma_private
);
261 sr2
|= CCSR_DMA_SR_EOSI
;
265 if (sr
& CCSR_DMA_SR_EOLSI
) {
266 sr2
|= CCSR_DMA_SR_EOLSI
;
270 /* Clear the bits that we set */
272 out_be32(&dma_channel
->sr
, sr2
);
278 * fsl_dma_new: initialize this PCM driver.
280 * This function is called when the codec driver calls snd_soc_new_pcms(),
281 * once for each .dai_link in the machine driver's snd_soc_card
284 * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which
285 * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM
286 * is specified. Therefore, any DMA buffers we allocate will always be in low
287 * memory, but we support for 36-bit physical addresses anyway.
289 * Regardless of where the memory is actually allocated, since the device can
290 * technically DMA to any 36-bit address, we do need to set the DMA mask to 36.
292 static int fsl_dma_new(struct snd_soc_pcm_runtime
*rtd
)
294 struct snd_card
*card
= rtd
->card
->snd_card
;
295 struct snd_pcm
*pcm
= rtd
->pcm
;
298 ret
= dma_coerce_mask_and_coherent(card
->dev
, DMA_BIT_MASK(36));
302 /* Some codecs have separate DAIs for playback and capture, so we
303 * should allocate a DMA buffer only for the streams that are valid.
306 if (pcm
->streams
[SNDRV_PCM_STREAM_PLAYBACK
].substream
) {
307 ret
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, card
->dev
,
308 fsl_dma_hardware
.buffer_bytes_max
,
309 &pcm
->streams
[SNDRV_PCM_STREAM_PLAYBACK
].substream
->dma_buffer
);
311 dev_err(card
->dev
, "can't alloc playback dma buffer\n");
316 if (pcm
->streams
[SNDRV_PCM_STREAM_CAPTURE
].substream
) {
317 ret
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, card
->dev
,
318 fsl_dma_hardware
.buffer_bytes_max
,
319 &pcm
->streams
[SNDRV_PCM_STREAM_CAPTURE
].substream
->dma_buffer
);
321 dev_err(card
->dev
, "can't alloc capture dma buffer\n");
322 snd_dma_free_pages(&pcm
->streams
[SNDRV_PCM_STREAM_PLAYBACK
].substream
->dma_buffer
);
331 * fsl_dma_open: open a new substream.
333 * Each substream has its own DMA buffer.
335 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link
336 * descriptors that ping-pong from one period to the next. For example, if
337 * there are six periods and two link descriptors, this is how they look
338 * before playback starts:
340 * The last link descriptor
341 * ____________ points back to the first
350 * _________________________________________
351 * | | | | | | | The DMA buffer is
352 * | | | | | | | divided into 6 parts
353 * |______|______|______|______|______|______|
355 * and here's how they look after the first period is finished playing:
367 * _________________________________________
370 * |______|______|______|______|______|______|
372 * The first link descriptor now points to the third period. The DMA
373 * controller is currently playing the second period. When it finishes, it
374 * will jump back to the first descriptor and play the third period.
376 * There are four reasons we do this:
378 * 1. The only way to get the DMA controller to automatically restart the
379 * transfer when it gets to the end of the buffer is to use chaining
380 * mode. Basic direct mode doesn't offer that feature.
381 * 2. We need to receive an interrupt at the end of every period. The DMA
382 * controller can generate an interrupt at the end of every link transfer
383 * (aka segment). Making each period into a DMA segment will give us the
384 * interrupts we need.
385 * 3. By creating only two link descriptors, regardless of the number of
386 * periods, we do not need to reallocate the link descriptors if the
387 * number of periods changes.
388 * 4. All of the audio data is still stored in a single, contiguous DMA
389 * buffer, which is what ALSA expects. We're just dividing it into
390 * contiguous parts, and creating a link descriptor for each one.
392 static int fsl_dma_open(struct snd_pcm_substream
*substream
)
394 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
395 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
396 struct device
*dev
= rtd
->platform
->dev
;
397 struct dma_object
*dma
=
398 container_of(rtd
->platform
->driver
, struct dma_object
, dai
);
399 struct fsl_dma_private
*dma_private
;
400 struct ccsr_dma_channel __iomem
*dma_channel
;
401 dma_addr_t ld_buf_phys
;
402 u64 temp_link
; /* Pointer to next link descriptor */
404 unsigned int channel
;
409 * Reject any DMA buffer whose size is not a multiple of the period
410 * size. We need to make sure that the DMA buffer can be evenly divided
413 ret
= snd_pcm_hw_constraint_integer(runtime
,
414 SNDRV_PCM_HW_PARAM_PERIODS
);
416 dev_err(dev
, "invalid buffer size\n");
420 channel
= substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
? 0 : 1;
423 dev_err(dev
, "dma channel already assigned\n");
427 dma_private
= dma_alloc_coherent(dev
, sizeof(struct fsl_dma_private
),
428 &ld_buf_phys
, GFP_KERNEL
);
430 dev_err(dev
, "can't allocate dma private data\n");
433 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
434 dma_private
->ssi_sxx_phys
= dma
->ssi_stx_phys
;
436 dma_private
->ssi_sxx_phys
= dma
->ssi_srx_phys
;
438 dma_private
->ssi_fifo_depth
= dma
->ssi_fifo_depth
;
439 dma_private
->dma_channel
= dma
->channel
;
440 dma_private
->irq
= dma
->irq
;
441 dma_private
->substream
= substream
;
442 dma_private
->ld_buf_phys
= ld_buf_phys
;
443 dma_private
->dma_buf_phys
= substream
->dma_buffer
.addr
;
445 ret
= request_irq(dma_private
->irq
, fsl_dma_isr
, 0, "fsldma-audio",
448 dev_err(dev
, "can't register ISR for IRQ %u (ret=%i)\n",
449 dma_private
->irq
, ret
);
450 dma_free_coherent(dev
, sizeof(struct fsl_dma_private
),
451 dma_private
, dma_private
->ld_buf_phys
);
457 snd_pcm_set_runtime_buffer(substream
, &substream
->dma_buffer
);
458 snd_soc_set_runtime_hwparams(substream
, &fsl_dma_hardware
);
459 runtime
->private_data
= dma_private
;
461 /* Program the fixed DMA controller parameters */
463 dma_channel
= dma_private
->dma_channel
;
465 temp_link
= dma_private
->ld_buf_phys
+
466 sizeof(struct fsl_dma_link_descriptor
);
468 for (i
= 0; i
< NUM_DMA_LINKS
; i
++) {
469 dma_private
->link
[i
].next
= cpu_to_be64(temp_link
);
471 temp_link
+= sizeof(struct fsl_dma_link_descriptor
);
473 /* The last link descriptor points to the first */
474 dma_private
->link
[i
- 1].next
= cpu_to_be64(dma_private
->ld_buf_phys
);
476 /* Tell the DMA controller where the first link descriptor is */
477 out_be32(&dma_channel
->clndar
,
478 CCSR_DMA_CLNDAR_ADDR(dma_private
->ld_buf_phys
));
479 out_be32(&dma_channel
->eclndar
,
480 CCSR_DMA_ECLNDAR_ADDR(dma_private
->ld_buf_phys
));
482 /* The manual says the BCR must be clear before enabling EMP */
483 out_be32(&dma_channel
->bcr
, 0);
486 * Program the mode register for interrupts, external master control,
487 * and source/destination hold. Also clear the Channel Abort bit.
489 mr
= in_be32(&dma_channel
->mr
) &
490 ~(CCSR_DMA_MR_CA
| CCSR_DMA_MR_DAHE
| CCSR_DMA_MR_SAHE
);
493 * We want External Master Start and External Master Pause enabled,
494 * because the SSI is controlling the DMA controller. We want the DMA
495 * controller to be set up in advance, and then we signal only the SSI
496 * to start transferring.
498 * We want End-Of-Segment Interrupts enabled, because this will generate
499 * an interrupt at the end of each segment (each link descriptor
500 * represents one segment). Each DMA segment is the same thing as an
501 * ALSA period, so this is how we get an interrupt at the end of every
504 * We want Error Interrupt enabled, so that we can get an error if
505 * the DMA controller is mis-programmed somehow.
507 mr
|= CCSR_DMA_MR_EOSIE
| CCSR_DMA_MR_EIE
| CCSR_DMA_MR_EMP_EN
|
510 /* For playback, we want the destination address to be held. For
511 capture, set the source address to be held. */
512 mr
|= (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) ?
513 CCSR_DMA_MR_DAHE
: CCSR_DMA_MR_SAHE
;
515 out_be32(&dma_channel
->mr
, mr
);
521 * fsl_dma_hw_params: continue initializing the DMA links
523 * This function obtains hardware parameters about the opened stream and
524 * programs the DMA controller accordingly.
526 * One drawback of big-endian is that when copying integers of different
527 * sizes to a fixed-sized register, the address to which the integer must be
528 * copied is dependent on the size of the integer.
530 * For example, if P is the address of a 32-bit register, and X is a 32-bit
531 * integer, then X should be copied to address P. However, if X is a 16-bit
532 * integer, then it should be copied to P+2. If X is an 8-bit register,
533 * then it should be copied to P+3.
535 * So for playback of 8-bit samples, the DMA controller must transfer single
536 * bytes from the DMA buffer to the last byte of the STX0 register, i.e.
537 * offset by 3 bytes. For 16-bit samples, the offset is two bytes.
539 * For 24-bit samples, the offset is 1 byte. However, the DMA controller
540 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4,
541 * and 8 bytes at a time). So we do not support packed 24-bit samples.
542 * 24-bit data must be padded to 32 bits.
544 static int fsl_dma_hw_params(struct snd_pcm_substream
*substream
,
545 struct snd_pcm_hw_params
*hw_params
)
547 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
548 struct fsl_dma_private
*dma_private
= runtime
->private_data
;
549 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
550 struct device
*dev
= rtd
->platform
->dev
;
552 /* Number of bits per sample */
553 unsigned int sample_bits
=
554 snd_pcm_format_physical_width(params_format(hw_params
));
556 /* Number of bytes per frame */
557 unsigned int sample_bytes
= sample_bits
/ 8;
559 /* Bus address of SSI STX register */
560 dma_addr_t ssi_sxx_phys
= dma_private
->ssi_sxx_phys
;
562 /* Size of the DMA buffer, in bytes */
563 size_t buffer_size
= params_buffer_bytes(hw_params
);
565 /* Number of bytes per period */
566 size_t period_size
= params_period_bytes(hw_params
);
568 /* Pointer to next period */
569 dma_addr_t temp_addr
= substream
->dma_buffer
.addr
;
571 /* Pointer to DMA controller */
572 struct ccsr_dma_channel __iomem
*dma_channel
= dma_private
->dma_channel
;
574 u32 mr
; /* DMA Mode Register */
578 /* Initialize our DMA tracking variables */
579 dma_private
->period_size
= period_size
;
580 dma_private
->num_periods
= params_periods(hw_params
);
581 dma_private
->dma_buf_end
= dma_private
->dma_buf_phys
+ buffer_size
;
582 dma_private
->dma_buf_next
= dma_private
->dma_buf_phys
+
583 (NUM_DMA_LINKS
* period_size
);
585 if (dma_private
->dma_buf_next
>= dma_private
->dma_buf_end
)
586 /* This happens if the number of periods == NUM_DMA_LINKS */
587 dma_private
->dma_buf_next
= dma_private
->dma_buf_phys
;
589 mr
= in_be32(&dma_channel
->mr
) & ~(CCSR_DMA_MR_BWC_MASK
|
590 CCSR_DMA_MR_SAHTS_MASK
| CCSR_DMA_MR_DAHTS_MASK
);
592 /* Due to a quirk of the SSI's STX register, the target address
593 * for the DMA operations depends on the sample size. So we calculate
594 * that offset here. While we're at it, also tell the DMA controller
595 * how much data to transfer per sample.
597 switch (sample_bits
) {
599 mr
|= CCSR_DMA_MR_DAHTS_1
| CCSR_DMA_MR_SAHTS_1
;
603 mr
|= CCSR_DMA_MR_DAHTS_2
| CCSR_DMA_MR_SAHTS_2
;
607 mr
|= CCSR_DMA_MR_DAHTS_4
| CCSR_DMA_MR_SAHTS_4
;
610 /* We should never get here */
611 dev_err(dev
, "unsupported sample size %u\n", sample_bits
);
616 * BWC determines how many bytes are sent/received before the DMA
617 * controller checks the SSI to see if it needs to stop. BWC should
618 * always be a multiple of the frame size, so that we always transmit
619 * whole frames. Each frame occupies two slots in the FIFO. The
620 * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two
621 * (MR[BWC] can only represent even powers of two).
623 * To simplify the process, we set BWC to the largest value that is
624 * less than or equal to the FIFO watermark. For playback, this ensures
625 * that we transfer the maximum amount without overrunning the FIFO.
626 * For capture, this ensures that we transfer the maximum amount without
627 * underrunning the FIFO.
630 * w = SSI watermark value (which equals f - 2)
631 * b = DMA bandwidth count (in bytes)
632 * s = sample size (in bytes, which equals frame_size * 2)
634 * For playback, we never transmit more than the transmit FIFO
635 * watermark, otherwise we might write more data than the FIFO can hold.
636 * The watermark is equal to the FIFO depth minus two.
638 * For capture, two equations must hold:
642 * So, b > 2 * s, but b must also be <= s * w. To simplify, we set
643 * b = s * w, which is equal to
644 * (dma_private->ssi_fifo_depth - 2) * sample_bytes.
646 mr
|= CCSR_DMA_MR_BWC((dma_private
->ssi_fifo_depth
- 2) * sample_bytes
);
648 out_be32(&dma_channel
->mr
, mr
);
650 for (i
= 0; i
< NUM_DMA_LINKS
; i
++) {
651 struct fsl_dma_link_descriptor
*link
= &dma_private
->link
[i
];
653 link
->count
= cpu_to_be32(period_size
);
655 /* The snoop bit tells the DMA controller whether it should tell
656 * the ECM to snoop during a read or write to an address. For
657 * audio, we use DMA to transfer data between memory and an I/O
658 * device (the SSI's STX0 or SRX0 register). Snooping is only
659 * needed if there is a cache, so we need to snoop memory
660 * addresses only. For playback, that means we snoop the source
661 * but not the destination. For capture, we snoop the
662 * destination but not the source.
664 * Note that failing to snoop properly is unlikely to cause
665 * cache incoherency if the period size is larger than the
666 * size of L1 cache. This is because filling in one period will
667 * flush out the data for the previous period. So if you
668 * increased period_bytes_min to a large enough size, you might
669 * get more performance by not snooping, and you'll still be
670 * okay. You'll need to update fsl_dma_update_pointers() also.
672 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
673 link
->source_addr
= cpu_to_be32(temp_addr
);
674 link
->source_attr
= cpu_to_be32(CCSR_DMA_ATR_SNOOP
|
675 upper_32_bits(temp_addr
));
677 link
->dest_addr
= cpu_to_be32(ssi_sxx_phys
);
678 link
->dest_attr
= cpu_to_be32(CCSR_DMA_ATR_NOSNOOP
|
679 upper_32_bits(ssi_sxx_phys
));
681 link
->source_addr
= cpu_to_be32(ssi_sxx_phys
);
682 link
->source_attr
= cpu_to_be32(CCSR_DMA_ATR_NOSNOOP
|
683 upper_32_bits(ssi_sxx_phys
));
685 link
->dest_addr
= cpu_to_be32(temp_addr
);
686 link
->dest_attr
= cpu_to_be32(CCSR_DMA_ATR_SNOOP
|
687 upper_32_bits(temp_addr
));
690 temp_addr
+= period_size
;
697 * fsl_dma_pointer: determine the current position of the DMA transfer
699 * This function is called by ALSA when ALSA wants to know where in the
700 * stream buffer the hardware currently is.
702 * For playback, the SAR register contains the physical address of the most
703 * recent DMA transfer. For capture, the value is in the DAR register.
705 * The base address of the buffer is stored in the source_addr field of the
706 * first link descriptor.
708 static snd_pcm_uframes_t
fsl_dma_pointer(struct snd_pcm_substream
*substream
)
710 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
711 struct fsl_dma_private
*dma_private
= runtime
->private_data
;
712 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
713 struct device
*dev
= rtd
->platform
->dev
;
714 struct ccsr_dma_channel __iomem
*dma_channel
= dma_private
->dma_channel
;
716 snd_pcm_uframes_t frames
;
718 /* Obtain the current DMA pointer, but don't read the ESAD bits if we
719 * only have 32-bit DMA addresses. This function is typically called
720 * in interrupt context, so we need to optimize it.
722 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
723 position
= in_be32(&dma_channel
->sar
);
724 #ifdef CONFIG_PHYS_64BIT
725 position
|= (u64
)(in_be32(&dma_channel
->satr
) &
726 CCSR_DMA_ATR_ESAD_MASK
) << 32;
729 position
= in_be32(&dma_channel
->dar
);
730 #ifdef CONFIG_PHYS_64BIT
731 position
|= (u64
)(in_be32(&dma_channel
->datr
) &
732 CCSR_DMA_ATR_ESAD_MASK
) << 32;
737 * When capture is started, the SSI immediately starts to fill its FIFO.
738 * This means that the DMA controller is not started until the FIFO is
739 * full. However, ALSA calls this function before that happens, when
740 * MR.DAR is still zero. In this case, just return zero to indicate
741 * that nothing has been received yet.
746 if ((position
< dma_private
->dma_buf_phys
) ||
747 (position
> dma_private
->dma_buf_end
)) {
748 dev_err(dev
, "dma pointer is out of range, halting stream\n");
749 return SNDRV_PCM_POS_XRUN
;
752 frames
= bytes_to_frames(runtime
, position
- dma_private
->dma_buf_phys
);
755 * If the current address is just past the end of the buffer, wrap it
758 if (frames
== runtime
->buffer_size
)
765 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params()
767 * Release the resources allocated in fsl_dma_hw_params() and de-program the
770 * This function can be called multiple times.
772 static int fsl_dma_hw_free(struct snd_pcm_substream
*substream
)
774 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
775 struct fsl_dma_private
*dma_private
= runtime
->private_data
;
778 struct ccsr_dma_channel __iomem
*dma_channel
;
780 dma_channel
= dma_private
->dma_channel
;
783 out_be32(&dma_channel
->mr
, CCSR_DMA_MR_CA
);
784 out_be32(&dma_channel
->mr
, 0);
786 /* Reset all the other registers */
787 out_be32(&dma_channel
->sr
, -1);
788 out_be32(&dma_channel
->clndar
, 0);
789 out_be32(&dma_channel
->eclndar
, 0);
790 out_be32(&dma_channel
->satr
, 0);
791 out_be32(&dma_channel
->sar
, 0);
792 out_be32(&dma_channel
->datr
, 0);
793 out_be32(&dma_channel
->dar
, 0);
794 out_be32(&dma_channel
->bcr
, 0);
795 out_be32(&dma_channel
->nlndar
, 0);
796 out_be32(&dma_channel
->enlndar
, 0);
803 * fsl_dma_close: close the stream.
805 static int fsl_dma_close(struct snd_pcm_substream
*substream
)
807 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
808 struct fsl_dma_private
*dma_private
= runtime
->private_data
;
809 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
810 struct device
*dev
= rtd
->platform
->dev
;
811 struct dma_object
*dma
=
812 container_of(rtd
->platform
->driver
, struct dma_object
, dai
);
815 if (dma_private
->irq
)
816 free_irq(dma_private
->irq
, dma_private
);
818 /* Deallocate the fsl_dma_private structure */
819 dma_free_coherent(dev
, sizeof(struct fsl_dma_private
),
820 dma_private
, dma_private
->ld_buf_phys
);
821 substream
->runtime
->private_data
= NULL
;
830 * Remove this PCM driver.
832 static void fsl_dma_free_dma_buffers(struct snd_pcm
*pcm
)
834 struct snd_pcm_substream
*substream
;
837 for (i
= 0; i
< ARRAY_SIZE(pcm
->streams
); i
++) {
838 substream
= pcm
->streams
[i
].substream
;
840 snd_dma_free_pages(&substream
->dma_buffer
);
841 substream
->dma_buffer
.area
= NULL
;
842 substream
->dma_buffer
.addr
= 0;
848 * find_ssi_node -- returns the SSI node that points to its DMA channel node
850 * Although this DMA driver attempts to operate independently of the other
851 * devices, it still needs to determine some information about the SSI device
852 * that it's working with. Unfortunately, the device tree does not contain
853 * a pointer from the DMA channel node to the SSI node -- the pointer goes the
854 * other way. So we need to scan the device tree for SSI nodes until we find
855 * the one that points to the given DMA channel node. It's ugly, but at least
856 * it's contained in this one function.
858 static struct device_node
*find_ssi_node(struct device_node
*dma_channel_np
)
860 struct device_node
*ssi_np
, *np
;
862 for_each_compatible_node(ssi_np
, NULL
, "fsl,mpc8610-ssi") {
863 /* Check each DMA phandle to see if it points to us. We
864 * assume that device_node pointers are a valid comparison.
866 np
= of_parse_phandle(ssi_np
, "fsl,playback-dma", 0);
868 if (np
== dma_channel_np
)
871 np
= of_parse_phandle(ssi_np
, "fsl,capture-dma", 0);
873 if (np
== dma_channel_np
)
880 static struct snd_pcm_ops fsl_dma_ops
= {
881 .open
= fsl_dma_open
,
882 .close
= fsl_dma_close
,
883 .ioctl
= snd_pcm_lib_ioctl
,
884 .hw_params
= fsl_dma_hw_params
,
885 .hw_free
= fsl_dma_hw_free
,
886 .pointer
= fsl_dma_pointer
,
889 static int fsl_soc_dma_probe(struct platform_device
*pdev
)
891 struct dma_object
*dma
;
892 struct device_node
*np
= pdev
->dev
.of_node
;
893 struct device_node
*ssi_np
;
895 const uint32_t *iprop
;
898 /* Find the SSI node that points to us. */
899 ssi_np
= find_ssi_node(np
);
901 dev_err(&pdev
->dev
, "cannot find parent SSI node\n");
905 ret
= of_address_to_resource(ssi_np
, 0, &res
);
907 dev_err(&pdev
->dev
, "could not determine resources for %s\n",
913 dma
= kzalloc(sizeof(*dma
) + strlen(np
->full_name
), GFP_KERNEL
);
915 dev_err(&pdev
->dev
, "could not allocate dma object\n");
920 strcpy(dma
->path
, np
->full_name
);
921 dma
->dai
.ops
= &fsl_dma_ops
;
922 dma
->dai
.pcm_new
= fsl_dma_new
;
923 dma
->dai
.pcm_free
= fsl_dma_free_dma_buffers
;
925 /* Store the SSI-specific information that we need */
926 dma
->ssi_stx_phys
= res
.start
+ offsetof(struct ccsr_ssi
, stx0
);
927 dma
->ssi_srx_phys
= res
.start
+ offsetof(struct ccsr_ssi
, srx0
);
929 iprop
= of_get_property(ssi_np
, "fsl,fifo-depth", NULL
);
931 dma
->ssi_fifo_depth
= be32_to_cpup(iprop
);
933 /* Older 8610 DTs didn't have the fifo-depth property */
934 dma
->ssi_fifo_depth
= 8;
938 ret
= snd_soc_register_platform(&pdev
->dev
, &dma
->dai
);
940 dev_err(&pdev
->dev
, "could not register platform\n");
945 dma
->channel
= of_iomap(np
, 0);
946 dma
->irq
= irq_of_parse_and_map(np
, 0);
948 dev_set_drvdata(&pdev
->dev
, dma
);
953 static int fsl_soc_dma_remove(struct platform_device
*pdev
)
955 struct dma_object
*dma
= dev_get_drvdata(&pdev
->dev
);
957 snd_soc_unregister_platform(&pdev
->dev
);
958 iounmap(dma
->channel
);
959 irq_dispose_mapping(dma
->irq
);
965 static const struct of_device_id fsl_soc_dma_ids
[] = {
966 { .compatible
= "fsl,ssi-dma-channel", },
969 MODULE_DEVICE_TABLE(of
, fsl_soc_dma_ids
);
971 static struct platform_driver fsl_soc_dma_driver
= {
973 .name
= "fsl-pcm-audio",
974 .owner
= THIS_MODULE
,
975 .of_match_table
= fsl_soc_dma_ids
,
977 .probe
= fsl_soc_dma_probe
,
978 .remove
= fsl_soc_dma_remove
,
981 module_platform_driver(fsl_soc_dma_driver
);
983 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
984 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver");
985 MODULE_LICENSE("GPL v2");