| blob | a36ff61321ce39ff10e136425e12a125deb8e085 |
1 # SPDX-License-Identifier: GPL-2.0-only
2 config ARM64
3 def_bool y
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_CLOCKSOURCE_DATA
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_COHERENT_TO_PFN
16 select ARCH_HAS_DMA_MMAP_PGPROT
17 select ARCH_HAS_DMA_PREP_COHERENT
18 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
19 select ARCH_HAS_ELF_RANDOMIZE
20 select ARCH_HAS_FAST_MULTIPLIER
21 select ARCH_HAS_FORTIFY_SOURCE
22 select ARCH_HAS_GCOV_PROFILE_ALL
23 select ARCH_HAS_GIGANTIC_PAGE
24 select ARCH_HAS_KCOV
25 select ARCH_HAS_KEEPINITRD
26 select ARCH_HAS_MEMBARRIER_SYNC_CORE
27 select ARCH_HAS_PTE_SPECIAL
28 select ARCH_HAS_SETUP_DMA_OPS
29 select ARCH_HAS_SET_DIRECT_MAP
30 select ARCH_HAS_SET_MEMORY
31 select ARCH_HAS_STRICT_KERNEL_RWX
32 select ARCH_HAS_STRICT_MODULE_RWX
33 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
34 select ARCH_HAS_SYNC_DMA_FOR_CPU
35 select ARCH_HAS_SYSCALL_WRAPPER
36 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
37 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
38 select ARCH_HAVE_NMI_SAFE_CMPXCHG
39 select ARCH_INLINE_READ_LOCK if !PREEMPT
40 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
41 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
42 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
43 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
45 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
46 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
47 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
49 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
50 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
51 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
53 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
54 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
55 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
56 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
57 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
59 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
60 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
61 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
63 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
64 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
65 select ARCH_KEEP_MEMBLOCK
66 select ARCH_USE_CMPXCHG_LOCKREF
67 select ARCH_USE_QUEUED_RWLOCKS
68 select ARCH_USE_QUEUED_SPINLOCKS
69 select ARCH_SUPPORTS_MEMORY_FAILURE
70 select ARCH_SUPPORTS_ATOMIC_RMW
71 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
72 select ARCH_SUPPORTS_NUMA_BALANCING
73 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
74 select ARCH_WANT_FRAME_POINTERS
75 select ARCH_HAS_UBSAN_SANITIZE_ALL
76 select ARM_AMBA
77 select ARM_ARCH_TIMER
78 select ARM_GIC
79 select AUDIT_ARCH_COMPAT_GENERIC
80 select ARM_GIC_V2M if PCI
81 select ARM_GIC_V3
82 select ARM_GIC_V3_ITS if PCI
83 select ARM_PSCI_FW
84 select BUILDTIME_EXTABLE_SORT
85 select CLONE_BACKWARDS
86 select COMMON_CLK
87 select CPU_PM if (SUSPEND || CPU_IDLE)
88 select CRC32
89 select DCACHE_WORD_ACCESS
90 select DMA_DIRECT_REMAP
91 select EDAC_SUPPORT
92 select FRAME_POINTER
93 select GENERIC_ALLOCATOR
94 select GENERIC_ARCH_TOPOLOGY
95 select GENERIC_CLOCKEVENTS
96 select GENERIC_CLOCKEVENTS_BROADCAST
97 select GENERIC_CPU_AUTOPROBE
98 select GENERIC_CPU_VULNERABILITIES
99 select GENERIC_EARLY_IOREMAP
100 select GENERIC_IDLE_POLL_SETUP
101 select GENERIC_IRQ_MULTI_HANDLER
102 select GENERIC_IRQ_PROBE
103 select GENERIC_IRQ_SHOW
104 select GENERIC_IRQ_SHOW_LEVEL
105 select GENERIC_PCI_IOMAP
106 select GENERIC_SCHED_CLOCK
107 select GENERIC_SMP_IDLE_THREAD
108 select GENERIC_STRNCPY_FROM_USER
109 select GENERIC_STRNLEN_USER
110 select GENERIC_TIME_VSYSCALL
111 select GENERIC_GETTIMEOFDAY
112 select GENERIC_COMPAT_VDSO if (!CPU_BIG_ENDIAN && COMPAT)
113 select HANDLE_DOMAIN_IRQ
114 select HARDIRQS_SW_RESEND
115 select HAVE_PCI
116 select HAVE_ACPI_APEI if (ACPI && EFI)
117 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
118 select HAVE_ARCH_AUDITSYSCALL
119 select HAVE_ARCH_BITREVERSE
120 select HAVE_ARCH_HUGE_VMAP
121 select HAVE_ARCH_JUMP_LABEL
122 select HAVE_ARCH_JUMP_LABEL_RELATIVE
123 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
124 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
125 select HAVE_ARCH_KGDB
126 select HAVE_ARCH_MMAP_RND_BITS
127 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
128 select HAVE_ARCH_PREL32_RELOCATIONS
129 select HAVE_ARCH_SECCOMP_FILTER
130 select HAVE_ARCH_STACKLEAK
131 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
132 select HAVE_ARCH_TRACEHOOK
133 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
134 select HAVE_ARCH_VMAP_STACK
135 select HAVE_ARM_SMCCC
136 select HAVE_EBPF_JIT
137 select HAVE_C_RECORDMCOUNT
138 select HAVE_CMPXCHG_DOUBLE
139 select HAVE_CMPXCHG_LOCAL
140 select HAVE_CONTEXT_TRACKING
141 select HAVE_DEBUG_BUGVERBOSE
142 select HAVE_DEBUG_KMEMLEAK
143 select HAVE_DMA_CONTIGUOUS
144 select HAVE_DYNAMIC_FTRACE
145 select HAVE_EFFICIENT_UNALIGNED_ACCESS
146 select HAVE_FAST_GUP
147 select HAVE_FTRACE_MCOUNT_RECORD
148 select HAVE_FUNCTION_TRACER
149 select HAVE_FUNCTION_GRAPH_TRACER
150 select HAVE_GCC_PLUGINS
151 select HAVE_HW_BREAKPOINT if PERF_EVENTS
152 select HAVE_IRQ_TIME_ACCOUNTING
153 select HAVE_MEMBLOCK_NODE_MAP if NUMA
154 select HAVE_NMI
155 select HAVE_PATA_PLATFORM
156 select HAVE_PERF_EVENTS
157 select HAVE_PERF_REGS
158 select HAVE_PERF_USER_STACK_DUMP
159 select HAVE_REGS_AND_STACK_ACCESS_API
160 select HAVE_FUNCTION_ARG_ACCESS_API
161 select HAVE_RCU_TABLE_FREE
162 select HAVE_RSEQ
163 select HAVE_STACKPROTECTOR
164 select HAVE_SYSCALL_TRACEPOINTS
165 select HAVE_KPROBES
166 select HAVE_KRETPROBES
167 select HAVE_GENERIC_VDSO
168 select IOMMU_DMA if IOMMU_SUPPORT
169 select IRQ_DOMAIN
170 select IRQ_FORCED_THREADING
171 select MODULES_USE_ELF_RELA
172 select NEED_DMA_MAP_STATE
173 select NEED_SG_DMA_LENGTH
174 select OF
175 select OF_EARLY_FLATTREE
176 select PCI_DOMAINS_GENERIC if PCI
177 select PCI_ECAM if (ACPI && PCI)
178 select PCI_SYSCALL if PCI
179 select POWER_RESET
180 select POWER_SUPPLY
181 select REFCOUNT_FULL
182 select SPARSE_IRQ
183 select SWIOTLB
184 select SYSCTL_EXCEPTION_TRACE
185 select THREAD_INFO_IN_TASK
186 help
187 ARM 64-bit (AArch64) Linux support.
189 config 64BIT
190 def_bool y
192 config MMU
193 def_bool y
195 config ARM64_PAGE_SHIFT
196 int
197 default 16 if ARM64_64K_PAGES
198 default 14 if ARM64_16K_PAGES
199 default 12
201 config ARM64_CONT_SHIFT
202 int
203 default 5 if ARM64_64K_PAGES
204 default 7 if ARM64_16K_PAGES
205 default 4
207 config ARCH_MMAP_RND_BITS_MIN
208 default 14 if ARM64_64K_PAGES
209 default 16 if ARM64_16K_PAGES
210 default 18
212 # max bits determined by the following formula:
213 # VA_BITS - PAGE_SHIFT - 3
214 config ARCH_MMAP_RND_BITS_MAX
215 default 19 if ARM64_VA_BITS=36
216 default 24 if ARM64_VA_BITS=39
217 default 27 if ARM64_VA_BITS=42
218 default 30 if ARM64_VA_BITS=47
219 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
220 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
221 default 33 if ARM64_VA_BITS=48
222 default 14 if ARM64_64K_PAGES
223 default 16 if ARM64_16K_PAGES
224 default 18
226 config ARCH_MMAP_RND_COMPAT_BITS_MIN
227 default 7 if ARM64_64K_PAGES
228 default 9 if ARM64_16K_PAGES
229 default 11
231 config ARCH_MMAP_RND_COMPAT_BITS_MAX
232 default 16
234 config NO_IOPORT_MAP
235 def_bool y if !PCI
237 config STACKTRACE_SUPPORT
238 def_bool y
240 config ILLEGAL_POINTER_VALUE
241 hex
242 default 0xdead000000000000
244 config LOCKDEP_SUPPORT
245 def_bool y
247 config TRACE_IRQFLAGS_SUPPORT
248 def_bool y
250 config GENERIC_BUG
251 def_bool y
252 depends on BUG
254 config GENERIC_BUG_RELATIVE_POINTERS
255 def_bool y
256 depends on GENERIC_BUG
258 config GENERIC_HWEIGHT
259 def_bool y
261 config GENERIC_CSUM
262 def_bool y
264 config GENERIC_CALIBRATE_DELAY
265 def_bool y
267 config ZONE_DMA32
268 bool "Support DMA32 zone" if EXPERT
269 default y
271 config ARCH_ENABLE_MEMORY_HOTPLUG
272 def_bool y
274 config SMP
275 def_bool y
277 config KERNEL_MODE_NEON
278 def_bool y
280 config FIX_EARLYCON_MEM
281 def_bool y
283 config PGTABLE_LEVELS
284 int
285 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
286 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
287 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52)
288 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
289 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
290 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
292 config ARCH_SUPPORTS_UPROBES
293 def_bool y
295 config ARCH_PROC_KCORE_TEXT
296 def_bool y
298 source "arch/arm64/Kconfig.platforms"
300 menu "Kernel Features"
302 menu "ARM errata workarounds via the alternatives framework"
304 config ARM64_WORKAROUND_CLEAN_CACHE
305 bool
307 config ARM64_ERRATUM_826319
308 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
309 default y
310 select ARM64_WORKAROUND_CLEAN_CACHE
311 help
312 This option adds an alternative code sequence to work around ARM
313 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
314 AXI master interface and an L2 cache.
316 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
317 and is unable to accept a certain write via this interface, it will
318 not progress on read data presented on the read data channel and the
319 system can deadlock.
321 The workaround promotes data cache clean instructions to
322 data cache clean-and-invalidate.
323 Please note that this does not necessarily enable the workaround,
324 as it depends on the alternative framework, which will only patch
325 the kernel if an affected CPU is detected.
327 If unsure, say Y.
329 config ARM64_ERRATUM_827319
330 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
331 default y
332 select ARM64_WORKAROUND_CLEAN_CACHE
333 help
334 This option adds an alternative code sequence to work around ARM
335 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
336 master interface and an L2 cache.
338 Under certain conditions this erratum can cause a clean line eviction
339 to occur at the same time as another transaction to the same address
340 on the AMBA 5 CHI interface, which can cause data corruption if the
341 interconnect reorders the two transactions.
343 The workaround promotes data cache clean instructions to
344 data cache clean-and-invalidate.
345 Please note that this does not necessarily enable the workaround,
346 as it depends on the alternative framework, which will only patch
347 the kernel if an affected CPU is detected.
349 If unsure, say Y.
351 config ARM64_ERRATUM_824069
352 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
353 default y
354 select ARM64_WORKAROUND_CLEAN_CACHE
355 help
356 This option adds an alternative code sequence to work around ARM
357 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
358 to a coherent interconnect.
360 If a Cortex-A53 processor is executing a store or prefetch for
361 write instruction at the same time as a processor in another
362 cluster is executing a cache maintenance operation to the same
363 address, then this erratum might cause a clean cache line to be
364 incorrectly marked as dirty.
366 The workaround promotes data cache clean instructions to
367 data cache clean-and-invalidate.
368 Please note that this option does not necessarily enable the
369 workaround, as it depends on the alternative framework, which will
370 only patch the kernel if an affected CPU is detected.
372 If unsure, say Y.
374 config ARM64_ERRATUM_819472
375 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
376 default y
377 select ARM64_WORKAROUND_CLEAN_CACHE
378 help
379 This option adds an alternative code sequence to work around ARM
380 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
381 present when it is connected to a coherent interconnect.
383 If the processor is executing a load and store exclusive sequence at
384 the same time as a processor in another cluster is executing a cache
385 maintenance operation to the same address, then this erratum might
386 cause data corruption.
388 The workaround promotes data cache clean instructions to
389 data cache clean-and-invalidate.
390 Please note that this does not necessarily enable the workaround,
391 as it depends on the alternative framework, which will only patch
392 the kernel if an affected CPU is detected.
394 If unsure, say Y.
396 config ARM64_ERRATUM_832075
397 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
398 default y
399 help
400 This option adds an alternative code sequence to work around ARM
401 erratum 832075 on Cortex-A57 parts up to r1p2.
403 Affected Cortex-A57 parts might deadlock when exclusive load/store
404 instructions to Write-Back memory are mixed with Device loads.
406 The workaround is to promote device loads to use Load-Acquire
407 semantics.
408 Please note that this does not necessarily enable the workaround,
409 as it depends on the alternative framework, which will only patch
410 the kernel if an affected CPU is detected.
412 If unsure, say Y.
414 config ARM64_ERRATUM_834220
415 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
416 depends on KVM
417 default y
418 help
419 This option adds an alternative code sequence to work around ARM
420 erratum 834220 on Cortex-A57 parts up to r1p2.
422 Affected Cortex-A57 parts might report a Stage 2 translation
423 fault as the result of a Stage 1 fault for load crossing a
424 page boundary when there is a permission or device memory
425 alignment fault at Stage 1 and a translation fault at Stage 2.
427 The workaround is to verify that the Stage 1 translation
428 doesn't generate a fault before handling the Stage 2 fault.
429 Please note that this does not necessarily enable the workaround,
430 as it depends on the alternative framework, which will only patch
431 the kernel if an affected CPU is detected.
433 If unsure, say Y.
435 config ARM64_ERRATUM_845719
436 bool "Cortex-A53: 845719: a load might read incorrect data"
437 depends on COMPAT
438 default y
439 help
440 This option adds an alternative code sequence to work around ARM
441 erratum 845719 on Cortex-A53 parts up to r0p4.
443 When running a compat (AArch32) userspace on an affected Cortex-A53
444 part, a load at EL0 from a virtual address that matches the bottom 32
445 bits of the virtual address used by a recent load at (AArch64) EL1
446 might return incorrect data.
448 The workaround is to write the contextidr_el1 register on exception
449 return to a 32-bit task.
450 Please note that this does not necessarily enable the workaround,
451 as it depends on the alternative framework, which will only patch
452 the kernel if an affected CPU is detected.
454 If unsure, say Y.
456 config ARM64_ERRATUM_843419
457 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
458 default y
459 select ARM64_MODULE_PLTS if MODULES
460 help
461 This option links the kernel with '--fix-cortex-a53-843419' and
462 enables PLT support to replace certain ADRP instructions, which can
463 cause subsequent memory accesses to use an incorrect address on
464 Cortex-A53 parts up to r0p4.
466 If unsure, say Y.
468 config ARM64_ERRATUM_1024718
469 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
470 default y
471 help
472 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
474 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
475 update of the hardware dirty bit when the DBM/AP bits are updated
476 without a break-before-make. The workaround is to disable the usage
477 of hardware DBM locally on the affected cores. CPUs not affected by
478 this erratum will continue to use the feature.
480 If unsure, say Y.
482 config ARM64_ERRATUM_1418040
483 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
484 default y
485 depends on COMPAT
486 help
487 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
488 errata 1188873 and 1418040.
490 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
491 cause register corruption when accessing the timer registers
492 from AArch32 userspace.
494 If unsure, say Y.
496 config ARM64_ERRATUM_1165522
497 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
498 default y
499 help
500 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
502 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
503 corrupted TLBs by speculating an AT instruction during a guest
504 context switch.
506 If unsure, say Y.
508 config ARM64_ERRATUM_1286807
509 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
510 default y
511 select ARM64_WORKAROUND_REPEAT_TLBI
512 help
513 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
515 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
516 address for a cacheable mapping of a location is being
517 accessed by a core while another core is remapping the virtual
518 address to a new physical page using the recommended
519 break-before-make sequence, then under very rare circumstances
520 TLBI+DSB completes before a read using the translation being
521 invalidated has been observed by other observers. The
522 workaround repeats the TLBI+DSB operation.
524 If unsure, say Y.
526 config ARM64_ERRATUM_1463225
527 bool "Cortex-A76: Software Step might prevent interrupt recognition"
528 default y
529 help
530 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
532 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
533 of a system call instruction (SVC) can prevent recognition of
534 subsequent interrupts when software stepping is disabled in the
535 exception handler of the system call and either kernel debugging
536 is enabled or VHE is in use.
538 Work around the erratum by triggering a dummy step exception
539 when handling a system call from a task that is being stepped
540 in a VHE configuration of the kernel.
542 If unsure, say Y.
544 config CAVIUM_ERRATUM_22375
545 bool "Cavium erratum 22375, 24313"
546 default y
547 help
548 Enable workaround for errata 22375 and 24313.
550 This implements two gicv3-its errata workarounds for ThunderX. Both
551 with a small impact affecting only ITS table allocation.
553 erratum 22375: only alloc 8MB table size
554 erratum 24313: ignore memory access type
556 The fixes are in ITS initialization and basically ignore memory access
557 type and table size provided by the TYPER and BASER registers.
559 If unsure, say Y.
561 config CAVIUM_ERRATUM_23144
562 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
563 depends on NUMA
564 default y
565 help
566 ITS SYNC command hang for cross node io and collections/cpu mapping.
568 If unsure, say Y.
570 config CAVIUM_ERRATUM_23154
571 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
572 default y
573 help
574 The gicv3 of ThunderX requires a modified version for
575 reading the IAR status to ensure data synchronization
576 (access to icc_iar1_el1 is not sync'ed before and after).
578 If unsure, say Y.
580 config CAVIUM_ERRATUM_27456
581 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
582 default y
583 help
584 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
585 instructions may cause the icache to become corrupted if it
586 contains data for a non-current ASID. The fix is to
587 invalidate the icache when changing the mm context.
589 If unsure, say Y.
591 config CAVIUM_ERRATUM_30115
592 bool "Cavium erratum 30115: Guest may disable interrupts in host"
593 default y
594 help
595 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
596 1.2, and T83 Pass 1.0, KVM guest execution may disable
597 interrupts in host. Trapping both GICv3 group-0 and group-1
598 accesses sidesteps the issue.
600 If unsure, say Y.
602 config QCOM_FALKOR_ERRATUM_1003
603 bool "Falkor E1003: Incorrect translation due to ASID change"
604 default y
605 help
606 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
607 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
608 in TTBR1_EL1, this situation only occurs in the entry trampoline and
609 then only for entries in the walk cache, since the leaf translation
610 is unchanged. Work around the erratum by invalidating the walk cache
611 entries for the trampoline before entering the kernel proper.
613 config ARM64_WORKAROUND_REPEAT_TLBI
614 bool
616 config QCOM_FALKOR_ERRATUM_1009
617 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
618 default y
619 select ARM64_WORKAROUND_REPEAT_TLBI
620 help
621 On Falkor v1, the CPU may prematurely complete a DSB following a
622 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
623 one more time to fix the issue.
625 If unsure, say Y.
627 config QCOM_QDF2400_ERRATUM_0065
628 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
629 default y
630 help
631 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
632 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
633 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
635 If unsure, say Y.
637 config SOCIONEXT_SYNQUACER_PREITS
638 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
639 default y
640 help
641 Socionext Synquacer SoCs implement a separate h/w block to generate
642 MSI doorbell writes with non-zero values for the device ID.
644 If unsure, say Y.
646 config HISILICON_ERRATUM_161600802
647 bool "Hip07 161600802: Erroneous redistributor VLPI base"
648 default y
649 help
650 The HiSilicon Hip07 SoC uses the wrong redistributor base
651 when issued ITS commands such as VMOVP and VMAPP, and requires
652 a 128kB offset to be applied to the target address in this commands.
654 If unsure, say Y.
656 config QCOM_FALKOR_ERRATUM_E1041
657 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
658 default y
659 help
660 Falkor CPU may speculatively fetch instructions from an improper
661 memory location when MMU translation is changed from SCTLR_ELn[M]=1
662 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
664 If unsure, say Y.
666 config FUJITSU_ERRATUM_010001
667 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
668 default y
669 help
670 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
671 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
672 accesses may cause undefined fault (Data abort, DFSC=0b111111).
673 This fault occurs under a specific hardware condition when a
674 load/store instruction performs an address translation using:
675 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
676 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
677 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
678 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
680 The workaround is to ensure these bits are clear in TCR_ELx.
681 The workaround only affects the Fujitsu-A64FX.
683 If unsure, say Y.
685 endmenu
688 choice
689 prompt "Page size"
690 default ARM64_4K_PAGES
691 help
692 Page size (translation granule) configuration.
694 config ARM64_4K_PAGES
695 bool "4KB"
696 help
697 This feature enables 4KB pages support.
699 config ARM64_16K_PAGES
700 bool "16KB"
701 help
702 The system will use 16KB pages support. AArch32 emulation
703 requires applications compiled with 16K (or a multiple of 16K)
704 aligned segments.
706 config ARM64_64K_PAGES
707 bool "64KB"
708 help
709 This feature enables 64KB pages support (4KB by default)
710 allowing only two levels of page tables and faster TLB
711 look-up. AArch32 emulation requires applications compiled
712 with 64K aligned segments.
714 endchoice
716 choice
717 prompt "Virtual address space size"
718 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
719 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
720 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
721 help
722 Allows choosing one of multiple possible virtual address
723 space sizes. The level of translation table is determined by
724 a combination of page size and virtual address space size.
726 config ARM64_VA_BITS_36
727 bool "36-bit" if EXPERT
728 depends on ARM64_16K_PAGES
730 config ARM64_VA_BITS_39
731 bool "39-bit"
732 depends on ARM64_4K_PAGES
734 config ARM64_VA_BITS_42
735 bool "42-bit"
736 depends on ARM64_64K_PAGES
738 config ARM64_VA_BITS_47
739 bool "47-bit"
740 depends on ARM64_16K_PAGES
742 config ARM64_VA_BITS_48
743 bool "48-bit"
745 config ARM64_USER_VA_BITS_52
746 bool "52-bit (user)"
747 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
748 help
749 Enable 52-bit virtual addressing for userspace when explicitly
750 requested via a hint to mmap(). The kernel will continue to
751 use 48-bit virtual addresses for its own mappings.
753 NOTE: Enabling 52-bit virtual addressing in conjunction with
754 ARMv8.3 Pointer Authentication will result in the PAC being
755 reduced from 7 bits to 3 bits, which may have a significant
756 impact on its susceptibility to brute-force attacks.
758 If unsure, select 48-bit virtual addressing instead.
760 endchoice
762 config ARM64_FORCE_52BIT
763 bool "Force 52-bit virtual addresses for userspace"
764 depends on ARM64_USER_VA_BITS_52 && EXPERT
765 help
766 For systems with 52-bit userspace VAs enabled, the kernel will attempt
767 to maintain compatibility with older software by providing 48-bit VAs
768 unless a hint is supplied to mmap.
770 This configuration option disables the 48-bit compatibility logic, and
771 forces all userspace addresses to be 52-bit on HW that supports it. One
772 should only enable this configuration option for stress testing userspace
773 memory management code. If unsure say N here.
775 config ARM64_VA_BITS
776 int
777 default 36 if ARM64_VA_BITS_36
778 default 39 if ARM64_VA_BITS_39
779 default 42 if ARM64_VA_BITS_42
780 default 47 if ARM64_VA_BITS_47
781 default 48 if ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52
783 choice
784 prompt "Physical address space size"
785 default ARM64_PA_BITS_48
786 help
787 Choose the maximum physical address range that the kernel will
788 support.
790 config ARM64_PA_BITS_48
791 bool "48-bit"
793 config ARM64_PA_BITS_52
794 bool "52-bit (ARMv8.2)"
795 depends on ARM64_64K_PAGES
796 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
797 help
798 Enable support for a 52-bit physical address space, introduced as
799 part of the ARMv8.2-LPA extension.
801 With this enabled, the kernel will also continue to work on CPUs that
802 do not support ARMv8.2-LPA, but with some added memory overhead (and
803 minor performance overhead).
805 endchoice
807 config ARM64_PA_BITS
808 int
809 default 48 if ARM64_PA_BITS_48
810 default 52 if ARM64_PA_BITS_52
812 config CPU_BIG_ENDIAN
813 bool "Build big-endian kernel"
814 help
815 Say Y if you plan on running a kernel in big-endian mode.
817 config SCHED_MC
818 bool "Multi-core scheduler support"
819 help
820 Multi-core scheduler support improves the CPU scheduler's decision
821 making when dealing with multi-core CPU chips at a cost of slightly
822 increased overhead in some places. If unsure say N here.
824 config SCHED_SMT
825 bool "SMT scheduler support"
826 help
827 Improves the CPU scheduler's decision making when dealing with
828 MultiThreading at a cost of slightly increased overhead in some
829 places. If unsure say N here.
831 config NR_CPUS
832 int "Maximum number of CPUs (2-4096)"
833 range 2 4096
834 default "256"
836 config HOTPLUG_CPU
837 bool "Support for hot-pluggable CPUs"
838 select GENERIC_IRQ_MIGRATION
839 help
840 Say Y here to experiment with turning CPUs off and on. CPUs
841 can be controlled through /sys/devices/system/cpu.
843 # Common NUMA Features
844 config NUMA
845 bool "Numa Memory Allocation and Scheduler Support"
846 select ACPI_NUMA if ACPI
847 select OF_NUMA
848 help
849 Enable NUMA (Non Uniform Memory Access) support.
851 The kernel will try to allocate memory used by a CPU on the
852 local memory of the CPU and add some more
853 NUMA awareness to the kernel.
855 config NODES_SHIFT
856 int "Maximum NUMA Nodes (as a power of 2)"
857 range 1 10
858 default "2"
859 depends on NEED_MULTIPLE_NODES
860 help
861 Specify the maximum number of NUMA Nodes available on the target
862 system. Increases memory reserved to accommodate various tables.
864 config USE_PERCPU_NUMA_NODE_ID
865 def_bool y
866 depends on NUMA
868 config HAVE_SETUP_PER_CPU_AREA
869 def_bool y
870 depends on NUMA
872 config NEED_PER_CPU_EMBED_FIRST_CHUNK
873 def_bool y
874 depends on NUMA
876 config HOLES_IN_ZONE
877 def_bool y
879 source "kernel/Kconfig.hz"
881 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
882 def_bool y
884 config ARCH_SPARSEMEM_ENABLE
885 def_bool y
886 select SPARSEMEM_VMEMMAP_ENABLE
888 config ARCH_SPARSEMEM_DEFAULT
889 def_bool ARCH_SPARSEMEM_ENABLE
891 config ARCH_SELECT_MEMORY_MODEL
892 def_bool ARCH_SPARSEMEM_ENABLE
894 config ARCH_FLATMEM_ENABLE
895 def_bool !NUMA
897 config HAVE_ARCH_PFN_VALID
898 def_bool y
900 config HW_PERF_EVENTS
901 def_bool y
902 depends on ARM_PMU
904 config SYS_SUPPORTS_HUGETLBFS
905 def_bool y
907 config ARCH_WANT_HUGE_PMD_SHARE
908 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
910 config ARCH_HAS_CACHE_LINE_SIZE
911 def_bool y
913 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
914 def_bool y if PGTABLE_LEVELS > 2
916 config SECCOMP
917 bool "Enable seccomp to safely compute untrusted bytecode"
918 ---help---
919 This kernel feature is useful for number crunching applications
920 that may need to compute untrusted bytecode during their
921 execution. By using pipes or other transports made available to
922 the process as file descriptors supporting the read/write
923 syscalls, it's possible to isolate those applications in
924 their own address space using seccomp. Once seccomp is
925 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
926 and the task is only allowed to execute a few safe syscalls
927 defined by each seccomp mode.
929 config PARAVIRT
930 bool "Enable paravirtualization code"
931 help
932 This changes the kernel so it can modify itself when it is run
933 under a hypervisor, potentially improving performance significantly
934 over full virtualization.
936 config PARAVIRT_TIME_ACCOUNTING
937 bool "Paravirtual steal time accounting"
938 select PARAVIRT
939 help
940 Select this option to enable fine granularity task steal time
941 accounting. Time spent executing other tasks in parallel with
942 the current vCPU is discounted from the vCPU power. To account for
943 that, there can be a small performance impact.
945 If in doubt, say N here.
947 config KEXEC
948 depends on PM_SLEEP_SMP
949 select KEXEC_CORE
950 bool "kexec system call"
951 ---help---
952 kexec is a system call that implements the ability to shutdown your
953 current kernel, and to start another kernel. It is like a reboot
954 but it is independent of the system firmware. And like a reboot
955 you can start any kernel with it, not just Linux.
957 config KEXEC_FILE
958 bool "kexec file based system call"
959 select KEXEC_CORE
960 help
961 This is new version of kexec system call. This system call is
962 file based and takes file descriptors as system call argument
963 for kernel and initramfs as opposed to list of segments as
964 accepted by previous system call.
966 config KEXEC_VERIFY_SIG
967 bool "Verify kernel signature during kexec_file_load() syscall"
968 depends on KEXEC_FILE
969 help
970 Select this option to verify a signature with loaded kernel
971 image. If configured, any attempt of loading a image without
972 valid signature will fail.
974 In addition to that option, you need to enable signature
975 verification for the corresponding kernel image type being
976 loaded in order for this to work.
978 config KEXEC_IMAGE_VERIFY_SIG
979 bool "Enable Image signature verification support"
980 default y
981 depends on KEXEC_VERIFY_SIG
982 depends on EFI && SIGNED_PE_FILE_VERIFICATION
983 help
984 Enable Image signature verification support.
986 comment "Support for PE file signature verification disabled"
987 depends on KEXEC_VERIFY_SIG
988 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
990 config CRASH_DUMP
991 bool "Build kdump crash kernel"
992 help
993 Generate crash dump after being started by kexec. This should
994 be normally only set in special crash dump kernels which are
995 loaded in the main kernel with kexec-tools into a specially
996 reserved region and then later executed after a crash by
997 kdump/kexec.
999 For more details see Documentation/kdump/kdump.rst
1001 config XEN_DOM0
1002 def_bool y
1003 depends on XEN
1005 config XEN
1006 bool "Xen guest support on ARM64"
1007 depends on ARM64 && OF
1008 select SWIOTLB_XEN
1009 select PARAVIRT
1010 help
1011 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1013 config FORCE_MAX_ZONEORDER
1014 int
1015 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1016 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1017 default "11"
1018 help
1019 The kernel memory allocator divides physically contiguous memory
1020 blocks into "zones", where each zone is a power of two number of
1021 pages. This option selects the largest power of two that the kernel
1022 keeps in the memory allocator. If you need to allocate very large
1023 blocks of physically contiguous memory, then you may need to
1024 increase this value.
1026 This config option is actually maximum order plus one. For example,
1027 a value of 11 means that the largest free memory block is 2^10 pages.
1029 We make sure that we can allocate upto a HugePage size for each configuration.
1030 Hence we have :
1031 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1033 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1034 4M allocations matching the default size used by generic code.
1036 config UNMAP_KERNEL_AT_EL0
1037 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1038 default y
1039 help
1040 Speculation attacks against some high-performance processors can
1041 be used to bypass MMU permission checks and leak kernel data to
1042 userspace. This can be defended against by unmapping the kernel
1043 when running in userspace, mapping it back in on exception entry
1044 via a trampoline page in the vector table.
1046 If unsure, say Y.
1048 config HARDEN_BRANCH_PREDICTOR
1049 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1050 default y
1051 help
1052 Speculation attacks against some high-performance processors rely on
1053 being able to manipulate the branch predictor for a victim context by
1054 executing aliasing branches in the attacker context. Such attacks
1055 can be partially mitigated against by clearing internal branch
1056 predictor state and limiting the prediction logic in some situations.
1058 This config option will take CPU-specific actions to harden the
1059 branch predictor against aliasing attacks and may rely on specific
1060 instruction sequences or control bits being set by the system
1061 firmware.
1063 If unsure, say Y.
1065 config HARDEN_EL2_VECTORS
1066 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1067 default y
1068 help
1069 Speculation attacks against some high-performance processors can
1070 be used to leak privileged information such as the vector base
1071 register, resulting in a potential defeat of the EL2 layout
1072 randomization.
1074 This config option will map the vectors to a fixed location,
1075 independent of the EL2 code mapping, so that revealing VBAR_EL2
1076 to an attacker does not give away any extra information. This
1077 only gets enabled on affected CPUs.
1079 If unsure, say Y.
1081 config ARM64_SSBD
1082 bool "Speculative Store Bypass Disable" if EXPERT
1083 default y
1084 help
1085 This enables mitigation of the bypassing of previous stores
1086 by speculative loads.
1088 If unsure, say Y.
1090 config RODATA_FULL_DEFAULT_ENABLED
1091 bool "Apply r/o permissions of VM areas also to their linear aliases"
1092 default y
1093 help
1094 Apply read-only attributes of VM areas to the linear alias of
1095 the backing pages as well. This prevents code or read-only data
1096 from being modified (inadvertently or intentionally) via another
1097 mapping of the same memory page. This additional enhancement can
1098 be turned off at runtime by passing rodata=[off|on] (and turned on
1099 with rodata=full if this option is set to 'n')
1101 This requires the linear region to be mapped down to pages,
1102 which may adversely affect performance in some cases.
1104 config ARM64_SW_TTBR0_PAN
1105 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1106 help
1107 Enabling this option prevents the kernel from accessing
1108 user-space memory directly by pointing TTBR0_EL1 to a reserved
1109 zeroed area and reserved ASID. The user access routines
1110 restore the valid TTBR0_EL1 temporarily.
1112 menuconfig COMPAT
1113 bool "Kernel support for 32-bit EL0"
1114 depends on ARM64_4K_PAGES || EXPERT
1115 select COMPAT_BINFMT_ELF if BINFMT_ELF
1116 select HAVE_UID16
1117 select OLD_SIGSUSPEND3
1118 select COMPAT_OLD_SIGACTION
1119 help
1120 This option enables support for a 32-bit EL0 running under a 64-bit
1121 kernel at EL1. AArch32-specific components such as system calls,
1122 the user helper functions, VFP support and the ptrace interface are
1123 handled appropriately by the kernel.
1125 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1126 that you will only be able to execute AArch32 binaries that were compiled
1127 with page size aligned segments.
1129 If you want to execute 32-bit userspace applications, say Y.
1131 if COMPAT
1133 config KUSER_HELPERS
1134 bool "Enable kuser helpers page for 32 bit applications"
1135 default y
1136 help
1137 Warning: disabling this option may break 32-bit user programs.
1139 Provide kuser helpers to compat tasks. The kernel provides
1140 helper code to userspace in read only form at a fixed location
1141 to allow userspace to be independent of the CPU type fitted to
1142 the system. This permits binaries to be run on ARMv4 through
1143 to ARMv8 without modification.
1145 See Documentation/arm/kernel_user_helpers.txt for details.
1147 However, the fixed address nature of these helpers can be used
1148 by ROP (return orientated programming) authors when creating
1149 exploits.
1151 If all of the binaries and libraries which run on your platform
1152 are built specifically for your platform, and make no use of
1153 these helpers, then you can turn this option off to hinder
1154 such exploits. However, in that case, if a binary or library
1155 relying on those helpers is run, it will not function correctly.
1157 Say N here only if you are absolutely certain that you do not
1158 need these helpers; otherwise, the safe option is to say Y.
1161 menuconfig ARMV8_DEPRECATED
1162 bool "Emulate deprecated/obsolete ARMv8 instructions"
1163 depends on SYSCTL
1164 help
1165 Legacy software support may require certain instructions
1166 that have been deprecated or obsoleted in the architecture.
1168 Enable this config to enable selective emulation of these
1169 features.
1171 If unsure, say Y
1173 if ARMV8_DEPRECATED
1175 config SWP_EMULATION
1176 bool "Emulate SWP/SWPB instructions"
1177 help
1178 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1179 they are always undefined. Say Y here to enable software
1180 emulation of these instructions for userspace using LDXR/STXR.
1182 In some older versions of glibc [<=2.8] SWP is used during futex
1183 trylock() operations with the assumption that the code will not
1184 be preempted. This invalid assumption may be more likely to fail
1185 with SWP emulation enabled, leading to deadlock of the user
1186 application.
1188 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1189 on an external transaction monitoring block called a global
1190 monitor to maintain update atomicity. If your system does not
1191 implement a global monitor, this option can cause programs that
1192 perform SWP operations to uncached memory to deadlock.
1194 If unsure, say Y
1196 config CP15_BARRIER_EMULATION
1197 bool "Emulate CP15 Barrier instructions"
1198 help
1199 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1200 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1201 strongly recommended to use the ISB, DSB, and DMB
1202 instructions instead.
1204 Say Y here to enable software emulation of these
1205 instructions for AArch32 userspace code. When this option is
1206 enabled, CP15 barrier usage is traced which can help
1207 identify software that needs updating.
1209 If unsure, say Y
1211 config SETEND_EMULATION
1212 bool "Emulate SETEND instruction"
1213 help
1214 The SETEND instruction alters the data-endianness of the
1215 AArch32 EL0, and is deprecated in ARMv8.
1217 Say Y here to enable software emulation of the instruction
1218 for AArch32 userspace code.
1220 Note: All the cpus on the system must have mixed endian support at EL0
1221 for this feature to be enabled. If a new CPU - which doesn't support mixed
1222 endian - is hotplugged in after this feature has been enabled, there could
1223 be unexpected results in the applications.
1225 If unsure, say Y
1226 endif
1228 endif
1230 menu "ARMv8.1 architectural features"
1232 config ARM64_HW_AFDBM
1233 bool "Support for hardware updates of the Access and Dirty page flags"
1234 default y
1235 help
1236 The ARMv8.1 architecture extensions introduce support for
1237 hardware updates of the access and dirty information in page
1238 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1239 capable processors, accesses to pages with PTE_AF cleared will
1240 set this bit instead of raising an access flag fault.
1241 Similarly, writes to read-only pages with the DBM bit set will
1242 clear the read-only bit (AP[2]) instead of raising a
1243 permission fault.
1245 Kernels built with this configuration option enabled continue
1246 to work on pre-ARMv8.1 hardware and the performance impact is
1247 minimal. If unsure, say Y.
1249 config ARM64_PAN
1250 bool "Enable support for Privileged Access Never (PAN)"
1251 default y
1252 help
1253 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1254 prevents the kernel or hypervisor from accessing user-space (EL0)
1255 memory directly.
1257 Choosing this option will cause any unprotected (not using
1258 copy_to_user et al) memory access to fail with a permission fault.
1260 The feature is detected at runtime, and will remain as a 'nop'
1261 instruction if the cpu does not implement the feature.
1263 config ARM64_LSE_ATOMICS
1264 bool "Atomic instructions"
1265 default y
1266 help
1267 As part of the Large System Extensions, ARMv8.1 introduces new
1268 atomic instructions that are designed specifically to scale in
1269 very large systems.
1271 Say Y here to make use of these instructions for the in-kernel
1272 atomic routines. This incurs a small overhead on CPUs that do
1273 not support these instructions and requires the kernel to be
1274 built with binutils >= 2.25 in order for the new instructions
1275 to be used.
1277 config ARM64_VHE
1278 bool "Enable support for Virtualization Host Extensions (VHE)"
1279 default y
1280 help
1281 Virtualization Host Extensions (VHE) allow the kernel to run
1282 directly at EL2 (instead of EL1) on processors that support
1283 it. This leads to better performance for KVM, as they reduce
1284 the cost of the world switch.
1286 Selecting this option allows the VHE feature to be detected
1287 at runtime, and does not affect processors that do not
1288 implement this feature.
1290 endmenu
1292 menu "ARMv8.2 architectural features"
1294 config ARM64_UAO
1295 bool "Enable support for User Access Override (UAO)"
1296 default y
1297 help
1298 User Access Override (UAO; part of the ARMv8.2 Extensions)
1299 causes the 'unprivileged' variant of the load/store instructions to
1300 be overridden to be privileged.
1302 This option changes get_user() and friends to use the 'unprivileged'
1303 variant of the load/store instructions. This ensures that user-space
1304 really did have access to the supplied memory. When addr_limit is
1305 set to kernel memory the UAO bit will be set, allowing privileged
1306 access to kernel memory.
1308 Choosing this option will cause copy_to_user() et al to use user-space
1309 memory permissions.
1311 The feature is detected at runtime, the kernel will use the
1312 regular load/store instructions if the cpu does not implement the
1313 feature.
1315 config ARM64_PMEM
1316 bool "Enable support for persistent memory"
1317 select ARCH_HAS_PMEM_API
1318 select ARCH_HAS_UACCESS_FLUSHCACHE
1319 help
1320 Say Y to enable support for the persistent memory API based on the
1321 ARMv8.2 DCPoP feature.
1323 The feature is detected at runtime, and the kernel will use DC CVAC
1324 operations if DC CVAP is not supported (following the behaviour of
1325 DC CVAP itself if the system does not define a point of persistence).
1327 config ARM64_RAS_EXTN
1328 bool "Enable support for RAS CPU Extensions"
1329 default y
1330 help
1331 CPUs that support the Reliability, Availability and Serviceability
1332 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1333 errors, classify them and report them to software.
1335 On CPUs with these extensions system software can use additional
1336 barriers to determine if faults are pending and read the
1337 classification from a new set of registers.
1339 Selecting this feature will allow the kernel to use these barriers
1340 and access the new registers if the system supports the extension.
1341 Platform RAS features may additionally depend on firmware support.
1343 config ARM64_CNP
1344 bool "Enable support for Common Not Private (CNP) translations"
1345 default y
1346 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1347 help
1348 Common Not Private (CNP) allows translation table entries to
1349 be shared between different PEs in the same inner shareable
1350 domain, so the hardware can use this fact to optimise the
1351 caching of such entries in the TLB.
1353 Selecting this option allows the CNP feature to be detected
1354 at runtime, and does not affect PEs that do not implement
1355 this feature.
1357 endmenu
1359 menu "ARMv8.3 architectural features"
1361 config ARM64_PTR_AUTH
1362 bool "Enable support for pointer authentication"
1363 default y
1364 depends on !KVM || ARM64_VHE
1365 help
1366 Pointer authentication (part of the ARMv8.3 Extensions) provides
1367 instructions for signing and authenticating pointers against secret
1368 keys, which can be used to mitigate Return Oriented Programming (ROP)
1369 and other attacks.
1371 This option enables these instructions at EL0 (i.e. for userspace).
1373 Choosing this option will cause the kernel to initialise secret keys
1374 for each process at exec() time, with these keys being
1375 context-switched along with the process.
1377 The feature is detected at runtime. If the feature is not present in
1378 hardware it will not be advertised to userspace/KVM guest nor will it
1379 be enabled. However, KVM guest also require VHE mode and hence
1380 CONFIG_ARM64_VHE=y option to use this feature.
1382 endmenu
1384 config ARM64_SVE
1385 bool "ARM Scalable Vector Extension support"
1386 default y
1387 depends on !KVM || ARM64_VHE
1388 help
1389 The Scalable Vector Extension (SVE) is an extension to the AArch64
1390 execution state which complements and extends the SIMD functionality
1391 of the base architecture to support much larger vectors and to enable
1392 additional vectorisation opportunities.
1394 To enable use of this extension on CPUs that implement it, say Y.
1396 On CPUs that support the SVE2 extensions, this option will enable
1397 those too.
1399 Note that for architectural reasons, firmware _must_ implement SVE
1400 support when running on SVE capable hardware. The required support
1401 is present in:
1403 * version 1.5 and later of the ARM Trusted Firmware
1404 * the AArch64 boot wrapper since commit 5e1261e08abf
1405 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1407 For other firmware implementations, consult the firmware documentation
1408 or vendor.
1410 If you need the kernel to boot on SVE-capable hardware with broken
1411 firmware, you may need to say N here until you get your firmware
1412 fixed. Otherwise, you may experience firmware panics or lockups when
1413 booting the kernel. If unsure and you are not observing these
1414 symptoms, you should assume that it is safe to say Y.
1416 CPUs that support SVE are architecturally required to support the
1417 Virtualization Host Extensions (VHE), so the kernel makes no
1418 provision for supporting SVE alongside KVM without VHE enabled.
1419 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1420 KVM in the same kernel image.
1422 config ARM64_MODULE_PLTS
1423 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1424 depends on MODULES
1425 select HAVE_MOD_ARCH_SPECIFIC
1426 help
1427 Allocate PLTs when loading modules so that jumps and calls whose
1428 targets are too far away for their relative offsets to be encoded
1429 in the instructions themselves can be bounced via veneers in the
1430 module's PLT. This allows modules to be allocated in the generic
1431 vmalloc area after the dedicated module memory area has been
1432 exhausted.
1434 When running with address space randomization (KASLR), the module
1435 region itself may be too far away for ordinary relative jumps and
1436 calls, and so in that case, module PLTs are required and cannot be
1437 disabled.
1439 Specific errata workaround(s) might also force module PLTs to be
1440 enabled (ARM64_ERRATUM_843419).
1442 config ARM64_PSEUDO_NMI
1443 bool "Support for NMI-like interrupts"
1444 select CONFIG_ARM_GIC_V3
1445 help
1446 Adds support for mimicking Non-Maskable Interrupts through the use of
1447 GIC interrupt priority. This support requires version 3 or later of
1448 ARM GIC.
1450 This high priority configuration for interrupts needs to be
1451 explicitly enabled by setting the kernel parameter
1452 "irqchip.gicv3_pseudo_nmi" to 1.
1454 If unsure, say N
1456 if ARM64_PSEUDO_NMI
1457 config ARM64_DEBUG_PRIORITY_MASKING
1458 bool "Debug interrupt priority masking"
1459 help
1460 This adds runtime checks to functions enabling/disabling
1461 interrupts when using priority masking. The additional checks verify
1462 the validity of ICC_PMR_EL1 when calling concerned functions.
1464 If unsure, say N
1465 endif
1467 config RELOCATABLE
1468 bool
1469 help
1470 This builds the kernel as a Position Independent Executable (PIE),
1471 which retains all relocation metadata required to relocate the
1472 kernel binary at runtime to a different virtual address than the
1473 address it was linked at.
1474 Since AArch64 uses the RELA relocation format, this requires a
1475 relocation pass at runtime even if the kernel is loaded at the
1476 same address it was linked at.
1478 config RANDOMIZE_BASE
1479 bool "Randomize the address of the kernel image"
1480 select ARM64_MODULE_PLTS if MODULES
1481 select RELOCATABLE
1482 help
1483 Randomizes the virtual address at which the kernel image is
1484 loaded, as a security feature that deters exploit attempts
1485 relying on knowledge of the location of kernel internals.
1487 It is the bootloader's job to provide entropy, by passing a
1488 random u64 value in /chosen/kaslr-seed at kernel entry.
1490 When booting via the UEFI stub, it will invoke the firmware's
1491 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1492 to the kernel proper. In addition, it will randomise the physical
1493 location of the kernel Image as well.
1495 If unsure, say N.
1497 config RANDOMIZE_MODULE_REGION_FULL
1498 bool "Randomize the module region over a 4 GB range"
1499 depends on RANDOMIZE_BASE
1500 default y
1501 help
1502 Randomizes the location of the module region inside a 4 GB window
1503 covering the core kernel. This way, it is less likely for modules
1504 to leak information about the location of core kernel data structures
1505 but it does imply that function calls between modules and the core
1506 kernel will need to be resolved via veneers in the module PLT.
1508 When this option is not set, the module region will be randomized over
1509 a limited range that contains the [_stext, _etext] interval of the
1510 core kernel, so branch relocations are always in range.
1512 config CC_HAVE_STACKPROTECTOR_SYSREG
1513 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1515 config STACKPROTECTOR_PER_TASK
1516 def_bool y
1517 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1519 endmenu
1521 menu "Boot options"
1523 config ARM64_ACPI_PARKING_PROTOCOL
1524 bool "Enable support for the ARM64 ACPI parking protocol"
1525 depends on ACPI
1526 help
1527 Enable support for the ARM64 ACPI parking protocol. If disabled
1528 the kernel will not allow booting through the ARM64 ACPI parking
1529 protocol even if the corresponding data is present in the ACPI
1530 MADT table.
1532 config CMDLINE
1533 string "Default kernel command string"
1534 default ""
1535 help
1536 Provide a set of default command-line options at build time by
1537 entering them here. As a minimum, you should specify the the
1538 root device (e.g. root=/dev/nfs).
1540 config CMDLINE_FORCE
1541 bool "Always use the default kernel command string"
1542 help
1543 Always use the default kernel command string, even if the boot
1544 loader passes other arguments to the kernel.
1545 This is useful if you cannot or don't want to change the
1546 command-line options your boot loader passes to the kernel.
1548 config EFI_STUB
1549 bool
1551 config EFI
1552 bool "UEFI runtime support"
1553 depends on OF && !CPU_BIG_ENDIAN
1554 depends on KERNEL_MODE_NEON
1555 select ARCH_SUPPORTS_ACPI
1556 select LIBFDT
1557 select UCS2_STRING
1558 select EFI_PARAMS_FROM_FDT
1559 select EFI_RUNTIME_WRAPPERS
1560 select EFI_STUB
1561 select EFI_ARMSTUB
1562 default y
1563 help
1564 This option provides support for runtime services provided
1565 by UEFI firmware (such as non-volatile variables, realtime
1566 clock, and platform reset). A UEFI stub is also provided to
1567 allow the kernel to be booted as an EFI application. This
1568 is only useful on systems that have UEFI firmware.
1570 config DMI
1571 bool "Enable support for SMBIOS (DMI) tables"
1572 depends on EFI
1573 default y
1574 help
1575 This enables SMBIOS/DMI feature for systems.
1577 This option is only useful on systems that have UEFI firmware.
1578 However, even with this option, the resultant kernel should
1579 continue to boot on existing non-UEFI platforms.
1581 endmenu
1583 config SYSVIPC_COMPAT
1584 def_bool y
1585 depends on COMPAT && SYSVIPC
1587 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1588 def_bool y
1589 depends on HUGETLB_PAGE && MIGRATION
1591 menu "Power management options"
1593 source "kernel/power/Kconfig"
1595 config ARCH_HIBERNATION_POSSIBLE
1596 def_bool y
1597 depends on CPU_PM
1599 config ARCH_HIBERNATION_HEADER
1600 def_bool y
1601 depends on HIBERNATION
1603 config ARCH_SUSPEND_POSSIBLE
1604 def_bool y
1606 endmenu
1608 menu "CPU Power Management"
1610 source "drivers/cpuidle/Kconfig"
1612 source "drivers/cpufreq/Kconfig"
1614 endmenu
1616 source "drivers/firmware/Kconfig"
1618 source "drivers/acpi/Kconfig"
1620 source "arch/arm64/kvm/Kconfig"
1622 if CRYPTO
1623 source "arch/arm64/crypto/Kconfig"
1624 endif