2 * the simple DMA Implementation for Blackfin
4 * Copyright 2007-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 #include <linux/module.h>
11 #include <asm/blackfin.h>
14 struct dma_register
* const dma_io_base_addr
[MAX_DMA_CHANNELS
] = {
15 (struct dma_register
*) DMA0_NEXT_DESC_PTR
,
16 (struct dma_register
*) DMA1_NEXT_DESC_PTR
,
17 (struct dma_register
*) DMA2_NEXT_DESC_PTR
,
18 (struct dma_register
*) DMA3_NEXT_DESC_PTR
,
19 (struct dma_register
*) DMA4_NEXT_DESC_PTR
,
20 (struct dma_register
*) DMA5_NEXT_DESC_PTR
,
21 (struct dma_register
*) DMA6_NEXT_DESC_PTR
,
22 (struct dma_register
*) DMA7_NEXT_DESC_PTR
,
23 (struct dma_register
*) DMA8_NEXT_DESC_PTR
,
24 (struct dma_register
*) DMA9_NEXT_DESC_PTR
,
25 (struct dma_register
*) DMA10_NEXT_DESC_PTR
,
26 (struct dma_register
*) DMA11_NEXT_DESC_PTR
,
27 (struct dma_register
*) DMA12_NEXT_DESC_PTR
,
28 (struct dma_register
*) DMA13_NEXT_DESC_PTR
,
29 (struct dma_register
*) DMA14_NEXT_DESC_PTR
,
30 (struct dma_register
*) DMA15_NEXT_DESC_PTR
,
31 (struct dma_register
*) DMA16_NEXT_DESC_PTR
,
32 (struct dma_register
*) DMA17_NEXT_DESC_PTR
,
33 (struct dma_register
*) DMA18_NEXT_DESC_PTR
,
34 (struct dma_register
*) DMA19_NEXT_DESC_PTR
,
35 (struct dma_register
*) DMA20_NEXT_DESC_PTR
,
36 (struct dma_register
*) DMA21_NEXT_DESC_PTR
,
37 (struct dma_register
*) DMA22_NEXT_DESC_PTR
,
38 (struct dma_register
*) DMA23_NEXT_DESC_PTR
,
39 (struct dma_register
*) MDMA_D0_NEXT_DESC_PTR
,
40 (struct dma_register
*) MDMA_S0_NEXT_DESC_PTR
,
41 (struct dma_register
*) MDMA_D1_NEXT_DESC_PTR
,
42 (struct dma_register
*) MDMA_S1_NEXT_DESC_PTR
,
43 (struct dma_register
*) MDMA_D2_NEXT_DESC_PTR
,
44 (struct dma_register
*) MDMA_S2_NEXT_DESC_PTR
,
45 (struct dma_register
*) MDMA_D3_NEXT_DESC_PTR
,
46 (struct dma_register
*) MDMA_S3_NEXT_DESC_PTR
,
48 EXPORT_SYMBOL(dma_io_base_addr
);
50 int channel2irq(unsigned int channel
)
56 ret_irq
= IRQ_SPORT0_RX
;
59 ret_irq
= IRQ_SPORT0_TX
;
62 ret_irq
= IRQ_SPORT1_RX
;
65 ret_irq
= IRQ_SPORT1_TX
;
74 ret_irq
= IRQ_UART0_RX
;
77 ret_irq
= IRQ_UART0_TX
;
80 ret_irq
= IRQ_UART1_RX
;
83 ret_irq
= IRQ_UART1_TX
;
95 ret_irq
= IRQ_PIXC_IN0
;
98 ret_irq
= IRQ_PIXC_IN1
;
101 ret_irq
= IRQ_PIXC_OUT
;
104 ret_irq
= IRQ_SPORT2_RX
;
107 ret_irq
= IRQ_SPORT2_TX
;
110 ret_irq
= IRQ_SPORT3_RX
;
113 ret_irq
= IRQ_SPORT3_TX
;
121 case CH_MEM_STREAM0_SRC
:
122 case CH_MEM_STREAM0_DEST
:
123 ret_irq
= IRQ_MDMAS0
;
125 case CH_MEM_STREAM1_SRC
:
126 case CH_MEM_STREAM1_DEST
:
127 ret_irq
= IRQ_MDMAS1
;
129 case CH_MEM_STREAM2_SRC
:
130 case CH_MEM_STREAM2_DEST
:
131 ret_irq
= IRQ_MDMAS2
;
133 case CH_MEM_STREAM3_SRC
:
134 case CH_MEM_STREAM3_DEST
:
135 ret_irq
= IRQ_MDMAS3
;