drivers/usb/dwc2/hcd.h

   1 /*
   2  * hcd.h - DesignWare HS OTG Controller host-mode declarations
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36 #ifndef __DWC2_HCD_H__
  37 #define __DWC2_HCD_H__
  38
  39 /*
  40  * This file contains the structures, constants, and interfaces for the
  41  * Host Contoller Driver (HCD)
  42  *
  43  * The Host Controller Driver (HCD) is responsible for translating requests
  44  * from the USB Driver into the appropriate actions on the DWC_otg controller.
  45  * It isolates the USBD from the specifics of the controller by providing an
  46  * API to the USBD.
  47  */
  48
  49 struct dwc2_qh;
  50
  51 /**
  52  * struct dwc2_host_chan - Software host channel descriptor
  53  *
  54  * @hc_num:             Host channel number, used for register address lookup
  55  * @dev_addr:           Address of the device
  56  * @ep_num:             Endpoint of the device
  57  * @ep_is_in:           Endpoint direction
  58  * @speed:              Device speed. One of the following values:
  59  *                       - USB_SPEED_LOW
  60  *                       - USB_SPEED_FULL
  61  *                       - USB_SPEED_HIGH
  62  * @ep_type:            Endpoint type. One of the following values:
  63  *                       - USB_ENDPOINT_XFER_CONTROL: 0
  64  *                       - USB_ENDPOINT_XFER_ISOC:    1
  65  *                       - USB_ENDPOINT_XFER_BULK:    2
  66  *                       - USB_ENDPOINT_XFER_INTR:    3
  67  * @max_packet:         Max packet size in bytes
  68  * @data_pid_start:     PID for initial transaction.
  69  *                       0: DATA0
  70  *                       1: DATA2
  71  *                       2: DATA1
  72  *                       3: MDATA (non-Control EP),
  73  *                          SETUP (Control EP)
  74  * @multi_count:        Number of additional periodic transactions per
  75  *                      (micro)frame
  76  * @xfer_buf:           Pointer to current transfer buffer position
  77  * @xfer_dma:           DMA address of xfer_buf
  78  * @align_buf:          In Buffer DMA mode this will be used if xfer_buf is not
  79  *                      DWORD aligned
  80  * @xfer_len:           Total number of bytes to transfer
  81  * @xfer_count:         Number of bytes transferred so far
  82  * @start_pkt_count:    Packet count at start of transfer
  83  * @xfer_started:       True if the transfer has been started
  84  * @ping:               True if a PING request should be issued on this channel
  85  * @error_state:        True if the error count for this transaction is non-zero
  86  * @halt_on_queue:      True if this channel should be halted the next time a
  87  *                      request is queued for the channel. This is necessary in
  88  *                      slave mode if no request queue space is available when
  89  *                      an attempt is made to halt the channel.
  90  * @halt_pending:       True if the host channel has been halted, but the core
  91  *                      is not finished flushing queued requests
  92  * @do_split:           Enable split for the channel
  93  * @complete_split:     Enable complete split
  94  * @hub_addr:           Address of high speed hub for the split
  95  * @hub_port:           Port of the low/full speed device for the split
  96  * @xact_pos:           Split transaction position. One of the following values:
  97  *                       - DWC2_HCSPLT_XACTPOS_MID
  98  *                       - DWC2_HCSPLT_XACTPOS_BEGIN
  99  *                       - DWC2_HCSPLT_XACTPOS_END
 100  *                       - DWC2_HCSPLT_XACTPOS_ALL
 101  * @requests:           Number of requests issued for this channel since it was
 102  *                      assigned to the current transfer (not counting PINGs)
 103  * @schinfo:            Scheduling micro-frame bitmap
 104  * @ntd:                Number of transfer descriptors for the transfer
 105  * @halt_status:        Reason for halting the host channel
 106  * @hcint               Contents of the HCINT register when the interrupt came
 107  * @qh:                 QH for the transfer being processed by this channel
 108  * @hc_list_entry:      For linking to list of host channels
 109  * @desc_list_addr:     Current QH's descriptor list DMA address
 110  *
 111  * This structure represents the state of a single host channel when acting in
 112  * host mode. It contains the data items needed to transfer packets to an
 113  * endpoint via a host channel.
 114  */
 115 struct dwc2_host_chan {
 116         u8 hc_num;
 117
 118         unsigned dev_addr:7;
 119         unsigned ep_num:4;
 120         unsigned ep_is_in:1;
 121         unsigned speed:4;
 122         unsigned ep_type:2;
 123         unsigned max_packet:11;
 124         unsigned data_pid_start:2;
 125 #define DWC2_HC_PID_DATA0       TSIZ_SC_MC_PID_DATA0
 126 #define DWC2_HC_PID_DATA2       TSIZ_SC_MC_PID_DATA2
 127 #define DWC2_HC_PID_DATA1       TSIZ_SC_MC_PID_DATA1
 128 #define DWC2_HC_PID_MDATA       TSIZ_SC_MC_PID_MDATA
 129 #define DWC2_HC_PID_SETUP       TSIZ_SC_MC_PID_SETUP
 130
 131         unsigned multi_count:2;
 132
 133         u8 *xfer_buf;
 134         dma_addr_t xfer_dma;
 135         dma_addr_t align_buf;
 136         u32 xfer_len;
 137         u32 xfer_count;
 138         u16 start_pkt_count;
 139         u8 xfer_started;
 140         u8 do_ping;
 141         u8 error_state;
 142         u8 halt_on_queue;
 143         u8 halt_pending;
 144         u8 do_split;
 145         u8 complete_split;
 146         u8 hub_addr;
 147         u8 hub_port;
 148         u8 xact_pos;
 149 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID
 150 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END
 151 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN
 152 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL
 153
 154         u8 requests;
 155         u8 schinfo;
 156         u16 ntd;
 157         enum dwc2_halt_status halt_status;
 158         u32 hcint;
 159         struct dwc2_qh *qh;
 160         struct list_head hc_list_entry;
 161         dma_addr_t desc_list_addr;
 162 };
 163
 164 struct dwc2_hcd_pipe_info {
 165         u8 dev_addr;
 166         u8 ep_num;
 167         u8 pipe_type;
 168         u8 pipe_dir;
 169         u16 mps;
 170 };
 171
 172 struct dwc2_hcd_iso_packet_desc {
 173         u32 offset;
 174         u32 length;
 175         u32 actual_length;
 176         u32 status;
 177 };
 178
 179 struct dwc2_qtd;
 180
 181 struct dwc2_hcd_urb {
 182         void *priv;
 183         struct dwc2_qtd *qtd;
 184         void *buf;
 185         dma_addr_t dma;
 186         void *setup_packet;
 187         dma_addr_t setup_dma;
 188         u32 length;
 189         u32 actual_length;
 190         u32 status;
 191         u32 error_count;
 192         u32 packet_count;
 193         u32 flags;
 194         u16 interval;
 195         struct dwc2_hcd_pipe_info pipe_info;
 196         struct dwc2_hcd_iso_packet_desc iso_descs[0];
 197 };
 198
 199 /* Phases for control transfers */
 200 enum dwc2_control_phase {
 201         DWC2_CONTROL_SETUP,
 202         DWC2_CONTROL_DATA,
 203         DWC2_CONTROL_STATUS,
 204 };
 205
 206 /* Transaction types */
 207 enum dwc2_transaction_type {
 208         DWC2_TRANSACTION_NONE,
 209         DWC2_TRANSACTION_PERIODIC,
 210         DWC2_TRANSACTION_NON_PERIODIC,
 211         DWC2_TRANSACTION_ALL,
 212 };
 213
 214 /**
 215  * struct dwc2_qh - Software queue head structure
 216  *
 217  * @ep_type:            Endpoint type. One of the following values:
 218  *                       - USB_ENDPOINT_XFER_CONTROL
 219  *                       - USB_ENDPOINT_XFER_BULK
 220  *                       - USB_ENDPOINT_XFER_INT
 221  *                       - USB_ENDPOINT_XFER_ISOC
 222  * @ep_is_in:           Endpoint direction
 223  * @maxp:               Value from wMaxPacketSize field of Endpoint Descriptor
 224  * @dev_speed:          Device speed. One of the following values:
 225  *                       - USB_SPEED_LOW
 226  *                       - USB_SPEED_FULL
 227  *                       - USB_SPEED_HIGH
 228  * @data_toggle:        Determines the PID of the next data packet for
 229  *                      non-controltransfers. Ignored for control transfers.
 230  *                      One of the following values:
 231  *                       - DWC2_HC_PID_DATA0
 232  *                       - DWC2_HC_PID_DATA1
 233  * @ping_state:         Ping state
 234  * @do_split:           Full/low speed endpoint on high-speed hub requires split
 235  * @td_first:           Index of first activated isochronous transfer descriptor
 236  * @td_last:            Index of last activated isochronous transfer descriptor
 237  * @usecs:              Bandwidth in microseconds per (micro)frame
 238  * @interval:           Interval between transfers in (micro)frames
 239  * @sched_frame:        (Micro)frame to initialize a periodic transfer.
 240  *                      The transfer executes in the following (micro)frame.
 241  * @frame_usecs:        Internal variable used by the microframe scheduler
 242  * @start_split_frame:  (Micro)frame at which last start split was initialized
 243  * @ntd:                Actual number of transfer descriptors in a list
 244  * @dw_align_buf:       Used instead of original buffer if its physical address
 245  *                      is not dword-aligned
 246  * @dw_align_buf_size:  Size of dw_align_buf
 247  * @dw_align_buf_dma:   DMA address for dw_align_buf
 248  * @qtd_list:           List of QTDs for this QH
 249  * @channel:            Host channel currently processing transfers for this QH
 250  * @qh_list_entry:      Entry for QH in either the periodic or non-periodic
 251  *                      schedule
 252  * @desc_list:          List of transfer descriptors
 253  * @desc_list_dma:      Physical address of desc_list
 254  * @n_bytes:            Xfer Bytes array. Each element corresponds to a transfer
 255  *                      descriptor and indicates original XferSize value for the
 256  *                      descriptor
 257  * @tt_buffer_dirty     True if clear_tt_buffer_complete is pending
 258  *
 259  * A Queue Head (QH) holds the static characteristics of an endpoint and
 260  * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
 261  * be entered in either the non-periodic or periodic schedule.
 262  */
 263 struct dwc2_qh {
 264         u8 ep_type;
 265         u8 ep_is_in;
 266         u16 maxp;
 267         u8 dev_speed;
 268         u8 data_toggle;
 269         u8 ping_state;
 270         u8 do_split;
 271         u8 td_first;
 272         u8 td_last;
 273         u16 usecs;
 274         u16 interval;
 275         u16 sched_frame;
 276         u16 frame_usecs[8];
 277         u16 start_split_frame;
 278         u16 ntd;
 279         u8 *dw_align_buf;
 280         int dw_align_buf_size;
 281         dma_addr_t dw_align_buf_dma;
 282         struct list_head qtd_list;
 283         struct dwc2_host_chan *channel;
 284         struct list_head qh_list_entry;
 285         struct dwc2_hcd_dma_desc *desc_list;
 286         dma_addr_t desc_list_dma;
 287         u32 *n_bytes;
 288         unsigned tt_buffer_dirty:1;
 289 };
 290
 291 /**
 292  * struct dwc2_qtd - Software queue transfer descriptor (QTD)
 293  *
 294  * @control_phase:      Current phase for control transfers (Setup, Data, or
 295  *                      Status)
 296  * @in_process:         Indicates if this QTD is currently processed by HW
 297  * @data_toggle:        Determines the PID of the next data packet for the
 298  *                      data phase of control transfers. Ignored for other
 299  *                      transfer types. One of the following values:
 300  *                       - DWC2_HC_PID_DATA0
 301  *                       - DWC2_HC_PID_DATA1
 302  * @complete_split:     Keeps track of the current split type for FS/LS
 303  *                      endpoints on a HS Hub
 304  * @isoc_split_pos:     Position of the ISOC split in full/low speed
 305  * @isoc_frame_index:   Index of the next frame descriptor for an isochronous
 306  *                      transfer. A frame descriptor describes the buffer
 307  *                      position and length of the data to be transferred in the
 308  *                      next scheduled (micro)frame of an isochronous transfer.
 309  *                      It also holds status for that transaction. The frame
 310  *                      index starts at 0.
 311  * @isoc_split_offset:  Position of the ISOC split in the buffer for the
 312  *                      current frame
 313  * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT
 314  * @error_count:        Holds the number of bus errors that have occurred for
 315  *                      a transaction within this transfer
 316  * @n_desc:             Number of DMA descriptors for this QTD
 317  * @isoc_frame_index_last: Last activated frame (packet) index, used in
 318  *                      descriptor DMA mode only
 319  * @urb:                URB for this transfer
 320  * @qh:                 Queue head for this QTD
 321  * @qtd_list_entry:     For linking to the QH's list of QTDs
 322  *
 323  * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
 324  * interrupt, or isochronous transfer. A single QTD is created for each URB
 325  * (of one of these types) submitted to the HCD. The transfer associated with
 326  * a QTD may require one or multiple transactions.
 327  *
 328  * A QTD is linked to a Queue Head, which is entered in either the
 329  * non-periodic or periodic schedule for execution. When a QTD is chosen for
 330  * execution, some or all of its transactions may be executed. After
 331  * execution, the state of the QTD is updated. The QTD may be retired if all
 332  * its transactions are complete or if an error occurred. Otherwise, it
 333  * remains in the schedule so more transactions can be executed later.
 334  */
 335 struct dwc2_qtd {
 336         enum dwc2_control_phase control_phase;
 337         u8 in_process;
 338         u8 data_toggle;
 339         u8 complete_split;
 340         u8 isoc_split_pos;
 341         u16 isoc_frame_index;
 342         u16 isoc_split_offset;
 343         u32 ssplit_out_xfer_count;
 344         u8 error_count;
 345         u8 n_desc;
 346         u16 isoc_frame_index_last;
 347         struct dwc2_hcd_urb *urb;
 348         struct dwc2_qh *qh;
 349         struct list_head qtd_list_entry;
 350 };
 351
 352 #ifdef DEBUG
 353 struct hc_xfer_info {
 354         struct dwc2_hsotg *hsotg;
 355         struct dwc2_host_chan *chan;
 356 };
 357 #endif
 358
 359 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */
 360 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg)
 361 {
 362         return (struct usb_hcd *)hsotg->priv;
 363 }
 364
 365 /*
 366  * Inline used to disable one channel interrupt. Channel interrupts are
 367  * disabled when the channel is halted or released by the interrupt handler.
 368  * There is no need to handle further interrupts of that type until the
 369  * channel is re-assigned. In fact, subsequent handling may cause crashes
 370  * because the channel structures are cleaned up when the channel is released.
 371  */
 372 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
 373 {
 374         u32 mask = readl(hsotg->regs + HCINTMSK(chnum));
 375
 376         mask &= ~intr;
 377         writel(mask, hsotg->regs + HCINTMSK(chnum));
 378 }
 379
 380 /*
 381  * Returns the mode of operation, host or device
 382  */
 383 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
 384 {
 385         return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
 386 }
 387 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
 388 {
 389         return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
 390 }
 391
 392 /*
 393  * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they
 394  * are read as 1, they won't clear when written back.
 395  */
 396 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
 397 {
 398         u32 hprt0 = readl(hsotg->regs + HPRT0);
 399
 400         hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
 401         return hprt0;
 402 }
 403
 404 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe)
 405 {
 406         return pipe->ep_num;
 407 }
 408
 409 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe)
 410 {
 411         return pipe->pipe_type;
 412 }
 413
 414 static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe)
 415 {
 416         return pipe->mps;
 417 }
 418
 419 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe)
 420 {
 421         return pipe->dev_addr;
 422 }
 423
 424 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe)
 425 {
 426         return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC;
 427 }
 428
 429 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe)
 430 {
 431         return pipe->pipe_type == USB_ENDPOINT_XFER_INT;
 432 }
 433
 434 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe)
 435 {
 436         return pipe->pipe_type == USB_ENDPOINT_XFER_BULK;
 437 }
 438
 439 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe)
 440 {
 441         return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL;
 442 }
 443
 444 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe)
 445 {
 446         return pipe->pipe_dir == USB_DIR_IN;
 447 }
 448
 449 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe)
 450 {
 451         return !dwc2_hcd_is_pipe_in(pipe);
 452 }
 453
 454 extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq,
 455                          const struct dwc2_core_params *params);
 456 extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg);
 457 extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
 458                                 const struct dwc2_core_params *params);
 459 extern void dwc2_set_all_params(struct dwc2_core_params *params, int value);
 460 extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
 461
 462 /* Transaction Execution Functions */
 463 extern enum dwc2_transaction_type dwc2_hcd_select_transactions(
 464                                                 struct dwc2_hsotg *hsotg);
 465 extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
 466                                         enum dwc2_transaction_type tr_type);
 467
 468 /* Schedule Queue Functions */
 469 /* Implemented in hcd_queue.c */
 470 extern void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg);
 471 extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
 472 extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
 473 extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
 474 extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 475                                    int sched_csplit);
 476
 477 extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb);
 478 extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
 479                             struct dwc2_qh **qh, gfp_t mem_flags);
 480
 481 /* Unlinks and frees a QTD */
 482 static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
 483                                                 struct dwc2_qtd *qtd,
 484                                                 struct dwc2_qh *qh)
 485 {
 486         list_del(&qtd->qtd_list_entry);
 487         kfree(qtd);
 488 }
 489
 490 /* Descriptor DMA support functions */
 491 extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg,
 492                                      struct dwc2_qh *qh);
 493 extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg,
 494                                         struct dwc2_host_chan *chan, int chnum,
 495                                         enum dwc2_halt_status halt_status);
 496
 497 extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 498                                  gfp_t mem_flags);
 499 extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
 500
 501 /* Check if QH is non-periodic */
 502 #define dwc2_qh_is_non_per(_qh_ptr_) \
 503         ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \
 504          (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL)
 505
 506 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC
 507 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; }
 508 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; }
 509 static inline bool dbg_urb(struct urb *urb) { return true; }
 510 static inline bool dbg_perio(void) { return true; }
 511 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */
 512 static inline bool dbg_hc(struct dwc2_host_chan *hc)
 513 {
 514         return hc->ep_type == USB_ENDPOINT_XFER_BULK ||
 515                hc->ep_type == USB_ENDPOINT_XFER_CONTROL;
 516 }
 517
 518 static inline bool dbg_qh(struct dwc2_qh *qh)
 519 {
 520         return qh->ep_type == USB_ENDPOINT_XFER_BULK ||
 521                qh->ep_type == USB_ENDPOINT_XFER_CONTROL;
 522 }
 523
 524 static inline bool dbg_urb(struct urb *urb)
 525 {
 526         return usb_pipetype(urb->pipe) == PIPE_BULK ||
 527                usb_pipetype(urb->pipe) == PIPE_CONTROL;
 528 }
 529
 530 static inline bool dbg_perio(void) { return false; }
 531 #endif
 532
 533 /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */
 534 #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03))
 535
 536 /* Packet size for any kind of endpoint descriptor */
 537 #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff)
 538
 539 /*
 540  * Returns true if frame1 is less than or equal to frame2. The comparison is
 541  * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the
 542  * frame number when the max frame number is reached.
 543  */
 544 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2)
 545 {
 546         return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1);
 547 }
 548
 549 /*
 550  * Returns true if frame1 is greater than frame2. The comparison is done
 551  * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
 552  * number when the max frame number is reached.
 553  */
 554 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2)
 555 {
 556         return (frame1 != frame2) &&
 557                ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1);
 558 }
 559
 560 /*
 561  * Increments frame by the amount specified by inc. The addition is done
 562  * modulo HFNUM_MAX_FRNUM. Returns the incremented value.
 563  */
 564 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc)
 565 {
 566         return (frame + inc) & HFNUM_MAX_FRNUM;
 567 }
 568
 569 static inline u16 dwc2_full_frame_num(u16 frame)
 570 {
 571         return (frame & HFNUM_MAX_FRNUM) >> 3;
 572 }
 573
 574 static inline u16 dwc2_micro_frame_num(u16 frame)
 575 {
 576         return frame & 0x7;
 577 }
 578
 579 /*
 580  * Returns the Core Interrupt Status register contents, ANDed with the Core
 581  * Interrupt Mask register contents
 582  */
 583 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
 584 {
 585         return readl(hsotg->regs + GINTSTS) & readl(hsotg->regs + GINTMSK);
 586 }
 587
 588 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
 589 {
 590         return dwc2_urb->status;
 591 }
 592
 593 static inline u32 dwc2_hcd_urb_get_actual_length(
 594                 struct dwc2_hcd_urb *dwc2_urb)
 595 {
 596         return dwc2_urb->actual_length;
 597 }
 598
 599 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb)
 600 {
 601         return dwc2_urb->error_count;
 602 }
 603
 604 static inline void dwc2_hcd_urb_set_iso_desc_params(
 605                 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset,
 606                 u32 length)
 607 {
 608         dwc2_urb->iso_descs[desc_num].offset = offset;
 609         dwc2_urb->iso_descs[desc_num].length = length;
 610 }
 611
 612 static inline u32 dwc2_hcd_urb_get_iso_desc_status(
 613                 struct dwc2_hcd_urb *dwc2_urb, int desc_num)
 614 {
 615         return dwc2_urb->iso_descs[desc_num].status;
 616 }
 617
 618 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length(
 619                 struct dwc2_hcd_urb *dwc2_urb, int desc_num)
 620 {
 621         return dwc2_urb->iso_descs[desc_num].actual_length;
 622 }
 623
 624 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg,
 625                                                   struct usb_host_endpoint *ep)
 626 {
 627         struct dwc2_qh *qh = ep->hcpriv;
 628
 629         if (qh && !list_empty(&qh->qh_list_entry))
 630                 return 1;
 631
 632         return 0;
 633 }
 634
 635 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg,
 636                                             struct usb_host_endpoint *ep)
 637 {
 638         struct dwc2_qh *qh = ep->hcpriv;
 639
 640         if (!qh) {
 641                 WARN_ON(1);
 642                 return 0;
 643         }
 644
 645         return qh->usecs;
 646 }
 647
 648 extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
 649                                       struct dwc2_host_chan *chan, int chnum,
 650                                       struct dwc2_qtd *qtd);
 651
 652 /* HCD Core API */
 653
 654 /**
 655  * dwc2_handle_hcd_intr() - Called on every hardware interrupt
 656  *
 657  * @hsotg: The DWC2 HCD
 658  *
 659  * Returns IRQ_HANDLED if interrupt is handled
 660  * Return IRQ_NONE if interrupt is not handled
 661  */
 662 extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg);
 663
 664 /**
 665  * dwc2_hcd_stop() - Halts the DWC_otg host mode operation
 666  *
 667  * @hsotg: The DWC2 HCD
 668  */
 669 extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg);
 670
 671 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
 672 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg);
 673
 674 /**
 675  * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host,
 676  * and 0 otherwise
 677  *
 678  * @hsotg: The DWC2 HCD
 679  */
 680 extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg);
 681
 682 /**
 683  * dwc2_hcd_get_frame_number() - Returns current frame number
 684  *
 685  * @hsotg: The DWC2 HCD
 686  */
 687 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
 688
 689 /**
 690  * dwc2_hcd_dump_state() - Dumps hsotg state
 691  *
 692  * @hsotg: The DWC2 HCD
 693  *
 694  * NOTE: This function will be removed once the peripheral controller code
 695  * is integrated and the driver is stable
 696  */
 697 extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg);
 698
 699 /**
 700  * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF
 701  *
 702  * @hsotg: The DWC2 HCD
 703  *
 704  * This can be used to determine average interrupt latency. Frame remaining is
 705  * also shown for start transfer and two additional sample points.
 706  *
 707  * NOTE: This function will be removed once the peripheral controller code
 708  * is integrated and the driver is stable
 709  */
 710 extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg);
 711
 712 /* URB interface */
 713
 714 /* Transfer flags */
 715 #define URB_GIVEBACK_ASAP       0x1
 716 #define URB_SEND_ZERO_PACKET    0x2
 717
 718 /* Host driver callbacks */
 719
 720 extern void dwc2_host_start(struct dwc2_hsotg *hsotg);
 721 extern void dwc2_host_disconnect(struct dwc2_hsotg *hsotg);
 722 extern void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
 723                                int *hub_addr, int *hub_port);
 724 extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context);
 725 extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
 726                                int status);
 727
 728 #ifdef DEBUG
 729 /*
 730  * Macro to sample the remaining PHY clocks left in the current frame. This
 731  * may be used during debugging to determine the average time it takes to
 732  * execute sections of code. There are two possible sample points, "a" and
 733  * "b", so the _letter_ argument must be one of these values.
 734  *
 735  * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
 736  * example, "cat /sys/devices/lm0/hcd_frrem".
 737  */
 738 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_)                        \
 739 do {                                                                    \
 740         struct hfnum_data _hfnum_;                                      \
 741         struct dwc2_qtd *_qtd_;                                         \
 742                                                                         \
 743         _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd,      \
 744                            qtd_list_entry);                             \
 745         if (usb_pipeint(_qtd_->urb->pipe) &&                            \
 746             (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \
 747                 _hfnum_.d32 = readl((_hcd_)->regs + HFNUM);             \
 748                 switch (_hfnum_.b.frnum & 0x7) {                        \
 749                 case 7:                                                 \
 750                         (_hcd_)->hfnum_7_samples_##_letter_++;          \
 751                         (_hcd_)->hfnum_7_frrem_accum_##_letter_ +=      \
 752                                 _hfnum_.b.frrem;                        \
 753                         break;                                          \
 754                 case 0:                                                 \
 755                         (_hcd_)->hfnum_0_samples_##_letter_++;          \
 756                         (_hcd_)->hfnum_0_frrem_accum_##_letter_ +=      \
 757                                 _hfnum_.b.frrem;                        \
 758                         break;                                          \
 759                 default:                                                \
 760                         (_hcd_)->hfnum_other_samples_##_letter_++;      \
 761                         (_hcd_)->hfnum_other_frrem_accum_##_letter_ +=  \
 762                                 _hfnum_.b.frrem;                        \
 763                         break;                                          \
 764                 }                                                       \
 765         }                                                               \
 766 } while (0)
 767 #else
 768 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_)        do {} while (0)
 769 #endif
 770
 771 #endif /* __DWC2_HCD_H__ */