| blob | 50eda500f39a184243debd2248c07c583ac6fde5 |
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
16 / {
17 aliases {
18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
22 gpio4 = &gpio5;
23 gpio5 = &gpio6;
24 gpio6 = &gpio7;
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 spi0 = &ecspi1;
34 spi1 = &ecspi2;
35 spi2 = &cspi;
36 ethernet0 = &fec;
37 };
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42 cpu@0 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a8";
45 reg = <0x0>;
46 };
47 };
49 tzic: tz-interrupt-controller@0fffc000 {
50 compatible = "fsl,imx53-tzic", "fsl,tzic";
51 interrupt-controller;
52 #interrupt-cells = <1>;
53 reg = <0x0fffc000 0x4000>;
54 };
56 clocks {
57 #address-cells = <1>;
58 #size-cells = <0>;
60 ckil {
61 compatible = "fsl,imx-ckil", "fixed-clock";
62 clock-frequency = <32768>;
63 };
65 ckih1 {
66 compatible = "fsl,imx-ckih1", "fixed-clock";
67 clock-frequency = <22579200>;
68 };
70 ckih2 {
71 compatible = "fsl,imx-ckih2", "fixed-clock";
72 clock-frequency = <0>;
73 };
75 osc {
76 compatible = "fsl,imx-osc", "fixed-clock";
77 clock-frequency = <24000000>;
78 };
79 };
81 soc {
82 #address-cells = <1>;
83 #size-cells = <1>;
84 compatible = "simple-bus";
85 interrupt-parent = <&tzic>;
86 ranges;
88 ipu: ipu@18000000 {
89 #crtc-cells = <1>;
90 compatible = "fsl,imx53-ipu";
91 reg = <0x18000000 0x08000000>;
92 interrupts = <11 10>;
93 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
94 clock-names = "bus", "di0", "di1";
95 resets = <&src 2>;
96 };
98 aips@50000000 { /* AIPS1 */
99 compatible = "fsl,aips-bus", "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 reg = <0x50000000 0x10000000>;
103 ranges;
105 spba@50000000 {
106 compatible = "fsl,spba-bus", "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 reg = <0x50000000 0x40000>;
110 ranges;
112 esdhc1: esdhc@50004000 {
113 compatible = "fsl,imx53-esdhc";
114 reg = <0x50004000 0x4000>;
115 interrupts = <1>;
116 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
117 clock-names = "ipg", "ahb", "per";
118 bus-width = <4>;
119 status = "disabled";
120 };
122 esdhc2: esdhc@50008000 {
123 compatible = "fsl,imx53-esdhc";
124 reg = <0x50008000 0x4000>;
125 interrupts = <2>;
126 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
127 clock-names = "ipg", "ahb", "per";
128 bus-width = <4>;
129 status = "disabled";
130 };
132 uart3: serial@5000c000 {
133 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
134 reg = <0x5000c000 0x4000>;
135 interrupts = <33>;
136 clocks = <&clks 32>, <&clks 33>;
137 clock-names = "ipg", "per";
138 status = "disabled";
139 };
141 ecspi1: ecspi@50010000 {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
145 reg = <0x50010000 0x4000>;
146 interrupts = <36>;
147 clocks = <&clks 51>, <&clks 52>;
148 clock-names = "ipg", "per";
149 status = "disabled";
150 };
152 ssi2: ssi@50014000 {
153 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
154 reg = <0x50014000 0x4000>;
155 interrupts = <30>;
156 clocks = <&clks 49>;
157 dmas = <&sdma 24 1 0>,
158 <&sdma 25 1 0>;
159 dma-names = "rx", "tx";
160 fsl,fifo-depth = <15>;
161 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
162 status = "disabled";
163 };
165 esdhc3: esdhc@50020000 {
166 compatible = "fsl,imx53-esdhc";
167 reg = <0x50020000 0x4000>;
168 interrupts = <3>;
169 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
170 clock-names = "ipg", "ahb", "per";
171 bus-width = <4>;
172 status = "disabled";
173 };
175 esdhc4: esdhc@50024000 {
176 compatible = "fsl,imx53-esdhc";
177 reg = <0x50024000 0x4000>;
178 interrupts = <4>;
179 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
180 clock-names = "ipg", "ahb", "per";
181 bus-width = <4>;
182 status = "disabled";
183 };
184 };
186 usbphy0: usbphy@0 {
187 compatible = "usb-nop-xceiv";
188 clocks = <&clks 124>;
189 clock-names = "main_clk";
190 status = "okay";
191 };
193 usbphy1: usbphy@1 {
194 compatible = "usb-nop-xceiv";
195 clocks = <&clks 125>;
196 clock-names = "main_clk";
197 status = "okay";
198 };
200 usbotg: usb@53f80000 {
201 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
202 reg = <0x53f80000 0x0200>;
203 interrupts = <18>;
204 clocks = <&clks 108>;
205 fsl,usbmisc = <&usbmisc 0>;
206 fsl,usbphy = <&usbphy0>;
207 status = "disabled";
208 };
210 usbh1: usb@53f80200 {
211 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
212 reg = <0x53f80200 0x0200>;
213 interrupts = <14>;
214 clocks = <&clks 108>;
215 fsl,usbmisc = <&usbmisc 1>;
216 fsl,usbphy = <&usbphy1>;
217 status = "disabled";
218 };
220 usbh2: usb@53f80400 {
221 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
222 reg = <0x53f80400 0x0200>;
223 interrupts = <16>;
224 clocks = <&clks 108>;
225 fsl,usbmisc = <&usbmisc 2>;
226 status = "disabled";
227 };
229 usbh3: usb@53f80600 {
230 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
231 reg = <0x53f80600 0x0200>;
232 interrupts = <17>;
233 clocks = <&clks 108>;
234 fsl,usbmisc = <&usbmisc 3>;
235 status = "disabled";
236 };
238 usbmisc: usbmisc@53f80800 {
239 #index-cells = <1>;
240 compatible = "fsl,imx53-usbmisc";
241 reg = <0x53f80800 0x200>;
242 clocks = <&clks 108>;
243 };
245 gpio1: gpio@53f84000 {
246 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
247 reg = <0x53f84000 0x4000>;
248 interrupts = <50 51>;
249 gpio-controller;
250 #gpio-cells = <2>;
251 interrupt-controller;
252 #interrupt-cells = <2>;
253 };
255 gpio2: gpio@53f88000 {
256 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
257 reg = <0x53f88000 0x4000>;
258 interrupts = <52 53>;
259 gpio-controller;
260 #gpio-cells = <2>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
263 };
265 gpio3: gpio@53f8c000 {
266 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
267 reg = <0x53f8c000 0x4000>;
268 interrupts = <54 55>;
269 gpio-controller;
270 #gpio-cells = <2>;
271 interrupt-controller;
272 #interrupt-cells = <2>;
273 };
275 gpio4: gpio@53f90000 {
276 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
277 reg = <0x53f90000 0x4000>;
278 interrupts = <56 57>;
279 gpio-controller;
280 #gpio-cells = <2>;
281 interrupt-controller;
282 #interrupt-cells = <2>;
283 };
285 wdog1: wdog@53f98000 {
286 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
287 reg = <0x53f98000 0x4000>;
288 interrupts = <58>;
289 clocks = <&clks 0>;
290 };
292 wdog2: wdog@53f9c000 {
293 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
294 reg = <0x53f9c000 0x4000>;
295 interrupts = <59>;
296 clocks = <&clks 0>;
297 status = "disabled";
298 };
300 gpt: timer@53fa0000 {
301 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
302 reg = <0x53fa0000 0x4000>;
303 interrupts = <39>;
304 clocks = <&clks 36>, <&clks 41>;
305 clock-names = "ipg", "per";
306 };
308 iomuxc: iomuxc@53fa8000 {
309 compatible = "fsl,imx53-iomuxc";
310 reg = <0x53fa8000 0x4000>;
312 audmux {
313 pinctrl_audmux_1: audmuxgrp-1 {
314 fsl,pins = <
315 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
316 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
317 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
318 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
319 >;
320 };
322 pinctrl_audmux_2: audmuxgrp-2 {
323 fsl,pins = <
324 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
325 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
326 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
327 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
328 >;
329 };
331 pinctrl_audmux_3: audmuxgrp-3 {
332 fsl,pins = <
333 MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
334 MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
335 MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
336 MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
337 >;
338 };
339 };
341 fec {
342 pinctrl_fec_1: fecgrp-1 {
343 fsl,pins = <
344 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
345 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
346 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
347 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
348 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
349 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
350 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
351 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
352 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
353 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
354 >;
355 };
357 pinctrl_fec_2: fecgrp-2 {
358 fsl,pins = <
359 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
360 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
361 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
362 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
363 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
364 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
365 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
366 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
367 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
368 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
369 MX53_PAD_KEY_ROW1__FEC_COL 0x80000000
370 MX53_PAD_KEY_COL3__FEC_CRS 0x80000000
371 MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000
372 MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000
373 MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000
374 MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000
375 MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000
376 MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000
377 >;
378 };
379 };
381 csi {
382 pinctrl_csi_1: csigrp-1 {
383 fsl,pins = <
384 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
385 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
386 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
387 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
388 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
389 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
390 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
391 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
392 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
393 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
394 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
395 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
396 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
397 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
398 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
399 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
400 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
401 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
402 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
403 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
404 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
405 >;
406 };
408 pinctrl_csi_2: csigrp-2 {
409 fsl,pins = <
410 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
411 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
412 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
413 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
414 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
415 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
416 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
417 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
418 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
419 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
420 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
421 >;
422 };
423 };
425 cspi {
426 pinctrl_cspi_1: cspigrp-1 {
427 fsl,pins = <
428 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
429 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
430 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
431 >;
432 };
434 pinctrl_cspi_2: cspigrp-2 {
435 fsl,pins = <
436 MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
437 MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
438 MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
439 >;
440 };
441 };
443 ecspi1 {
444 pinctrl_ecspi1_1: ecspi1grp-1 {
445 fsl,pins = <
446 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
447 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
448 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
449 >;
450 };
452 pinctrl_ecspi1_2: ecspi1grp-2 {
453 fsl,pins = <
454 MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000
455 MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000
456 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
457 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
458 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
459 MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
460 >;
461 };
462 };
464 ecspi2 {
465 pinctrl_ecspi2_1: ecspi2grp-1 {
466 fsl,pins = <
467 MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000
468 MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
469 MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
470 >;
471 };
472 };
474 esdhc1 {
475 pinctrl_esdhc1_1: esdhc1grp-1 {
476 fsl,pins = <
477 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
478 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
479 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
480 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
481 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
482 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
483 >;
484 };
486 pinctrl_esdhc1_2: esdhc1grp-2 {
487 fsl,pins = <
488 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
489 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
490 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
491 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
492 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
493 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
494 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
495 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
496 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
497 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
498 >;
499 };
500 };
502 esdhc2 {
503 pinctrl_esdhc2_1: esdhc2grp-1 {
504 fsl,pins = <
505 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
506 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
507 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
508 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
509 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
510 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
511 >;
512 };
513 };
515 esdhc3 {
516 pinctrl_esdhc3_1: esdhc3grp-1 {
517 fsl,pins = <
518 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
519 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
520 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
521 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
522 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
523 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
524 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
525 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
526 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
527 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
528 >;
529 };
530 };
532 can1 {
533 pinctrl_can1_1: can1grp-1 {
534 fsl,pins = <
535 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
536 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
537 >;
538 };
540 pinctrl_can1_2: can1grp-2 {
541 fsl,pins = <
542 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
543 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
544 >;
545 };
547 pinctrl_can1_3: can1grp-3 {
548 fsl,pins = <
549 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
550 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
551 >;
552 };
553 };
555 can2 {
556 pinctrl_can2_1: can2grp-1 {
557 fsl,pins = <
558 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
559 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
560 >;
561 };
562 };
564 i2c1 {
565 pinctrl_i2c1_1: i2c1grp-1 {
566 fsl,pins = <
567 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
568 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
569 >;
570 };
572 pinctrl_i2c1_2: i2c1grp-2 {
573 fsl,pins = <
574 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
575 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
576 >;
577 };
578 };
580 i2c2 {
581 pinctrl_i2c2_1: i2c2grp-1 {
582 fsl,pins = <
583 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
584 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
585 >;
586 };
588 pinctrl_i2c2_2: i2c2grp-2 {
589 fsl,pins = <
590 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
591 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
592 >;
593 };
594 };
596 i2c3 {
597 pinctrl_i2c3_1: i2c3grp-1 {
598 fsl,pins = <
599 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
600 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
601 >;
602 };
603 };
605 ipu_disp0 {
606 pinctrl_ipu_disp0_1: ipudisp0grp-1 {
607 fsl,pins = <
608 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
609 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
610 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
611 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
612 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
613 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
614 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
615 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
616 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
617 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
618 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
619 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
620 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
621 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
622 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
623 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
624 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
625 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
626 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
627 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
628 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
629 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
630 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
631 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
632 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
633 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
634 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
635 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
636 >;
637 };
638 };
640 ipu_disp1 {
641 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
642 fsl,pins = <
643 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
644 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
645 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
646 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
647 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
648 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
649 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
650 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
651 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
652 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
653 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
654 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
655 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
656 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
657 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
658 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
659 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
660 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
661 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
662 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
663 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
664 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
665 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
666 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
667 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
668 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
669 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
670 MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
671 MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
672 MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
673 MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
674 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
675 >;
676 };
677 };
679 ipu_disp2 {
680 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
681 fsl,pins = <
682 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
683 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
684 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
685 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
686 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
687 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
688 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
689 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
690 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
691 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
692 >;
693 };
694 };
696 nand {
697 pinctrl_nand_1: nandgrp-1 {
698 fsl,pins = <
699 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
700 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
701 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
702 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
703 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
704 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
705 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
706 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
707 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
708 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
709 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
710 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
711 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
712 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
713 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
714 >;
715 };
716 };
718 owire {
719 pinctrl_owire_1: owiregrp-1 {
720 fsl,pins = <
721 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
722 >;
723 };
724 };
726 pwm1 {
727 pinctrl_pwm1_1: pwm1grp-1 {
728 fsl,pins = <
729 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
730 >;
731 };
732 };
734 pwm2 {
735 pinctrl_pwm2_1: pwm2grp-1 {
736 fsl,pins = <
737 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
738 >;
739 };
740 };
742 uart1 {
743 pinctrl_uart1_1: uart1grp-1 {
744 fsl,pins = <
745 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
746 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
747 >;
748 };
750 pinctrl_uart1_2: uart1grp-2 {
751 fsl,pins = <
752 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
753 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
754 >;
755 };
757 pinctrl_uart1_3: uart1grp-3 {
758 fsl,pins = <
759 MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
760 MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
761 >;
762 };
763 };
765 uart2 {
766 pinctrl_uart2_1: uart2grp-1 {
767 fsl,pins = <
768 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
769 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
770 >;
771 };
773 pinctrl_uart2_2: uart2grp-2 {
774 fsl,pins = <
775 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
776 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
777 MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5
778 MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
779 >;
780 };
781 };
783 uart3 {
784 pinctrl_uart3_1: uart3grp-1 {
785 fsl,pins = <
786 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
787 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
788 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
789 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
790 >;
791 };
793 pinctrl_uart3_2: uart3grp-2 {
794 fsl,pins = <
795 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
796 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
797 >;
798 };
800 };
802 uart4 {
803 pinctrl_uart4_1: uart4grp-1 {
804 fsl,pins = <
805 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
806 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
807 >;
808 };
809 };
811 uart5 {
812 pinctrl_uart5_1: uart5grp-1 {
813 fsl,pins = <
814 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
815 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
816 >;
817 };
818 };
819 };
821 gpr: iomuxc-gpr@53fa8000 {
822 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
823 reg = <0x53fa8000 0xc>;
824 };
826 ldb: ldb@53fa8008 {
827 #address-cells = <1>;
828 #size-cells = <0>;
829 compatible = "fsl,imx53-ldb";
830 reg = <0x53fa8008 0x4>;
831 gpr = <&gpr>;
832 clocks = <&clks 122>, <&clks 120>,
833 <&clks 115>, <&clks 116>,
834 <&clks 123>, <&clks 85>;
835 clock-names = "di0_pll", "di1_pll",
836 "di0_sel", "di1_sel",
837 "di0", "di1";
838 status = "disabled";
840 lvds-channel@0 {
841 reg = <0>;
842 crtcs = <&ipu 0>;
843 status = "disabled";
844 };
846 lvds-channel@1 {
847 reg = <1>;
848 crtcs = <&ipu 1>;
849 status = "disabled";
850 };
851 };
853 pwm1: pwm@53fb4000 {
854 #pwm-cells = <2>;
855 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
856 reg = <0x53fb4000 0x4000>;
857 clocks = <&clks 37>, <&clks 38>;
858 clock-names = "ipg", "per";
859 interrupts = <61>;
860 };
862 pwm2: pwm@53fb8000 {
863 #pwm-cells = <2>;
864 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
865 reg = <0x53fb8000 0x4000>;
866 clocks = <&clks 39>, <&clks 40>;
867 clock-names = "ipg", "per";
868 interrupts = <94>;
869 };
871 uart1: serial@53fbc000 {
872 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
873 reg = <0x53fbc000 0x4000>;
874 interrupts = <31>;
875 clocks = <&clks 28>, <&clks 29>;
876 clock-names = "ipg", "per";
877 status = "disabled";
878 };
880 uart2: serial@53fc0000 {
881 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
882 reg = <0x53fc0000 0x4000>;
883 interrupts = <32>;
884 clocks = <&clks 30>, <&clks 31>;
885 clock-names = "ipg", "per";
886 status = "disabled";
887 };
889 can1: can@53fc8000 {
890 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
891 reg = <0x53fc8000 0x4000>;
892 interrupts = <82>;
893 clocks = <&clks 158>, <&clks 157>;
894 clock-names = "ipg", "per";
895 status = "disabled";
896 };
898 can2: can@53fcc000 {
899 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
900 reg = <0x53fcc000 0x4000>;
901 interrupts = <83>;
902 clocks = <&clks 87>, <&clks 86>;
903 clock-names = "ipg", "per";
904 status = "disabled";
905 };
907 src: src@53fd0000 {
908 compatible = "fsl,imx53-src", "fsl,imx51-src";
909 reg = <0x53fd0000 0x4000>;
910 #reset-cells = <1>;
911 };
913 clks: ccm@53fd4000{
914 compatible = "fsl,imx53-ccm";
915 reg = <0x53fd4000 0x4000>;
916 interrupts = <0 71 0x04 0 72 0x04>;
917 #clock-cells = <1>;
918 };
920 gpio5: gpio@53fdc000 {
921 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
922 reg = <0x53fdc000 0x4000>;
923 interrupts = <103 104>;
924 gpio-controller;
925 #gpio-cells = <2>;
926 interrupt-controller;
927 #interrupt-cells = <2>;
928 };
930 gpio6: gpio@53fe0000 {
931 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
932 reg = <0x53fe0000 0x4000>;
933 interrupts = <105 106>;
934 gpio-controller;
935 #gpio-cells = <2>;
936 interrupt-controller;
937 #interrupt-cells = <2>;
938 };
940 gpio7: gpio@53fe4000 {
941 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
942 reg = <0x53fe4000 0x4000>;
943 interrupts = <107 108>;
944 gpio-controller;
945 #gpio-cells = <2>;
946 interrupt-controller;
947 #interrupt-cells = <2>;
948 };
950 i2c3: i2c@53fec000 {
951 #address-cells = <1>;
952 #size-cells = <0>;
953 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
954 reg = <0x53fec000 0x4000>;
955 interrupts = <64>;
956 clocks = <&clks 88>;
957 status = "disabled";
958 };
960 uart4: serial@53ff0000 {
961 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
962 reg = <0x53ff0000 0x4000>;
963 interrupts = <13>;
964 clocks = <&clks 65>, <&clks 66>;
965 clock-names = "ipg", "per";
966 status = "disabled";
967 };
968 };
970 aips@60000000 { /* AIPS2 */
971 compatible = "fsl,aips-bus", "simple-bus";
972 #address-cells = <1>;
973 #size-cells = <1>;
974 reg = <0x60000000 0x10000000>;
975 ranges;
977 iim: iim@63f98000 {
978 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
979 reg = <0x63f98000 0x4000>;
980 interrupts = <69>;
981 clocks = <&clks 107>;
982 };
984 uart5: serial@63f90000 {
985 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
986 reg = <0x63f90000 0x4000>;
987 interrupts = <86>;
988 clocks = <&clks 67>, <&clks 68>;
989 clock-names = "ipg", "per";
990 status = "disabled";
991 };
993 owire: owire@63fa4000 {
994 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
995 reg = <0x63fa4000 0x4000>;
996 clocks = <&clks 159>;
997 status = "disabled";
998 };
1000 ecspi2: ecspi@63fac000 {
1001 #address-cells = <1>;
1002 #size-cells = <0>;
1003 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
1004 reg = <0x63fac000 0x4000>;
1005 interrupts = <37>;
1006 clocks = <&clks 53>, <&clks 54>;
1007 clock-names = "ipg", "per";
1008 status = "disabled";
1009 };
1011 sdma: sdma@63fb0000 {
1012 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
1013 reg = <0x63fb0000 0x4000>;
1014 interrupts = <6>;
1015 clocks = <&clks 56>, <&clks 56>;
1016 clock-names = "ipg", "ahb";
1017 #dma-cells = <3>;
1018 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
1019 };
1021 cspi: cspi@63fc0000 {
1022 #address-cells = <1>;
1023 #size-cells = <0>;
1024 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
1025 reg = <0x63fc0000 0x4000>;
1026 interrupts = <38>;
1027 clocks = <&clks 55>, <&clks 55>;
1028 clock-names = "ipg", "per";
1029 status = "disabled";
1030 };
1032 i2c2: i2c@63fc4000 {
1033 #address-cells = <1>;
1034 #size-cells = <0>;
1035 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
1036 reg = <0x63fc4000 0x4000>;
1037 interrupts = <63>;
1038 clocks = <&clks 35>;
1039 status = "disabled";
1040 };
1042 i2c1: i2c@63fc8000 {
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1045 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
1046 reg = <0x63fc8000 0x4000>;
1047 interrupts = <62>;
1048 clocks = <&clks 34>;
1049 status = "disabled";
1050 };
1052 ssi1: ssi@63fcc000 {
1053 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1054 reg = <0x63fcc000 0x4000>;
1055 interrupts = <29>;
1056 clocks = <&clks 48>;
1057 dmas = <&sdma 28 0 0>,
1058 <&sdma 29 0 0>;
1059 dma-names = "rx", "tx";
1060 fsl,fifo-depth = <15>;
1061 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
1062 status = "disabled";
1063 };
1065 audmux: audmux@63fd0000 {
1066 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
1067 reg = <0x63fd0000 0x4000>;
1068 status = "disabled";
1069 };
1071 nfc: nand@63fdb000 {
1072 compatible = "fsl,imx53-nand";
1073 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
1074 interrupts = <8>;
1075 clocks = <&clks 60>;
1076 status = "disabled";
1077 };
1079 ssi3: ssi@63fe8000 {
1080 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1081 reg = <0x63fe8000 0x4000>;
1082 interrupts = <96>;
1083 clocks = <&clks 50>;
1084 dmas = <&sdma 46 0 0>,
1085 <&sdma 47 0 0>;
1086 dma-names = "rx", "tx";
1087 fsl,fifo-depth = <15>;
1088 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
1089 status = "disabled";
1090 };
1092 fec: ethernet@63fec000 {
1093 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
1094 reg = <0x63fec000 0x4000>;
1095 interrupts = <87>;
1096 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
1097 clock-names = "ipg", "ahb", "ptp";
1098 status = "disabled";
1099 };
1101 tve: tve@63ff0000 {
1102 compatible = "fsl,imx53-tve";
1103 reg = <0x63ff0000 0x1000>;
1104 interrupts = <92>;
1105 clocks = <&clks 69>, <&clks 116>;
1106 clock-names = "tve", "di_sel";
1107 crtcs = <&ipu 1>;
1108 status = "disabled";
1109 };
1111 vpu: vpu@63ff4000 {
1112 compatible = "fsl,imx53-vpu";
1113 reg = <0x63ff4000 0x1000>;
1114 interrupts = <9>;
1115 clocks = <&clks 63>, <&clks 63>;
1116 clock-names = "per", "ahb";
1117 iram = <&ocram>;
1118 status = "disabled";
1119 };
1120 };
1122 ocram: sram@f8000000 {
1123 compatible = "mmio-sram";
1124 reg = <0xf8000000 0x20000>;
1125 clocks = <&clks 186>;
1126 };
1127 };
1128 };