arch/arm/boot/dts/rk3066a-clocks.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 / {
  17         clocks {
  18                 #address-cells = <1>;
  19                 #size-cells = <1>;
  20                 ranges;
  21
  22                 /*
  23                  * This is a dummy clock, to be used as placeholder on
  24                  * other mux clocks when a specific parent clock is not
  25                  * yet implemented. It should be dropped when the driver
  26                  * is complete.
  27                  */
  28                 dummy: dummy {
  29                         compatible = "fixed-clock";
  30                         clock-frequency = <0>;
  31                         #clock-cells = <0>;
  32                 };
  33
  34                 xin24m: xin24m {
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <24000000>;
  37                         #clock-cells = <0>;
  38                 };
  39
  40                 dummy48m: dummy48m {
  41                         compatible = "fixed-clock";
  42                         clock-frequency = <48000000>;
  43                         #clock-cells = <0>;
  44                 };
  45
  46                 dummy150m: dummy150m {
  47                         compatible = "fixed-clock";
  48                         clock-frequency = <150000000>;
  49                         #clock-cells = <0>;
  50                 };
  51
  52                 clk_gates0: gate-clk@200000d0 {
  53                         compatible = "rockchip,rk2928-gate-clk";
  54                         reg = <0x200000d0 0x4>;
  55                         clocks = <&dummy>, <&dummy>,
  56                                  <&dummy>, <&dummy>,
  57                                  <&dummy>, <&dummy>,
  58                                  <&dummy>, <&dummy>,
  59                                  <&dummy>, <&dummy>,
  60                                  <&dummy>, <&dummy>,
  61                                  <&dummy>, <&dummy>,
  62                                  <&dummy>, <&dummy>;
  63
  64                         clock-output-names =
  65                                 "gate_core_periph", "gate_cpu_gpll",
  66                                 "gate_ddrphy", "gate_aclk_cpu",
  67                                 "gate_hclk_cpu", "gate_pclk_cpu",
  68                                 "gate_atclk_cpu", "gate_i2s0",
  69                                 "gate_i2s0_frac", "gate_i2s1",
  70                                 "gate_i2s1_frac", "gate_i2s2",
  71                                 "gate_i2s2_frac", "gate_spdif",
  72                                 "gate_spdif_frac", "gate_testclk";
  73
  74                         #clock-cells = <1>;
  75                 };
  76
  77                 clk_gates1: gate-clk@200000d4 {
  78                         compatible = "rockchip,rk2928-gate-clk";
  79                         reg = <0x200000d4 0x4>;
  80                         clocks = <&xin24m>, <&xin24m>,
  81                                  <&xin24m>, <&dummy>,
  82                                  <&dummy>, <&xin24m>,
  83                                  <&xin24m>, <&dummy>,
  84                                  <&xin24m>, <&dummy>,
  85                                  <&xin24m>, <&dummy>,
  86                                  <&xin24m>, <&dummy>,
  87                                  <&xin24m>, <&dummy>;
  88
  89                         clock-output-names =
  90                                 "gate_timer0", "gate_timer1",
  91                                 "gate_timer2", "gate_jtag",
  92                                 "gate_aclk_lcdc1_src", "gate_otgphy0",
  93                                 "gate_otgphy1", "gate_ddr_gpll",
  94                                 "gate_uart0", "gate_frac_uart0",
  95                                 "gate_uart1", "gate_frac_uart1",
  96                                 "gate_uart2", "gate_frac_uart2",
  97                                 "gate_uart3", "gate_frac_uart3";
  98
  99                         #clock-cells = <1>;
 100                 };
 101
 102                 clk_gates2: gate-clk@200000d8 {
 103                         compatible = "rockchip,rk2928-gate-clk";
 104                         reg = <0x200000d8 0x4>;
 105                         clocks = <&clk_gates2 1>, <&dummy>,
 106                                  <&dummy>, <&dummy>,
 107                                  <&dummy>, <&dummy>,
 108                                  <&clk_gates2 3>, <&dummy>,
 109                                  <&dummy>, <&dummy>,
 110                                  <&dummy>, <&dummy48m>,
 111                                  <&dummy>, <&dummy48m>,
 112                                  <&dummy>, <&dummy>;
 113
 114                         clock-output-names =
 115                                 "gate_periph_src", "gate_aclk_periph",
 116                                 "gate_hclk_periph", "gate_pclk_periph",
 117                                 "gate_smc", "gate_mac",
 118                                 "gate_hsadc", "gate_hsadc_frac",
 119                                 "gate_saradc", "gate_spi0",
 120                                 "gate_spi1", "gate_mmc0",
 121                                 "gate_mac_lbtest", "gate_mmc1",
 122                                 "gate_emmc", "gate_tsadc";
 123
 124                         #clock-cells = <1>;
 125                 };
 126
 127                 clk_gates3: gate-clk@200000dc {
 128                         compatible = "rockchip,rk2928-gate-clk";
 129                         reg = <0x200000dc 0x4>;
 130                         clocks = <&dummy>, <&dummy>,
 131                                  <&dummy>, <&dummy>,
 132                                  <&dummy>, <&dummy>,
 133                                  <&dummy>, <&dummy>,
 134                                  <&dummy>, <&dummy>,
 135                                  <&dummy>, <&dummy>,
 136                                  <&dummy>, <&dummy>,
 137                                  <&dummy>, <&dummy>;
 138
 139                         clock-output-names =
 140                                 "gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
 141                                 "gate_dclk_lcdc1", "gate_pclkin_cif0",
 142                                 "gate_pclkin_cif1", "reserved",
 143                                 "reserved", "gate_cif0_out",
 144                                 "gate_cif1_out", "gate_aclk_vepu",
 145                                 "gate_hclk_vepu", "gate_aclk_vdpu",
 146                                 "gate_hclk_vdpu", "gate_gpu_src",
 147                                 "reserved", "gate_xin27m";
 148
 149                         #clock-cells = <1>;
 150                 };
 151
 152                 clk_gates4: gate-clk@200000e0 {
 153                         compatible = "rockchip,rk2928-gate-clk";
 154                         reg = <0x200000e0 0x4>;
 155                         clocks = <&clk_gates2 2>, <&clk_gates2 3>,
 156                                  <&clk_gates2 1>, <&clk_gates2 1>,
 157                                  <&clk_gates2 1>, <&clk_gates2 2>,
 158                                  <&clk_gates2 2>, <&clk_gates2 2>,
 159                                  <&clk_gates0 4>, <&clk_gates0 4>,
 160                                  <&clk_gates0 3>, <&clk_gates0 3>,
 161                                  <&clk_gates0 3>, <&clk_gates2 3>,
 162                                  <&clk_gates0 4>;
 163
 164                         clock-output-names =
 165                                 "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
 166                                 "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
 167                                 "gate_aclk_pei_niu", "gate_hclk_usb_peri",
 168                                 "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
 169                                 "gate_hclk_cpubus", "gate_hclk_ahb2apb",
 170                                 "gate_aclk_strc_sys", "gate_aclk_l2mem_con",
 171                                 "gate_aclk_intmem", "gate_pclk_tsadc",
 172                                 "gate_hclk_hdmi";
 173
 174                         #clock-cells = <1>;
 175                 };
 176
 177                 clk_gates5: gate-clk@200000e4 {
 178                         compatible = "rockchip,rk2928-gate-clk";
 179                         reg = <0x200000e4 0x4>;
 180                         clocks = <&clk_gates0 3>, <&clk_gates2 1>,
 181                                  <&clk_gates0 5>, <&clk_gates0 5>,
 182                                  <&clk_gates0 5>, <&clk_gates0 5>,
 183                                  <&clk_gates0 4>, <&clk_gates0 5>,
 184                                  <&clk_gates2 1>, <&clk_gates2 2>,
 185                                  <&clk_gates2 2>, <&clk_gates2 2>,
 186                                  <&clk_gates2 2>, <&clk_gates4 5>,
 187                                  <&clk_gates4 5>, <&dummy>;
 188
 189                         clock-output-names =
 190                                 "gate_aclk_dmac1", "gate_aclk_dmac2",
 191                                 "gate_pclk_efuse", "gate_pclk_tzpc",
 192                                 "gate_pclk_grf", "gate_pclk_pmu",
 193                                 "gate_hclk_rom", "gate_pclk_ddrupctl",
 194                                 "gate_aclk_smc", "gate_hclk_nandc",
 195                                 "gate_hclk_mmc0", "gate_hclk_mmc1",
 196                                 "gate_hclk_emmc", "gate_hclk_otg0",
 197                                 "gate_hclk_otg1", "gate_aclk_gpu";
 198
 199                         #clock-cells = <1>;
 200                 };
 201
 202                 clk_gates6: gate-clk@200000e8 {
 203                         compatible = "rockchip,rk2928-gate-clk";
 204                         reg = <0x200000e8 0x4>;
 205                         clocks = <&clk_gates3 0>, <&clk_gates0 4>,
 206                                  <&clk_gates0 4>, <&clk_gates1 4>,
 207                                  <&clk_gates0 4>, <&clk_gates3 0>,
 208                                  <&clk_gates0 4>, <&clk_gates1 4>,
 209                                  <&clk_gates3 0>, <&clk_gates0 4>,
 210                                  <&clk_gates0 4>, <&clk_gates1 4>,
 211                                  <&clk_gates0 4>, <&clk_gates3 0>,
 212                                  <&dummy>, <&dummy>;
 213
 214                         clock-output-names =
 215                                 "gate_aclk_lcdc0", "gate_hclk_lcdc0",
 216                                 "gate_hclk_lcdc1", "gate_aclk_lcdc1",
 217                                 "gate_hclk_cif0", "gate_aclk_cif0",
 218                                 "gate_hclk_cif1", "gate_aclk_cif1",
 219                                 "gate_aclk_ipp", "gate_hclk_ipp",
 220                                 "gate_hclk_rga", "gate_aclk_rga",
 221                                 "gate_hclk_vio_bus", "gate_aclk_vio0",
 222                                 "gate_aclk_vcodec", "gate_shclk_vio_h2h";
 223
 224                         #clock-cells = <1>;
 225                 };
 226
 227                 clk_gates7: gate-clk@200000ec {
 228                         compatible = "rockchip,rk2928-gate-clk";
 229                         reg = <0x200000ec 0x4>;
 230                         clocks = <&clk_gates2 2>, <&clk_gates0 4>,
 231                                  <&clk_gates0 4>, <&clk_gates0 4>,
 232                                  <&clk_gates0 4>, <&clk_gates2 2>,
 233                                  <&clk_gates2 2>, <&clk_gates0 5>,
 234                                  <&clk_gates0 5>, <&clk_gates0 5>,
 235                                  <&clk_gates0 5>, <&clk_gates2 3>,
 236                                  <&clk_gates2 3>, <&clk_gates2 3>,
 237                                  <&clk_gates2 3>, <&clk_gates2 3>;
 238
 239                         clock-output-names =
 240                                 "gate_hclk_emac", "gate_hclk_spdif",
 241                                 "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch",
 242                                 "gate_hclk_i2s_8ch", "gate_hclk_hsadc",
 243                                 "gate_hclk_pidf", "gate_pclk_timer0",
 244                                 "gate_pclk_timer1", "gate_pclk_timer2",
 245                                 "gate_pclk_pwm01", "gate_pclk_pwm23",
 246                                 "gate_pclk_spi0", "gate_pclk_spi1",
 247                                 "gate_pclk_saradc", "gate_pclk_wdt";
 248
 249                         #clock-cells = <1>;
 250                 };
 251
 252                 clk_gates8: gate-clk@200000f0 {
 253                         compatible = "rockchip,rk2928-gate-clk";
 254                         reg = <0x200000f0 0x4>;
 255                         clocks = <&clk_gates0 5>, <&clk_gates0 5>,
 256                                  <&clk_gates2 3>, <&clk_gates2 3>,
 257                                  <&clk_gates0 5>, <&clk_gates0 5>,
 258                                  <&clk_gates2 3>, <&clk_gates2 3>,
 259                                  <&clk_gates2 3>, <&clk_gates0 5>,
 260                                  <&clk_gates0 5>, <&clk_gates0 5>,
 261                                  <&clk_gates2 3>, <&clk_gates2 3>,
 262                                  <&dummy>, <&clk_gates0 5>;
 263
 264                         clock-output-names =
 265                                 "gate_pclk_uart0", "gate_pclk_uart1",
 266                                 "gate_pclk_uart2", "gate_pclk_uart3",
 267                                 "gate_pclk_i2c0", "gate_pclk_i2c1",
 268                                 "gate_pclk_i2c2", "gate_pclk_i2c3",
 269                                 "gate_pclk_i2c4", "gate_pclk_gpio0",
 270                                 "gate_pclk_gpio1", "gate_pclk_gpio2",
 271                                 "gate_pclk_gpio3", "gate_pclk_gpio4",
 272                                 "reserved", "gate_pclk_gpio6";
 273
 274                         #clock-cells = <1>;
 275                 };
 276
 277                 clk_gates9: gate-clk@200000f4 {
 278                         compatible = "rockchip,rk2928-gate-clk";
 279                         reg = <0x200000f4 0x4>;
 280                         clocks = <&dummy>, <&clk_gates0 5>,
 281                                  <&dummy>, <&dummy>,
 282                                  <&dummy>, <&clk_gates1 4>,
 283                                  <&clk_gates0 5>, <&dummy>,
 284                                  <&dummy>, <&dummy>,
 285                                  <&dummy>;
 286
 287                         clock-output-names =
 288                                 "gate_clk_core_dbg", "gate_pclk_dbg",
 289                                 "gate_clk_trace", "gate_atclk",
 290                                 "gate_clk_l2c", "gate_aclk_vio1",
 291                                 "gate_pclk_publ", "gate_aclk_intmem0",
 292                                 "gate_aclk_intmem1", "gate_aclk_intmem2",
 293                                 "gate_aclk_intmem3";
 294
 295                         #clock-cells = <1>;
 296                 };
 297         };
 298
 299 };