arch/arm/kvm/coproc.c

   1 /*
   2  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   3  * Authors: Rusty Russell <rusty@rustcorp.com.au>
   4  *          Christoffer Dall <c.dall@virtualopensystems.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License, version 2, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  18  */
  19 #include <linux/mm.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/uaccess.h>
  22 #include <asm/kvm_arm.h>
  23 #include <asm/kvm_host.h>
  24 #include <asm/kvm_emulate.h>
  25 #include <asm/kvm_coproc.h>
  26 #include <asm/kvm_mmu.h>
  27 #include <asm/cacheflush.h>
  28 #include <asm/cputype.h>
  29 #include <trace/events/kvm.h>
  30 #include <asm/vfp.h>
  31 #include "../vfp/vfpinstr.h"
  32
  33 #include "trace.h"
  34 #include "coproc.h"
  35
  36
  37 /******************************************************************************
  38  * Co-processor emulation
  39  *****************************************************************************/
  40
  41 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
  42 static u32 cache_levels;
  43
  44 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
  45 #define CSSELR_MAX 12
  46
  47 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run)
  48 {
  49         kvm_inject_undefined(vcpu);
  50         return 1;
  51 }
  52
  53 int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
  54 {
  55         /*
  56          * We can get here, if the host has been built without VFPv3 support,
  57          * but the guest attempted a floating point operation.
  58          */
  59         kvm_inject_undefined(vcpu);
  60         return 1;
  61 }
  62
  63 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
  64 {
  65         kvm_inject_undefined(vcpu);
  66         return 1;
  67 }
  68
  69 int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
  70 {
  71         kvm_inject_undefined(vcpu);
  72         return 1;
  73 }
  74
  75 /* See note at ARM ARM B1.14.4 */
  76 static bool access_dcsw(struct kvm_vcpu *vcpu,
  77                         const struct coproc_params *p,
  78                         const struct coproc_reg *r)
  79 {
  80         unsigned long val;
  81         int cpu;
  82
  83         if (!p->is_write)
  84                 return read_from_write_only(vcpu, p);
  85
  86         cpu = get_cpu();
  87
  88         cpumask_setall(&vcpu->arch.require_dcache_flush);
  89         cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
  90
  91         /* If we were already preempted, take the long way around */
  92         if (cpu != vcpu->arch.last_pcpu) {
  93                 flush_cache_all();
  94                 goto done;
  95         }
  96
  97         val = *vcpu_reg(vcpu, p->Rt1);
  98
  99         switch (p->CRm) {
 100         case 6:                 /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
 101         case 14:                /* DCCISW */
 102                 asm volatile("mcr p15, 0, %0, c7, c14, 2" : : "r" (val));
 103                 break;
 104
 105         case 10:                /* DCCSW */
 106                 asm volatile("mcr p15, 0, %0, c7, c10, 2" : : "r" (val));
 107                 break;
 108         }
 109
 110 done:
 111         put_cpu();
 112
 113         return true;
 114 }
 115
 116 /*
 117  * Generic accessor for VM registers. Only called as long as HCR_TVM
 118  * is set.
 119  */
 120 static bool access_vm_reg(struct kvm_vcpu *vcpu,
 121                           const struct coproc_params *p,
 122                           const struct coproc_reg *r)
 123 {
 124         BUG_ON(!p->is_write);
 125
 126         vcpu->arch.cp15[r->reg] = *vcpu_reg(vcpu, p->Rt1);
 127         if (p->is_64bit)
 128                 vcpu->arch.cp15[r->reg + 1] = *vcpu_reg(vcpu, p->Rt2);
 129
 130         return true;
 131 }
 132
 133 /*
 134  * SCTLR accessor. Only called as long as HCR_TVM is set.  If the
 135  * guest enables the MMU, we stop trapping the VM sys_regs and leave
 136  * it in complete control of the caches.
 137  *
 138  * Used by the cpu-specific code.
 139  */
 140 bool access_sctlr(struct kvm_vcpu *vcpu,
 141                   const struct coproc_params *p,
 142                   const struct coproc_reg *r)
 143 {
 144         access_vm_reg(vcpu, p, r);
 145
 146         if (vcpu_has_cache_enabled(vcpu)) {     /* MMU+Caches enabled? */
 147                 vcpu->arch.hcr &= ~HCR_TVM;
 148                 stage2_flush_vm(vcpu->kvm);
 149         }
 150
 151         return true;
 152 }
 153
 154 /*
 155  * We could trap ID_DFR0 and tell the guest we don't support performance
 156  * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
 157  * NAKed, so it will read the PMCR anyway.
 158  *
 159  * Therefore we tell the guest we have 0 counters.  Unfortunately, we
 160  * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
 161  * all PM registers, which doesn't crash the guest kernel at least.
 162  */
 163 static bool pm_fake(struct kvm_vcpu *vcpu,
 164                     const struct coproc_params *p,
 165                     const struct coproc_reg *r)
 166 {
 167         if (p->is_write)
 168                 return ignore_write(vcpu, p);
 169         else
 170                 return read_zero(vcpu, p);
 171 }
 172
 173 #define access_pmcr pm_fake
 174 #define access_pmcntenset pm_fake
 175 #define access_pmcntenclr pm_fake
 176 #define access_pmovsr pm_fake
 177 #define access_pmselr pm_fake
 178 #define access_pmceid0 pm_fake
 179 #define access_pmceid1 pm_fake
 180 #define access_pmccntr pm_fake
 181 #define access_pmxevtyper pm_fake
 182 #define access_pmxevcntr pm_fake
 183 #define access_pmuserenr pm_fake
 184 #define access_pmintenset pm_fake
 185 #define access_pmintenclr pm_fake
 186
 187 /* Architected CP15 registers.
 188  * CRn denotes the primary register number, but is copied to the CRm in the
 189  * user space API for 64-bit register access in line with the terminology used
 190  * in the ARM ARM.
 191  * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
 192  *            registers preceding 32-bit ones.
 193  */
 194 static const struct coproc_reg cp15_regs[] = {
 195         /* CSSELR: swapped by interrupt.S. */
 196         { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
 197                         NULL, reset_unknown, c0_CSSELR },
 198
 199         /* TTBR0/TTBR1/TTBCR: swapped by interrupt.S. */
 200         { CRm64( 2), Op1( 0), is64, access_vm_reg, reset_unknown64, c2_TTBR0 },
 201         { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32,
 202                         access_vm_reg, reset_unknown, c2_TTBR0 },
 203         { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32,
 204                         access_vm_reg, reset_unknown, c2_TTBR1 },
 205         { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
 206                         access_vm_reg, reset_val, c2_TTBCR, 0x00000000 },
 207         { CRm64( 2), Op1( 1), is64, access_vm_reg, reset_unknown64, c2_TTBR1 },
 208
 209         /* DACR: swapped by interrupt.S. */
 210         { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
 211                         access_vm_reg, reset_unknown, c3_DACR },
 212
 213         /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */
 214         { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
 215                         access_vm_reg, reset_unknown, c5_DFSR },
 216         { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
 217                         access_vm_reg, reset_unknown, c5_IFSR },
 218         { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32,
 219                         access_vm_reg, reset_unknown, c5_ADFSR },
 220         { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32,
 221                         access_vm_reg, reset_unknown, c5_AIFSR },
 222
 223         /* DFAR/IFAR: swapped by interrupt.S. */
 224         { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32,
 225                         access_vm_reg, reset_unknown, c6_DFAR },
 226         { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
 227                         access_vm_reg, reset_unknown, c6_IFAR },
 228
 229         /* PAR swapped by interrupt.S */
 230         { CRm64( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
 231
 232         /*
 233          * DC{C,I,CI}SW operations:
 234          */
 235         { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw},
 236         { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw},
 237         { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw},
 238         /*
 239          * Dummy performance monitor implementation.
 240          */
 241         { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr},
 242         { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset},
 243         { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr},
 244         { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr},
 245         { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr},
 246         { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0},
 247         { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1},
 248         { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr},
 249         { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper},
 250         { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr},
 251         { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr},
 252         { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset},
 253         { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr},
 254
 255         /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */
 256         { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,
 257                         access_vm_reg, reset_unknown, c10_PRRR},
 258         { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,
 259                         access_vm_reg, reset_unknown, c10_NMRR},
 260
 261         /* AMAIR0/AMAIR1: swapped by interrupt.S. */
 262         { CRn(10), CRm( 3), Op1( 0), Op2( 0), is32,
 263                         access_vm_reg, reset_unknown, c10_AMAIR0},
 264         { CRn(10), CRm( 3), Op1( 0), Op2( 1), is32,
 265                         access_vm_reg, reset_unknown, c10_AMAIR1},
 266
 267         /* VBAR: swapped by interrupt.S. */
 268         { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,
 269                         NULL, reset_val, c12_VBAR, 0x00000000 },
 270
 271         /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */
 272         { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32,
 273                         access_vm_reg, reset_val, c13_CID, 0x00000000 },
 274         { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32,
 275                         NULL, reset_unknown, c13_TID_URW },
 276         { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32,
 277                         NULL, reset_unknown, c13_TID_URO },
 278         { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
 279                         NULL, reset_unknown, c13_TID_PRIV },
 280
 281         /* CNTKCTL: swapped by interrupt.S. */
 282         { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32,
 283                         NULL, reset_val, c14_CNTKCTL, 0x00000000 },
 284 };
 285
 286 /* Target specific emulation tables */
 287 static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS];
 288
 289 void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table)
 290 {
 291         target_tables[table->target] = table;
 292 }
 293
 294 /* Get specific register table for this target. */
 295 static const struct coproc_reg *get_target_table(unsigned target, size_t *num)
 296 {
 297         struct kvm_coproc_target_table *table;
 298
 299         table = target_tables[target];
 300         *num = table->num;
 301         return table->table;
 302 }
 303
 304 static const struct coproc_reg *find_reg(const struct coproc_params *params,
 305                                          const struct coproc_reg table[],
 306                                          unsigned int num)
 307 {
 308         unsigned int i;
 309
 310         for (i = 0; i < num; i++) {
 311                 const struct coproc_reg *r = &table[i];
 312
 313                 if (params->is_64bit != r->is_64)
 314                         continue;
 315                 if (params->CRn != r->CRn)
 316                         continue;
 317                 if (params->CRm != r->CRm)
 318                         continue;
 319                 if (params->Op1 != r->Op1)
 320                         continue;
 321                 if (params->Op2 != r->Op2)
 322                         continue;
 323
 324                 return r;
 325         }
 326         return NULL;
 327 }
 328
 329 static int emulate_cp15(struct kvm_vcpu *vcpu,
 330                         const struct coproc_params *params)
 331 {
 332         size_t num;
 333         const struct coproc_reg *table, *r;
 334
 335         trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn,
 336                                    params->CRm, params->Op2, params->is_write);
 337
 338         table = get_target_table(vcpu->arch.target, &num);
 339
 340         /* Search target-specific then generic table. */
 341         r = find_reg(params, table, num);
 342         if (!r)
 343                 r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
 344
 345         if (likely(r)) {
 346                 /* If we don't have an accessor, we should never get here! */
 347                 BUG_ON(!r->access);
 348
 349                 if (likely(r->access(vcpu, params, r))) {
 350                         /* Skip instruction, since it was emulated */
 351                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 352                         return 1;
 353                 }
 354                 /* If access function fails, it should complain. */
 355         } else {
 356                 kvm_err("Unsupported guest CP15 access at: %08lx\n",
 357                         *vcpu_pc(vcpu));
 358                 print_cp_instr(params);
 359         }
 360         kvm_inject_undefined(vcpu);
 361         return 1;
 362 }
 363
 364 /**
 365  * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
 366  * @vcpu: The VCPU pointer
 367  * @run:  The kvm_run struct
 368  */
 369 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
 370 {
 371         struct coproc_params params;
 372
 373         params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
 374         params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
 375         params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
 376         params.is_64bit = true;
 377
 378         params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf;
 379         params.Op2 = 0;
 380         params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
 381         params.CRm = 0;
 382
 383         return emulate_cp15(vcpu, &params);
 384 }
 385
 386 static void reset_coproc_regs(struct kvm_vcpu *vcpu,
 387                               const struct coproc_reg *table, size_t num)
 388 {
 389         unsigned long i;
 390
 391         for (i = 0; i < num; i++)
 392                 if (table[i].reset)
 393                         table[i].reset(vcpu, &table[i]);
 394 }
 395
 396 /**
 397  * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
 398  * @vcpu: The VCPU pointer
 399  * @run:  The kvm_run struct
 400  */
 401 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
 402 {
 403         struct coproc_params params;
 404
 405         params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
 406         params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
 407         params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
 408         params.is_64bit = false;
 409
 410         params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
 411         params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 14) & 0x7;
 412         params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7;
 413         params.Rt2 = 0;
 414
 415         return emulate_cp15(vcpu, &params);
 416 }
 417
 418 /******************************************************************************
 419  * Userspace API
 420  *****************************************************************************/
 421
 422 static bool index_to_params(u64 id, struct coproc_params *params)
 423 {
 424         switch (id & KVM_REG_SIZE_MASK) {
 425         case KVM_REG_SIZE_U32:
 426                 /* Any unused index bits means it's not valid. */
 427                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
 428                            | KVM_REG_ARM_COPROC_MASK
 429                            | KVM_REG_ARM_32_CRN_MASK
 430                            | KVM_REG_ARM_CRM_MASK
 431                            | KVM_REG_ARM_OPC1_MASK
 432                            | KVM_REG_ARM_32_OPC2_MASK))
 433                         return false;
 434
 435                 params->is_64bit = false;
 436                 params->CRn = ((id & KVM_REG_ARM_32_CRN_MASK)
 437                                >> KVM_REG_ARM_32_CRN_SHIFT);
 438                 params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
 439                                >> KVM_REG_ARM_CRM_SHIFT);
 440                 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
 441                                >> KVM_REG_ARM_OPC1_SHIFT);
 442                 params->Op2 = ((id & KVM_REG_ARM_32_OPC2_MASK)
 443                                >> KVM_REG_ARM_32_OPC2_SHIFT);
 444                 return true;
 445         case KVM_REG_SIZE_U64:
 446                 /* Any unused index bits means it's not valid. */
 447                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
 448                               | KVM_REG_ARM_COPROC_MASK
 449                               | KVM_REG_ARM_CRM_MASK
 450                               | KVM_REG_ARM_OPC1_MASK))
 451                         return false;
 452                 params->is_64bit = true;
 453                 /* CRm to CRn: see cp15_to_index for details */
 454                 params->CRn = ((id & KVM_REG_ARM_CRM_MASK)
 455                                >> KVM_REG_ARM_CRM_SHIFT);
 456                 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
 457                                >> KVM_REG_ARM_OPC1_SHIFT);
 458                 params->Op2 = 0;
 459                 params->CRm = 0;
 460                 return true;
 461         default:
 462                 return false;
 463         }
 464 }
 465
 466 /* Decode an index value, and find the cp15 coproc_reg entry. */
 467 static const struct coproc_reg *index_to_coproc_reg(struct kvm_vcpu *vcpu,
 468                                                     u64 id)
 469 {
 470         size_t num;
 471         const struct coproc_reg *table, *r;
 472         struct coproc_params params;
 473
 474         /* We only do cp15 for now. */
 475         if ((id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT != 15)
 476                 return NULL;
 477
 478         if (!index_to_params(id, &params))
 479                 return NULL;
 480
 481         table = get_target_table(vcpu->arch.target, &num);
 482         r = find_reg(&params, table, num);
 483         if (!r)
 484                 r = find_reg(&params, cp15_regs, ARRAY_SIZE(cp15_regs));
 485
 486         /* Not saved in the cp15 array? */
 487         if (r && !r->reg)
 488                 r = NULL;
 489
 490         return r;
 491 }
 492
 493 /*
 494  * These are the invariant cp15 registers: we let the guest see the host
 495  * versions of these, so they're part of the guest state.
 496  *
 497  * A future CPU may provide a mechanism to present different values to
 498  * the guest, or a future kvm may trap them.
 499  */
 500 /* Unfortunately, there's no register-argument for mrc, so generate. */
 501 #define FUNCTION_FOR32(crn, crm, op1, op2, name)                        \
 502         static void get_##name(struct kvm_vcpu *v,                      \
 503                                const struct coproc_reg *r)              \
 504         {                                                               \
 505                 u32 val;                                                \
 506                                                                         \
 507                 asm volatile("mrc p15, " __stringify(op1)               \
 508                              ", %0, c" __stringify(crn)                 \
 509                              ", c" __stringify(crm)                     \
 510                              ", " __stringify(op2) "\n" : "=r" (val));  \
 511                 ((struct coproc_reg *)r)->val = val;                    \
 512         }
 513
 514 FUNCTION_FOR32(0, 0, 0, 0, MIDR)
 515 FUNCTION_FOR32(0, 0, 0, 1, CTR)
 516 FUNCTION_FOR32(0, 0, 0, 2, TCMTR)
 517 FUNCTION_FOR32(0, 0, 0, 3, TLBTR)
 518 FUNCTION_FOR32(0, 0, 0, 6, REVIDR)
 519 FUNCTION_FOR32(0, 1, 0, 0, ID_PFR0)
 520 FUNCTION_FOR32(0, 1, 0, 1, ID_PFR1)
 521 FUNCTION_FOR32(0, 1, 0, 2, ID_DFR0)
 522 FUNCTION_FOR32(0, 1, 0, 3, ID_AFR0)
 523 FUNCTION_FOR32(0, 1, 0, 4, ID_MMFR0)
 524 FUNCTION_FOR32(0, 1, 0, 5, ID_MMFR1)
 525 FUNCTION_FOR32(0, 1, 0, 6, ID_MMFR2)
 526 FUNCTION_FOR32(0, 1, 0, 7, ID_MMFR3)
 527 FUNCTION_FOR32(0, 2, 0, 0, ID_ISAR0)
 528 FUNCTION_FOR32(0, 2, 0, 1, ID_ISAR1)
 529 FUNCTION_FOR32(0, 2, 0, 2, ID_ISAR2)
 530 FUNCTION_FOR32(0, 2, 0, 3, ID_ISAR3)
 531 FUNCTION_FOR32(0, 2, 0, 4, ID_ISAR4)
 532 FUNCTION_FOR32(0, 2, 0, 5, ID_ISAR5)
 533 FUNCTION_FOR32(0, 0, 1, 1, CLIDR)
 534 FUNCTION_FOR32(0, 0, 1, 7, AIDR)
 535
 536 /* ->val is filled in by kvm_invariant_coproc_table_init() */
 537 static struct coproc_reg invariant_cp15[] = {
 538         { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR },
 539         { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR },
 540         { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR },
 541         { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR },
 542         { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR },
 543
 544         { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 },
 545         { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 },
 546         { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 },
 547         { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 },
 548         { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 },
 549         { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 },
 550         { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 },
 551         { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 },
 552
 553         { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 },
 554         { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 },
 555         { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 },
 556         { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 },
 557         { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 },
 558         { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 },
 559
 560         { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR },
 561         { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR },
 562 };
 563
 564 static int reg_from_user(void *val, const void __user *uaddr, u64 id)
 565 {
 566         /* This Just Works because we are little endian. */
 567         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
 568                 return -EFAULT;
 569         return 0;
 570 }
 571
 572 static int reg_to_user(void __user *uaddr, const void *val, u64 id)
 573 {
 574         /* This Just Works because we are little endian. */
 575         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
 576                 return -EFAULT;
 577         return 0;
 578 }
 579
 580 static int get_invariant_cp15(u64 id, void __user *uaddr)
 581 {
 582         struct coproc_params params;
 583         const struct coproc_reg *r;
 584
 585         if (!index_to_params(id, &params))
 586                 return -ENOENT;
 587
 588         r = find_reg(&params, invariant_cp15, ARRAY_SIZE(invariant_cp15));
 589         if (!r)
 590                 return -ENOENT;
 591
 592         return reg_to_user(uaddr, &r->val, id);
 593 }
 594
 595 static int set_invariant_cp15(u64 id, void __user *uaddr)
 596 {
 597         struct coproc_params params;
 598         const struct coproc_reg *r;
 599         int err;
 600         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
 601
 602         if (!index_to_params(id, &params))
 603                 return -ENOENT;
 604         r = find_reg(&params, invariant_cp15, ARRAY_SIZE(invariant_cp15));
 605         if (!r)
 606                 return -ENOENT;
 607
 608         err = reg_from_user(&val, uaddr, id);
 609         if (err)
 610                 return err;
 611
 612         /* This is what we mean by invariant: you can't change it. */
 613         if (r->val != val)
 614                 return -EINVAL;
 615
 616         return 0;
 617 }
 618
 619 static bool is_valid_cache(u32 val)
 620 {
 621         u32 level, ctype;
 622
 623         if (val >= CSSELR_MAX)
 624                 return false;
 625
 626         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
 627         level = (val >> 1);
 628         ctype = (cache_levels >> (level * 3)) & 7;
 629
 630         switch (ctype) {
 631         case 0: /* No cache */
 632                 return false;
 633         case 1: /* Instruction cache only */
 634                 return (val & 1);
 635         case 2: /* Data cache only */
 636         case 4: /* Unified cache */
 637                 return !(val & 1);
 638         case 3: /* Separate instruction and data caches */
 639                 return true;
 640         default: /* Reserved: we can't know instruction or data. */
 641                 return false;
 642         }
 643 }
 644
 645 /* Which cache CCSIDR represents depends on CSSELR value. */
 646 static u32 get_ccsidr(u32 csselr)
 647 {
 648         u32 ccsidr;
 649
 650         /* Make sure noone else changes CSSELR during this! */
 651         local_irq_disable();
 652         /* Put value into CSSELR */
 653         asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
 654         isb();
 655         /* Read result out of CCSIDR */
 656         asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
 657         local_irq_enable();
 658
 659         return ccsidr;
 660 }
 661
 662 static int demux_c15_get(u64 id, void __user *uaddr)
 663 {
 664         u32 val;
 665         u32 __user *uval = uaddr;
 666
 667         /* Fail if we have unknown bits set. */
 668         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
 669                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
 670                 return -ENOENT;
 671
 672         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
 673         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
 674                 if (KVM_REG_SIZE(id) != 4)
 675                         return -ENOENT;
 676                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
 677                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
 678                 if (!is_valid_cache(val))
 679                         return -ENOENT;
 680
 681                 return put_user(get_ccsidr(val), uval);
 682         default:
 683                 return -ENOENT;
 684         }
 685 }
 686
 687 static int demux_c15_set(u64 id, void __user *uaddr)
 688 {
 689         u32 val, newval;
 690         u32 __user *uval = uaddr;
 691
 692         /* Fail if we have unknown bits set. */
 693         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
 694                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
 695                 return -ENOENT;
 696
 697         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
 698         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
 699                 if (KVM_REG_SIZE(id) != 4)
 700                         return -ENOENT;
 701                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
 702                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
 703                 if (!is_valid_cache(val))
 704                         return -ENOENT;
 705
 706                 if (get_user(newval, uval))
 707                         return -EFAULT;
 708
 709                 /* This is also invariant: you can't change it. */
 710                 if (newval != get_ccsidr(val))
 711                         return -EINVAL;
 712                 return 0;
 713         default:
 714                 return -ENOENT;
 715         }
 716 }
 717
 718 #ifdef CONFIG_VFPv3
 719 static const int vfp_sysregs[] = { KVM_REG_ARM_VFP_FPEXC,
 720                                    KVM_REG_ARM_VFP_FPSCR,
 721                                    KVM_REG_ARM_VFP_FPINST,
 722                                    KVM_REG_ARM_VFP_FPINST2,
 723                                    KVM_REG_ARM_VFP_MVFR0,
 724                                    KVM_REG_ARM_VFP_MVFR1,
 725                                    KVM_REG_ARM_VFP_FPSID };
 726
 727 static unsigned int num_fp_regs(void)
 728 {
 729         if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK) >> MVFR0_A_SIMD_BIT) == 2)
 730                 return 32;
 731         else
 732                 return 16;
 733 }
 734
 735 static unsigned int num_vfp_regs(void)
 736 {
 737         /* Normal FP regs + control regs. */
 738         return num_fp_regs() + ARRAY_SIZE(vfp_sysregs);
 739 }
 740
 741 static int copy_vfp_regids(u64 __user *uindices)
 742 {
 743         unsigned int i;
 744         const u64 u32reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP;
 745         const u64 u64reg = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 746
 747         for (i = 0; i < num_fp_regs(); i++) {
 748                 if (put_user((u64reg | KVM_REG_ARM_VFP_BASE_REG) + i,
 749                              uindices))
 750                         return -EFAULT;
 751                 uindices++;
 752         }
 753
 754         for (i = 0; i < ARRAY_SIZE(vfp_sysregs); i++) {
 755                 if (put_user(u32reg | vfp_sysregs[i], uindices))
 756                         return -EFAULT;
 757                 uindices++;
 758         }
 759
 760         return num_vfp_regs();
 761 }
 762
 763 static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
 764 {
 765         u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
 766         u32 val;
 767
 768         /* Fail if we have unknown bits set. */
 769         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
 770                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
 771                 return -ENOENT;
 772
 773         if (vfpid < num_fp_regs()) {
 774                 if (KVM_REG_SIZE(id) != 8)
 775                         return -ENOENT;
 776                 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpregs[vfpid],
 777                                    id);
 778         }
 779
 780         /* FP control registers are all 32 bit. */
 781         if (KVM_REG_SIZE(id) != 4)
 782                 return -ENOENT;
 783
 784         switch (vfpid) {
 785         case KVM_REG_ARM_VFP_FPEXC:
 786                 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpexc, id);
 787         case KVM_REG_ARM_VFP_FPSCR:
 788                 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpscr, id);
 789         case KVM_REG_ARM_VFP_FPINST:
 790                 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst, id);
 791         case KVM_REG_ARM_VFP_FPINST2:
 792                 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst2, id);
 793         case KVM_REG_ARM_VFP_MVFR0:
 794                 val = fmrx(MVFR0);
 795                 return reg_to_user(uaddr, &val, id);
 796         case KVM_REG_ARM_VFP_MVFR1:
 797                 val = fmrx(MVFR1);
 798                 return reg_to_user(uaddr, &val, id);
 799         case KVM_REG_ARM_VFP_FPSID:
 800                 val = fmrx(FPSID);
 801                 return reg_to_user(uaddr, &val, id);
 802         default:
 803                 return -ENOENT;
 804         }
 805 }
 806
 807 static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
 808 {
 809         u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
 810         u32 val;
 811
 812         /* Fail if we have unknown bits set. */
 813         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
 814                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
 815                 return -ENOENT;
 816
 817         if (vfpid < num_fp_regs()) {
 818                 if (KVM_REG_SIZE(id) != 8)
 819                         return -ENOENT;
 820                 return reg_from_user(&vcpu->arch.vfp_guest.fpregs[vfpid],
 821                                      uaddr, id);
 822         }
 823
 824         /* FP control registers are all 32 bit. */
 825         if (KVM_REG_SIZE(id) != 4)
 826                 return -ENOENT;
 827
 828         switch (vfpid) {
 829         case KVM_REG_ARM_VFP_FPEXC:
 830                 return reg_from_user(&vcpu->arch.vfp_guest.fpexc, uaddr, id);
 831         case KVM_REG_ARM_VFP_FPSCR:
 832                 return reg_from_user(&vcpu->arch.vfp_guest.fpscr, uaddr, id);
 833         case KVM_REG_ARM_VFP_FPINST:
 834                 return reg_from_user(&vcpu->arch.vfp_guest.fpinst, uaddr, id);
 835         case KVM_REG_ARM_VFP_FPINST2:
 836                 return reg_from_user(&vcpu->arch.vfp_guest.fpinst2, uaddr, id);
 837         /* These are invariant. */
 838         case KVM_REG_ARM_VFP_MVFR0:
 839                 if (reg_from_user(&val, uaddr, id))
 840                         return -EFAULT;
 841                 if (val != fmrx(MVFR0))
 842                         return -EINVAL;
 843                 return 0;
 844         case KVM_REG_ARM_VFP_MVFR1:
 845                 if (reg_from_user(&val, uaddr, id))
 846                         return -EFAULT;
 847                 if (val != fmrx(MVFR1))
 848                         return -EINVAL;
 849                 return 0;
 850         case KVM_REG_ARM_VFP_FPSID:
 851                 if (reg_from_user(&val, uaddr, id))
 852                         return -EFAULT;
 853                 if (val != fmrx(FPSID))
 854                         return -EINVAL;
 855                 return 0;
 856         default:
 857                 return -ENOENT;
 858         }
 859 }
 860 #else /* !CONFIG_VFPv3 */
 861 static unsigned int num_vfp_regs(void)
 862 {
 863         return 0;
 864 }
 865
 866 static int copy_vfp_regids(u64 __user *uindices)
 867 {
 868         return 0;
 869 }
 870
 871 static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
 872 {
 873         return -ENOENT;
 874 }
 875
 876 static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
 877 {
 878         return -ENOENT;
 879 }
 880 #endif /* !CONFIG_VFPv3 */
 881
 882 int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
 883 {
 884         const struct coproc_reg *r;
 885         void __user *uaddr = (void __user *)(long)reg->addr;
 886
 887         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
 888                 return demux_c15_get(reg->id, uaddr);
 889
 890         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
 891                 return vfp_get_reg(vcpu, reg->id, uaddr);
 892
 893         r = index_to_coproc_reg(vcpu, reg->id);
 894         if (!r)
 895                 return get_invariant_cp15(reg->id, uaddr);
 896
 897         /* Note: copies two regs if size is 64 bit. */
 898         return reg_to_user(uaddr, &vcpu->arch.cp15[r->reg], reg->id);
 899 }
 900
 901 int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
 902 {
 903         const struct coproc_reg *r;
 904         void __user *uaddr = (void __user *)(long)reg->addr;
 905
 906         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
 907                 return demux_c15_set(reg->id, uaddr);
 908
 909         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
 910                 return vfp_set_reg(vcpu, reg->id, uaddr);
 911
 912         r = index_to_coproc_reg(vcpu, reg->id);
 913         if (!r)
 914                 return set_invariant_cp15(reg->id, uaddr);
 915
 916         /* Note: copies two regs if size is 64 bit */
 917         return reg_from_user(&vcpu->arch.cp15[r->reg], uaddr, reg->id);
 918 }
 919
 920 static unsigned int num_demux_regs(void)
 921 {
 922         unsigned int i, count = 0;
 923
 924         for (i = 0; i < CSSELR_MAX; i++)
 925                 if (is_valid_cache(i))
 926                         count++;
 927
 928         return count;
 929 }
 930
 931 static int write_demux_regids(u64 __user *uindices)
 932 {
 933         u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
 934         unsigned int i;
 935
 936         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
 937         for (i = 0; i < CSSELR_MAX; i++) {
 938                 if (!is_valid_cache(i))
 939                         continue;
 940                 if (put_user(val | i, uindices))
 941                         return -EFAULT;
 942                 uindices++;
 943         }
 944         return 0;
 945 }
 946
 947 static u64 cp15_to_index(const struct coproc_reg *reg)
 948 {
 949         u64 val = KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT);
 950         if (reg->is_64) {
 951                 val |= KVM_REG_SIZE_U64;
 952                 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
 953                 /*
 954                  * CRn always denotes the primary coproc. reg. nr. for the
 955                  * in-kernel representation, but the user space API uses the
 956                  * CRm for the encoding, because it is modelled after the
 957                  * MRRC/MCRR instructions: see the ARM ARM rev. c page
 958                  * B3-1445
 959                  */
 960                 val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT);
 961         } else {
 962                 val |= KVM_REG_SIZE_U32;
 963                 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
 964                 val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT);
 965                 val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
 966                 val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT);
 967         }
 968         return val;
 969 }
 970
 971 static bool copy_reg_to_user(const struct coproc_reg *reg, u64 __user **uind)
 972 {
 973         if (!*uind)
 974                 return true;
 975
 976         if (put_user(cp15_to_index(reg), *uind))
 977                 return false;
 978
 979         (*uind)++;
 980         return true;
 981 }
 982
 983 /* Assumed ordered tables, see kvm_coproc_table_init. */
 984 static int walk_cp15(struct kvm_vcpu *vcpu, u64 __user *uind)
 985 {
 986         const struct coproc_reg *i1, *i2, *end1, *end2;
 987         unsigned int total = 0;
 988         size_t num;
 989
 990         /* We check for duplicates here, to allow arch-specific overrides. */
 991         i1 = get_target_table(vcpu->arch.target, &num);
 992         end1 = i1 + num;
 993         i2 = cp15_regs;
 994         end2 = cp15_regs + ARRAY_SIZE(cp15_regs);
 995
 996         BUG_ON(i1 == end1 || i2 == end2);
 997
 998         /* Walk carefully, as both tables may refer to the same register. */
 999         while (i1 || i2) {
1000                 int cmp = cmp_reg(i1, i2);
1001                 /* target-specific overrides generic entry. */
1002                 if (cmp <= 0) {
1003                         /* Ignore registers we trap but don't save. */
1004                         if (i1->reg) {
1005                                 if (!copy_reg_to_user(i1, &uind))
1006                                         return -EFAULT;
1007                                 total++;
1008                         }
1009                 } else {
1010                         /* Ignore registers we trap but don't save. */
1011                         if (i2->reg) {
1012                                 if (!copy_reg_to_user(i2, &uind))
1013                                         return -EFAULT;
1014                                 total++;
1015                         }
1016                 }
1017
1018                 if (cmp <= 0 && ++i1 == end1)
1019                         i1 = NULL;
1020                 if (cmp >= 0 && ++i2 == end2)
1021                         i2 = NULL;
1022         }
1023         return total;
1024 }
1025
1026 unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu)
1027 {
1028         return ARRAY_SIZE(invariant_cp15)
1029                 + num_demux_regs()
1030                 + num_vfp_regs()
1031                 + walk_cp15(vcpu, (u64 __user *)NULL);
1032 }
1033
1034 int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
1035 {
1036         unsigned int i;
1037         int err;
1038
1039         /* Then give them all the invariant registers' indices. */
1040         for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) {
1041                 if (put_user(cp15_to_index(&invariant_cp15[i]), uindices))
1042                         return -EFAULT;
1043                 uindices++;
1044         }
1045
1046         err = walk_cp15(vcpu, uindices);
1047         if (err < 0)
1048                 return err;
1049         uindices += err;
1050
1051         err = copy_vfp_regids(uindices);
1052         if (err < 0)
1053                 return err;
1054         uindices += err;
1055
1056         return write_demux_regids(uindices);
1057 }
1058
1059 void kvm_coproc_table_init(void)
1060 {
1061         unsigned int i;
1062
1063         /* Make sure tables are unique and in order. */
1064         for (i = 1; i < ARRAY_SIZE(cp15_regs); i++)
1065                 BUG_ON(cmp_reg(&cp15_regs[i-1], &cp15_regs[i]) >= 0);
1066
1067         /* We abuse the reset function to overwrite the table itself. */
1068         for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++)
1069                 invariant_cp15[i].reset(NULL, &invariant_cp15[i]);
1070
1071         /*
1072          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
1073          *
1074          *   If software reads the Cache Type fields from Ctype1
1075          *   upwards, once it has seen a value of 0b000, no caches
1076          *   exist at further-out levels of the hierarchy. So, for
1077          *   example, if Ctype3 is the first Cache Type field with a
1078          *   value of 0b000, the values of Ctype4 to Ctype7 must be
1079          *   ignored.
1080          */
1081         asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels));
1082         for (i = 0; i < 7; i++)
1083                 if (((cache_levels >> (i*3)) & 7) == 0)
1084                         break;
1085         /* Clear all higher bits. */
1086         cache_levels &= (1 << (i*3))-1;
1087 }
1088
1089 /**
1090  * kvm_reset_coprocs - sets cp15 registers to reset value
1091  * @vcpu: The VCPU pointer
1092  *
1093  * This function finds the right table above and sets the registers on the
1094  * virtual CPU struct to their architecturally defined reset values.
1095  */
1096 void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
1097 {
1098         size_t num;
1099         const struct coproc_reg *table;
1100
1101         /* Catch someone adding a register without putting in reset entry. */
1102         memset(vcpu->arch.cp15, 0x42, sizeof(vcpu->arch.cp15));
1103
1104         /* Generic chip reset first (so target could override). */
1105         reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
1106
1107         table = get_target_table(vcpu->arch.target, &num);
1108         reset_coproc_regs(vcpu, table, num);
1109
1110         for (num = 1; num < NR_CP15_REGS; num++)
1111                 if (vcpu->arch.cp15[num] == 0x42424242)
1112                         panic("Didn't reset vcpu->arch.cp15[%zi]", num);
1113 }