2 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/linkage.h>
18 #include <linux/init.h>
20 #include <asm/cache.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/hardware/cache-l2x0.h>
30 #define PMC_SCRATCH41 0x140
32 #define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
34 #ifdef CONFIG_PM_SLEEP
38 * CPU boot vector when restarting the a CPU following
39 * an LP2 transition. Also branched to by LP0 and LP1 resume after
46 check_cpu_part_num 0xc09, r8, r9
48 blne tegra_init_l2_for_a15
51 tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
60 /* Are we on Tegra20? */
63 /* Clear the flow controller flags for this CPU. */
65 mov32 r2, TEGRA_FLOW_CTRL_BASE
67 /* Clear event & intr flag */
69 #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
70 movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps
71 @ & ext flags for CPU power mgnt
79 #ifdef CONFIG_HAVE_ARM_SCU
81 mov32 r0, TEGRA_ARM_PERIF_BASE
87 /* L2 cache resume & re-enable */
88 l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
95 #ifdef CONFIG_CACHE_L2X0
96 .globl l2x0_saved_regs_addr
101 .align L1_CACHE_SHIFT
102 ENTRY(__tegra_cpu_reset_handler_start)
105 * __tegra_cpu_reset_handler:
107 * Common handler for all CPU reset events.
109 * Register usage within the reset handler:
113 * R7 = CPU present (to the OS) mask
114 * R8 = CPU in LP1 state mask
115 * R9 = CPU in LP2 state mask
118 * R12 = pointer to reset handler data
120 * NOTE: This code is copied to IRAM. All code and data accesses
121 * must be position-independent.
124 .align L1_CACHE_SHIFT
125 ENTRY(__tegra_cpu_reset_handler)
127 cpsid aif, 0x13 @ SVC mode, interrupts disabled
129 tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
130 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
135 # Tegra20 is a Cortex-A9 r1p1
136 mrc p15, 0, r0, c1, c0, 0 @ read system control register
137 orr r0, r0, #1 << 14 @ erratum 716044
138 mcr p15, 0, r0, c1, c0, 0 @ write system control register
139 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
140 orr r0, r0, #1 << 4 @ erratum 742230
141 orr r0, r0, #1 << 11 @ erratum 751472
142 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
146 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
151 # Tegra30 is a Cortex-A9 r2p9
152 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
153 orr r0, r0, #1 << 6 @ erratum 743622
154 orr r0, r0, #1 << 11 @ erratum 751472
155 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
160 mrc p15, 0, r10, c0, c0, 5 @ MPIDR
161 and r10, r10, #0x3 @ R10 = CPU number
163 mov r11, r11, lsl r10 @ R11 = CPU mask
164 adr r12, __tegra_cpu_reset_handler_data
167 /* Does the OS know about this CPU? */
168 ldr r7, [r12, #RESET_DATA(MASK_PRESENT)]
169 tst r7, r11 @ if !present
170 bleq __die @ CPU not present (to OS)
173 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
174 /* Are we on Tegra20? */
177 /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
178 mov32 r5, TEGRA_PMC_BASE
181 strne r0, [r5, #PMC_SCRATCH41]
185 /* Waking up from LP1? */
186 ldr r8, [r12, #RESET_DATA(MASK_LP1)]
187 tst r8, r11 @ if in_lp1
190 bne __die @ only CPU0 can be here
191 ldr lr, [r12, #RESET_DATA(STARTUP_LP1)]
193 bleq __die @ no LP1 startup handler
194 THUMB( add lr, lr, #1 ) @ switch to Thumb mode
198 /* Waking up from LP2? */
199 ldr r9, [r12, #RESET_DATA(MASK_LP2)]
200 tst r9, r11 @ if in_lp2
202 ldr lr, [r12, #RESET_DATA(STARTUP_LP2)]
204 bleq __die @ no LP2 startup handler
211 * Can only be secondary boot (initial or hotplug)
212 * CPU0 can't be here for Tegra20/30
217 bleq __die @ CPU0 cannot be here
219 ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
221 bleq __die @ no secondary startup handler
226 * We don't know why the CPU reset. Just kill it.
227 * The LR register will contain the address we died at + 4.
232 mov32 r7, TEGRA_PMC_BASE
233 str lr, [r7, #PMC_SCRATCH41]
235 mov32 r7, TEGRA_CLK_RESET_BASE
237 /* Are we on Tegra20? */
241 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
244 str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET
247 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
248 mov32 r6, TEGRA_FLOW_CTRL_BASE
251 moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS
252 moveq r2, #FLOW_CTRL_CPU0_CSR
253 movne r1, r10, lsl #3
254 addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
255 addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
257 /* Clear CPU "event" and "interrupt" flags and power gate
258 it when halting but not before it is in the "WFI" state. */
260 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
261 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
264 /* Unconditionally halt this CPU */
265 mov r0, #FLOW_CTRL_WAITEVENT
267 ldr r0, [r6, +r1] @ memory barrier
271 wfi @ CPU should be power gated here
273 /* If the CPU didn't power gate above just kill it's clock. */
276 str r0, [r7, #348] @ CLK_CPU_CMPLX_SET
279 /* If the CPU still isn't dead, just spin here. */
281 ENDPROC(__tegra_cpu_reset_handler)
283 .align L1_CACHE_SHIFT
284 .type __tegra_cpu_reset_handler_data, %object
285 .globl __tegra_cpu_reset_handler_data
286 __tegra_cpu_reset_handler_data:
287 .rept TEGRA_RESET_DATA_SIZE
290 .align L1_CACHE_SHIFT
292 ENTRY(__tegra_cpu_reset_handler_end)