| blob | 8a03e9a31a3f7e2c3570472c36d59a7737c6adc8 |
1 /*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #ifdef CONFIG_ARM_LPAE
23 #include "proc-v7-3level.S"
24 #else
25 #include "proc-v7-2level.S"
26 #endif
28 ENTRY(cpu_v7_proc_init)
29 mov pc, lr
30 ENDPROC(cpu_v7_proc_init)
32 ENTRY(cpu_v7_proc_fin)
33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
34 bic r0, r0, #0x1000 @ ...i............
35 bic r0, r0, #0x0006 @ .............ca.
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
37 mov pc, lr
38 ENDPROC(cpu_v7_proc_fin)
40 /*
41 * cpu_v7_reset(loc)
42 *
43 * Perform a soft reset of the system. Put the CPU into the
44 * same state as it would be if it had been reset, and branch
45 * to what would be the reset vector.
46 *
47 * - loc - location to jump to for soft reset
48 *
49 * This code must be executed using a flat identity mapping with
50 * caches disabled.
51 */
52 .align 5
53 .pushsection .idmap.text, "ax"
54 ENTRY(cpu_v7_reset)
55 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
56 bic r1, r1, #0x1 @ ...............m
57 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
59 isb
60 bx r0
61 ENDPROC(cpu_v7_reset)
62 .popsection
64 /*
65 * cpu_v7_do_idle()
66 *
67 * Idle the processor (eg, wait for interrupt).
68 *
69 * IRQs are already disabled.
70 */
71 ENTRY(cpu_v7_do_idle)
72 dsb @ WFI may enter a low-power mode
73 wfi
74 mov pc, lr
75 ENDPROC(cpu_v7_do_idle)
77 ENTRY(cpu_v7_dcache_clean_area)
78 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
79 ALT_UP_B(1f)
80 mov pc, lr
81 1: dcache_line_size r2, r3
82 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
83 add r0, r0, r2
84 subs r1, r1, r2
85 bhi 2b
86 dsb ishst
87 mov pc, lr
88 ENDPROC(cpu_v7_dcache_clean_area)
90 string cpu_v7_name, "ARMv7 Processor"
91 .align
93 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
94 .globl cpu_v7_suspend_size
95 .equ cpu_v7_suspend_size, 4 * 8
96 #ifdef CONFIG_ARM_CPU_SUSPEND
97 ENTRY(cpu_v7_do_suspend)
98 stmfd sp!, {r4 - r11, lr}
99 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
100 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
101 stmia r0!, {r4 - r5}
102 #ifdef CONFIG_MMU
103 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
104 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
105 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
106 #endif
107 mrc p15, 0, r8, c1, c0, 0 @ Control register
108 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
109 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
110 stmia r0, {r6 - r11}
111 ldmfd sp!, {r4 - r11, pc}
112 ENDPROC(cpu_v7_do_suspend)
114 ENTRY(cpu_v7_do_resume)
115 mov ip, #0
116 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
117 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
118 ldmia r0!, {r4 - r5}
119 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
120 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
121 ldmia r0, {r6 - r11}
122 #ifdef CONFIG_MMU
123 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
124 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
125 #ifndef CONFIG_ARM_LPAE
126 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
127 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
128 #endif
129 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
130 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
131 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
132 ldr r4, =PRRR @ PRRR
133 ldr r5, =NMRR @ NMRR
134 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
135 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
136 #endif /* CONFIG_MMU */
137 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
138 teq r4, r9 @ Is it already set?
139 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
140 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
141 isb
142 dsb
143 mov r0, r8 @ control register
144 b cpu_resume_mmu
145 ENDPROC(cpu_v7_do_resume)
146 #endif
148 #ifdef CONFIG_CPU_PJ4B
149 globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
150 globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
151 globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
152 globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
153 globl_equ cpu_pj4b_reset, cpu_v7_reset
154 #ifdef CONFIG_PJ4B_ERRATA_4742
155 ENTRY(cpu_pj4b_do_idle)
156 dsb @ WFI may enter a low-power mode
157 wfi
158 dsb @barrier
159 mov pc, lr
160 ENDPROC(cpu_pj4b_do_idle)
161 #else
162 globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
163 #endif
164 globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
165 globl_equ cpu_pj4b_do_suspend, cpu_v7_do_suspend
166 globl_equ cpu_pj4b_do_resume, cpu_v7_do_resume
167 globl_equ cpu_pj4b_suspend_size, cpu_v7_suspend_size
169 #endif
171 /*
172 * __v7_setup
173 *
174 * Initialise TLB, Caches, and MMU state ready to switch the MMU
175 * on. Return in r0 the new CP15 C1 control register setting.
176 *
177 * This should be able to cover all ARMv7 cores.
178 *
179 * It is assumed that:
180 * - cache type register is implemented
181 */
182 __v7_ca5mp_setup:
183 __v7_ca9mp_setup:
184 __v7_cr7mp_setup:
185 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
186 b 1f
187 __v7_ca7mp_setup:
188 __v7_ca15mp_setup:
189 mov r10, #0
190 1:
191 #ifdef CONFIG_SMP
192 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
193 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
194 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
195 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
196 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
197 mcreq p15, 0, r0, c1, c0, 1
198 #endif
199 b __v7_setup
201 __v7_pj4b_setup:
202 #ifdef CONFIG_CPU_PJ4B
204 /* Auxiliary Debug Modes Control 1 Register */
205 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
206 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
207 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
209 /* Auxiliary Debug Modes Control 2 Register */
210 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
211 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
212 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
213 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
214 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
215 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
216 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
218 /* Auxiliary Functional Modes Control Register 0 */
219 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
220 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
221 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
223 /* Auxiliary Debug Modes Control 0 Register */
224 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
226 /* Auxiliary Debug Modes Control 1 Register */
227 mrc p15, 1, r0, c15, c1, 1
228 orr r0, r0, #PJ4B_CLEAN_LINE
229 orr r0, r0, #PJ4B_INTER_PARITY
230 bic r0, r0, #PJ4B_STATIC_BP
231 mcr p15, 1, r0, c15, c1, 1
233 /* Auxiliary Debug Modes Control 2 Register */
234 mrc p15, 1, r0, c15, c1, 2
235 bic r0, r0, #PJ4B_FAST_LDR
236 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
237 mcr p15, 1, r0, c15, c1, 2
239 /* Auxiliary Functional Modes Control Register 0 */
240 mrc p15, 1, r0, c15, c2, 0
241 #ifdef CONFIG_SMP
242 orr r0, r0, #PJ4B_SMP_CFB
243 #endif
244 orr r0, r0, #PJ4B_L1_PAR_CHK
245 orr r0, r0, #PJ4B_BROADCAST_CACHE
246 mcr p15, 1, r0, c15, c2, 0
248 /* Auxiliary Debug Modes Control 0 Register */
249 mrc p15, 1, r0, c15, c1, 0
250 orr r0, r0, #PJ4B_WFI_WFE
251 mcr p15, 1, r0, c15, c1, 0
253 #endif /* CONFIG_CPU_PJ4B */
255 __v7_setup:
256 adr r12, __v7_setup_stack @ the local stack
257 stmia r12, {r0-r5, r7, r9, r11, lr}
258 bl v7_flush_dcache_louis
259 ldmia r12, {r0-r5, r7, r9, r11, lr}
261 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
262 and r10, r0, #0xff000000 @ ARM?
263 teq r10, #0x41000000
264 bne 3f
265 and r5, r0, #0x00f00000 @ variant
266 and r6, r0, #0x0000000f @ revision
267 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
268 ubfx r0, r0, #4, #12 @ primary part number
270 /* Cortex-A8 Errata */
271 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
272 teq r0, r10
273 bne 2f
274 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
276 teq r5, #0x00100000 @ only present in r1p*
277 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
278 orreq r10, r10, #(1 << 6) @ set IBE to 1
279 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
280 #endif
281 #ifdef CONFIG_ARM_ERRATA_458693
282 teq r6, #0x20 @ only present in r2p0
283 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
284 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
285 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
286 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
287 #endif
288 #ifdef CONFIG_ARM_ERRATA_460075
289 teq r6, #0x20 @ only present in r2p0
290 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
291 tsteq r10, #1 << 22
292 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
293 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
294 #endif
295 b 3f
297 /* Cortex-A9 Errata */
298 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
299 teq r0, r10
300 bne 3f
301 #ifdef CONFIG_ARM_ERRATA_742230
302 cmp r6, #0x22 @ only present up to r2p2
303 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
304 orrle r10, r10, #1 << 4 @ set bit #4
305 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
306 #endif
307 #ifdef CONFIG_ARM_ERRATA_742231
308 teq r6, #0x20 @ present in r2p0
309 teqne r6, #0x21 @ present in r2p1
310 teqne r6, #0x22 @ present in r2p2
311 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
312 orreq r10, r10, #1 << 12 @ set bit #12
313 orreq r10, r10, #1 << 22 @ set bit #22
314 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
315 #endif
316 #ifdef CONFIG_ARM_ERRATA_743622
317 teq r5, #0x00200000 @ only present in r2p*
318 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
319 orreq r10, r10, #1 << 6 @ set bit #6
320 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
321 #endif
322 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
323 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
324 ALT_UP_B(1f)
325 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
326 orrlt r10, r10, #1 << 11 @ set bit #11
327 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
328 1:
329 #endif
331 /* Cortex-A15 Errata */
332 3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
333 teq r0, r10
334 bne 4f
336 #ifdef CONFIG_ARM_ERRATA_773022
337 cmp r6, #0x4 @ only present up to r0p4
338 mrcle p15, 0, r10, c1, c0, 1 @ read aux control register
339 orrle r10, r10, #1 << 1 @ disable loop buffer
340 mcrle p15, 0, r10, c1, c0, 1 @ write aux control register
341 #endif
343 4: mov r10, #0
344 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
345 #ifdef CONFIG_MMU
346 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
347 v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
348 ldr r5, =PRRR @ PRRR
349 ldr r6, =NMRR @ NMRR
350 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
351 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
352 #endif
353 dsb @ Complete invalidations
354 #ifndef CONFIG_ARM_THUMBEE
355 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
356 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
357 teq r0, #(1 << 12) @ check if ThumbEE is present
358 bne 1f
359 mov r5, #0
360 mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
361 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
362 orr r0, r0, #1 @ set the 1st bit in order to
363 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
364 1:
365 #endif
366 adr r5, v7_crval
367 ldmia r5, {r5, r6}
368 #ifdef CONFIG_CPU_ENDIAN_BE8
369 orr r6, r6, #1 << 25 @ big-endian page tables
370 #endif
371 #ifdef CONFIG_SWP_EMULATE
372 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
373 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
374 #endif
375 mrc p15, 0, r0, c1, c0, 0 @ read control register
376 bic r0, r0, r5 @ clear bits them
377 orr r0, r0, r6 @ set them
378 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
379 mov pc, lr @ return to head.S:__ret
380 ENDPROC(__v7_setup)
382 .align 2
383 __v7_setup_stack:
384 .space 4 * 11 @ 11 registers
386 __INITDATA
388 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
389 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
390 #ifdef CONFIG_CPU_PJ4B
391 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
392 #endif
394 .section ".rodata"
396 string cpu_arch_name, "armv7"
397 string cpu_elf_name, "v7"
398 .align
400 .section ".proc.info.init", #alloc, #execinstr
402 /*
403 * Standard v7 proc info content
404 */
405 .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
406 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
407 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
408 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
409 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
410 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
411 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
412 W(b) \initfunc
413 .long cpu_arch_name
414 .long cpu_elf_name
415 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
416 HWCAP_EDSP | HWCAP_TLS | \hwcaps
417 .long cpu_v7_name
418 .long \proc_fns
419 .long v7wbi_tlb_fns
420 .long v6_user_fns
421 .long v7_cache_fns
422 .endm
424 #ifndef CONFIG_ARM_LPAE
425 /*
426 * ARM Ltd. Cortex A5 processor.
427 */
428 .type __v7_ca5mp_proc_info, #object
429 __v7_ca5mp_proc_info:
430 .long 0x410fc050
431 .long 0xff0ffff0
432 __v7_proc __v7_ca5mp_setup
433 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
435 /*
436 * ARM Ltd. Cortex A9 processor.
437 */
438 .type __v7_ca9mp_proc_info, #object
439 __v7_ca9mp_proc_info:
440 .long 0x410fc090
441 .long 0xff0ffff0
442 __v7_proc __v7_ca9mp_setup
443 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
445 #endif /* CONFIG_ARM_LPAE */
447 /*
448 * Marvell PJ4B processor.
449 */
450 #ifdef CONFIG_CPU_PJ4B
451 .type __v7_pj4b_proc_info, #object
452 __v7_pj4b_proc_info:
453 .long 0x560f5800
454 .long 0xff0fff00
455 __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
456 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
457 #endif
459 /*
460 * ARM Ltd. Cortex R7 processor.
461 */
462 .type __v7_cr7mp_proc_info, #object
463 __v7_cr7mp_proc_info:
464 .long 0x410fc170
465 .long 0xff0ffff0
466 __v7_proc __v7_cr7mp_setup
467 .size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
469 /*
470 * ARM Ltd. Cortex A7 processor.
471 */
472 .type __v7_ca7mp_proc_info, #object
473 __v7_ca7mp_proc_info:
474 .long 0x410fc070
475 .long 0xff0ffff0
476 __v7_proc __v7_ca7mp_setup
477 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
479 /*
480 * ARM Ltd. Cortex A15 processor.
481 */
482 .type __v7_ca15mp_proc_info, #object
483 __v7_ca15mp_proc_info:
484 .long 0x410fc0f0
485 .long 0xff0ffff0
486 __v7_proc __v7_ca15mp_setup
487 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
489 /*
490 * Qualcomm Inc. Krait processors.
491 */
492 .type __krait_proc_info, #object
493 __krait_proc_info:
494 .long 0x510f0400 @ Required ID value
495 .long 0xff0ffc00 @ Mask for ID
496 /*
497 * Some Krait processors don't indicate support for SDIV and UDIV
498 * instructions in the ARM instruction set, even though they actually
499 * do support them.
500 */
501 __v7_proc __v7_setup, hwcaps = HWCAP_IDIV
502 .size __krait_proc_info, . - __krait_proc_info
504 /*
505 * Match any ARMv7 processor core.
506 */
507 .type __v7_proc_info, #object
508 __v7_proc_info:
509 .long 0x000f0000 @ Required ID value
510 .long 0x000f0000 @ Mask for ID
511 __v7_proc __v7_setup
512 .size __v7_proc_info, . - __v7_proc_info