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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / arch / mips / include / asm / kvm_host.h
blob883a162083af1fbaa0da483b23acd778ca6385dd
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
8 */
9
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
12
13 #include <linux/mutex.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/types.h>
17 #include <linux/kvm.h>
18 #include <linux/kvm_types.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
21
22
23 #define KVM_MAX_VCPUS 1
24 #define KVM_USER_MEM_SLOTS 8
25 /* memory slots that does not exposed to userspace */
26 #define KVM_PRIVATE_MEM_SLOTS 0
27
28 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
29
30 /* Don't support huge pages */
31 #define KVM_HPAGE_GFN_SHIFT(x) 0
32
33 /* We don't currently support large pages. */
34 #define KVM_NR_PAGE_SIZES 1
35 #define KVM_PAGES_PER_HPAGE(x) 1
36
37
38
39 /* Special address that contains the comm page, used for reducing # of traps */
40 #define KVM_GUEST_COMMPAGE_ADDR 0x0
41
42 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
43 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
44
45 #define KVM_GUEST_KUSEG 0x00000000UL
46 #define KVM_GUEST_KSEG0 0x40000000UL
47 #define KVM_GUEST_KSEG23 0x60000000UL
48 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
49 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
50
51 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
52 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
53 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
54
55 /*
56 * Map an address to a certain kernel segment
57 */
58 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
59 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
60 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
61
62 #define KVM_INVALID_PAGE 0xdeadbeef
63 #define KVM_INVALID_INST 0xdeadbeef
64 #define KVM_INVALID_ADDR 0xdeadbeef
65
66 #define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL
67
68 #define GUEST_TICKS_PER_JIFFY (40000000/HZ)
69 #define MS_TO_NS(x) (x * 1E6L)
70
71 #define CAUSEB_DC 27
72 #define CAUSEF_DC (_ULCAST_(1) << 27)
73
74 struct kvm;
75 struct kvm_run;
76 struct kvm_vcpu;
77 struct kvm_interrupt;
78
79 extern atomic_t kvm_mips_instance;
80 extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn);
81 extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);
82 extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn);
83
84 struct kvm_vm_stat {
85 u32 remote_tlb_flush;
86 };
87
88 struct kvm_vcpu_stat {
89 u32 wait_exits;
90 u32 cache_exits;
91 u32 signal_exits;
92 u32 int_exits;
93 u32 cop_unusable_exits;
94 u32 tlbmod_exits;
95 u32 tlbmiss_ld_exits;
96 u32 tlbmiss_st_exits;
97 u32 addrerr_st_exits;
98 u32 addrerr_ld_exits;
99 u32 syscall_exits;
100 u32 resvd_inst_exits;
101 u32 break_inst_exits;
102 u32 flush_dcache_exits;
103 u32 halt_wakeup;
104 };
105
106 enum kvm_mips_exit_types {
107 WAIT_EXITS,
108 CACHE_EXITS,
109 SIGNAL_EXITS,
110 INT_EXITS,
111 COP_UNUSABLE_EXITS,
112 TLBMOD_EXITS,
113 TLBMISS_LD_EXITS,
114 TLBMISS_ST_EXITS,
115 ADDRERR_ST_EXITS,
116 ADDRERR_LD_EXITS,
117 SYSCALL_EXITS,
118 RESVD_INST_EXITS,
119 BREAK_INST_EXITS,
120 FLUSH_DCACHE_EXITS,
121 MAX_KVM_MIPS_EXIT_TYPES
122 };
123
124 struct kvm_arch_memory_slot {
125 };
126
127 struct kvm_arch {
128 /* Guest GVA->HPA page table */
129 unsigned long *guest_pmap;
130 unsigned long guest_pmap_npages;
131
132 /* Wired host TLB used for the commpage */
133 int commpage_tlb;
134 };
135
136 #define N_MIPS_COPROC_REGS 32
137 #define N_MIPS_COPROC_SEL 8
138
139 struct mips_coproc {
140 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
141 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
142 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
143 #endif
144 };
145
146 /*
147 * Coprocessor 0 register names
148 */
149 #define MIPS_CP0_TLB_INDEX 0
150 #define MIPS_CP0_TLB_RANDOM 1
151 #define MIPS_CP0_TLB_LOW 2
152 #define MIPS_CP0_TLB_LO0 2
153 #define MIPS_CP0_TLB_LO1 3
154 #define MIPS_CP0_TLB_CONTEXT 4
155 #define MIPS_CP0_TLB_PG_MASK 5
156 #define MIPS_CP0_TLB_WIRED 6
157 #define MIPS_CP0_HWRENA 7
158 #define MIPS_CP0_BAD_VADDR 8
159 #define MIPS_CP0_COUNT 9
160 #define MIPS_CP0_TLB_HI 10
161 #define MIPS_CP0_COMPARE 11
162 #define MIPS_CP0_STATUS 12
163 #define MIPS_CP0_CAUSE 13
164 #define MIPS_CP0_EXC_PC 14
165 #define MIPS_CP0_PRID 15
166 #define MIPS_CP0_CONFIG 16
167 #define MIPS_CP0_LLADDR 17
168 #define MIPS_CP0_WATCH_LO 18
169 #define MIPS_CP0_WATCH_HI 19
170 #define MIPS_CP0_TLB_XCONTEXT 20
171 #define MIPS_CP0_ECC 26
172 #define MIPS_CP0_CACHE_ERR 27
173 #define MIPS_CP0_TAG_LO 28
174 #define MIPS_CP0_TAG_HI 29
175 #define MIPS_CP0_ERROR_PC 30
176 #define MIPS_CP0_DEBUG 23
177 #define MIPS_CP0_DEPC 24
178 #define MIPS_CP0_PERFCNT 25
179 #define MIPS_CP0_ERRCTL 26
180 #define MIPS_CP0_DATA_LO 28
181 #define MIPS_CP0_DATA_HI 29
182 #define MIPS_CP0_DESAVE 31
183
184 #define MIPS_CP0_CONFIG_SEL 0
185 #define MIPS_CP0_CONFIG1_SEL 1
186 #define MIPS_CP0_CONFIG2_SEL 2
187 #define MIPS_CP0_CONFIG3_SEL 3
188
189 /* Config0 register bits */
190 #define CP0C0_M 31
191 #define CP0C0_K23 28
192 #define CP0C0_KU 25
193 #define CP0C0_MDU 20
194 #define CP0C0_MM 17
195 #define CP0C0_BM 16
196 #define CP0C0_BE 15
197 #define CP0C0_AT 13
198 #define CP0C0_AR 10
199 #define CP0C0_MT 7
200 #define CP0C0_VI 3
201 #define CP0C0_K0 0
202
203 /* Config1 register bits */
204 #define CP0C1_M 31
205 #define CP0C1_MMU 25
206 #define CP0C1_IS 22
207 #define CP0C1_IL 19
208 #define CP0C1_IA 16
209 #define CP0C1_DS 13
210 #define CP0C1_DL 10
211 #define CP0C1_DA 7
212 #define CP0C1_C2 6
213 #define CP0C1_MD 5
214 #define CP0C1_PC 4
215 #define CP0C1_WR 3
216 #define CP0C1_CA 2
217 #define CP0C1_EP 1
218 #define CP0C1_FP 0
219
220 /* Config2 Register bits */
221 #define CP0C2_M 31
222 #define CP0C2_TU 28
223 #define CP0C2_TS 24
224 #define CP0C2_TL 20
225 #define CP0C2_TA 16
226 #define CP0C2_SU 12
227 #define CP0C2_SS 8
228 #define CP0C2_SL 4
229 #define CP0C2_SA 0
230
231 /* Config3 Register bits */
232 #define CP0C3_M 31
233 #define CP0C3_ISA_ON_EXC 16
234 #define CP0C3_ULRI 13
235 #define CP0C3_DSPP 10
236 #define CP0C3_LPA 7
237 #define CP0C3_VEIC 6
238 #define CP0C3_VInt 5
239 #define CP0C3_SP 4
240 #define CP0C3_MT 2
241 #define CP0C3_SM 1
242 #define CP0C3_TL 0
243
244 /* Have config1, Cacheable, noncoherent, write-back, write allocate*/
245 #define MIPS_CONFIG0 \
246 ((1 << CP0C0_M) | (0x3 << CP0C0_K0))
247
248 /* Have config2, no coprocessor2 attached, no MDMX support attached,
249 no performance counters, watch registers present,
250 no code compression, EJTAG present, no FPU, no watch registers */
251 #define MIPS_CONFIG1 \
252 ((1 << CP0C1_M) | \
253 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
254 (0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
255 (0 << CP0C1_FP))
256
257 /* Have config3, no tertiary/secondary caches implemented */
258 #define MIPS_CONFIG2 \
259 ((1 << CP0C2_M))
260
261 /* No config4, no DSP ASE, no large physaddr (PABITS),
262 no external interrupt controller, no vectored interrupts,
263 no 1kb pages, no SmartMIPS ASE, no trace logic */
264 #define MIPS_CONFIG3 \
265 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
266 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
267 (0 << CP0C3_SM) | (0 << CP0C3_TL))
268
269 /* MMU types, the first four entries have the same layout as the
270 CP0C0_MT field. */
271 enum mips_mmu_types {
272 MMU_TYPE_NONE,
273 MMU_TYPE_R4000,
274 MMU_TYPE_RESERVED,
275 MMU_TYPE_FMT,
276 MMU_TYPE_R3000,
277 MMU_TYPE_R6000,
278 MMU_TYPE_R8000
279 };
280
281 /*
282 * Trap codes
283 */
284 #define T_INT 0 /* Interrupt pending */
285 #define T_TLB_MOD 1 /* TLB modified fault */
286 #define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
287 #define T_TLB_ST_MISS 3 /* TLB miss on a store */
288 #define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
289 #define T_ADDR_ERR_ST 5 /* Address error on a store */
290 #define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
291 #define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
292 #define T_SYSCALL 8 /* System call */
293 #define T_BREAK 9 /* Breakpoint */
294 #define T_RES_INST 10 /* Reserved instruction exception */
295 #define T_COP_UNUSABLE 11 /* Coprocessor unusable */
296 #define T_OVFLOW 12 /* Arithmetic overflow */
297
298 /*
299 * Trap definitions added for r4000 port.
300 */
301 #define T_TRAP 13 /* Trap instruction */
302 #define T_VCEI 14 /* Virtual coherency exception */
303 #define T_FPE 15 /* Floating point exception */
304 #define T_WATCH 23 /* Watch address reference */
305 #define T_VCED 31 /* Virtual coherency data */
306
307 /* Resume Flags */
308 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
309 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
310
311 #define RESUME_GUEST 0
312 #define RESUME_GUEST_DR RESUME_FLAG_DR
313 #define RESUME_HOST RESUME_FLAG_HOST
314
315 enum emulation_result {
316 EMULATE_DONE, /* no further processing */
317 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
318 EMULATE_FAIL, /* can't emulate this instruction */
319 EMULATE_WAIT, /* WAIT instruction */
320 EMULATE_PRIV_FAIL,
321 };
322
323 #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
324 #define MIPS3_PG_V 0x00000002 /* Valid */
325 #define MIPS3_PG_NV 0x00000000
326 #define MIPS3_PG_D 0x00000004 /* Dirty */
327
328 #define mips3_paddr_to_tlbpfn(x) \
329 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
330 #define mips3_tlbpfn_to_paddr(x) \
331 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
332
333 #define MIPS3_PG_SHIFT 6
334 #define MIPS3_PG_FRAME 0x3fffffc0
335
336 #define VPN2_MASK 0xffffe000
337 #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && ((x).tlb_lo1 & MIPS3_PG_G))
338 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
339 #define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
340 #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) ? ((x).tlb_lo1 & MIPS3_PG_V) : ((x).tlb_lo0 & MIPS3_PG_V))
341
342 struct kvm_mips_tlb {
343 long tlb_mask;
344 long tlb_hi;
345 long tlb_lo0;
346 long tlb_lo1;
347 };
348
349 #define KVM_MIPS_GUEST_TLB_SIZE 64
350 struct kvm_vcpu_arch {
351 void *host_ebase, *guest_ebase;
352 int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
353 unsigned long host_stack;
354 unsigned long host_gp;
355
356 /* Host CP0 registers used when handling exits from guest */
357 unsigned long host_cp0_badvaddr;
358 unsigned long host_cp0_cause;
359 unsigned long host_cp0_epc;
360 unsigned long host_cp0_entryhi;
361 uint32_t guest_inst;
362
363 /* GPRS */
364 unsigned long gprs[32];
365 unsigned long hi;
366 unsigned long lo;
367 unsigned long pc;
368
369 /* FPU State */
370 struct mips_fpu_struct fpu;
371
372 /* COP0 State */
373 struct mips_coproc *cop0;
374
375 /* Host KSEG0 address of the EI/DI offset */
376 void *kseg0_commpage;
377
378 u32 io_gpr; /* GPR used as IO source/target */
379
380 /* Used to calibrate the virutal count register for the guest */
381 int32_t host_cp0_count;
382
383 /* Bitmask of exceptions that are pending */
384 unsigned long pending_exceptions;
385
386 /* Bitmask of pending exceptions to be cleared */
387 unsigned long pending_exceptions_clr;
388
389 unsigned long pending_load_cause;
390
391 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
392 unsigned long preempt_entryhi;
393
394 /* S/W Based TLB for guest */
395 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
396
397 /* Cached guest kernel/user ASIDs */
398 uint32_t guest_user_asid[NR_CPUS];
399 uint32_t guest_kernel_asid[NR_CPUS];
400 struct mm_struct guest_kernel_mm, guest_user_mm;
401
402 struct kvm_mips_tlb shadow_tlb[NR_CPUS][KVM_MIPS_GUEST_TLB_SIZE];
403
404
405 struct hrtimer comparecount_timer;
406
407 int last_sched_cpu;
408
409 /* WAIT executed */
410 int wait;
411 };
412
413
414 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
415 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
416 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
417 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
418 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
419 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
420 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
421 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
422 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
423 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
424 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
425 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
426 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
427 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
428 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
429 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
430 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
431 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
432 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
433 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
434 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
435 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
436 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
437 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
438 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
439 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
440 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
441 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
442 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
443 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
444 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
445 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
446 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
447 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
448 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
449 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
450 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
451 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
452 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
453 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
454 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
455 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
456 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
457
458 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
459 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
460 #define kvm_set_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] |= (val))
461 #define kvm_clear_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] &= ~(val))
462 #define kvm_change_c0_guest_cause(cop0, change, val) \
463 { \
464 kvm_clear_c0_guest_cause(cop0, change); \
465 kvm_set_c0_guest_cause(cop0, ((val) & (change))); \
466 }
467 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
468 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
469 #define kvm_change_c0_guest_ebase(cop0, change, val) \
470 { \
471 kvm_clear_c0_guest_ebase(cop0, change); \
472 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
473 }
474
475
476 struct kvm_mips_callbacks {
477 int (*handle_cop_unusable) (struct kvm_vcpu *vcpu);
478 int (*handle_tlb_mod) (struct kvm_vcpu *vcpu);
479 int (*handle_tlb_ld_miss) (struct kvm_vcpu *vcpu);
480 int (*handle_tlb_st_miss) (struct kvm_vcpu *vcpu);
481 int (*handle_addr_err_st) (struct kvm_vcpu *vcpu);
482 int (*handle_addr_err_ld) (struct kvm_vcpu *vcpu);
483 int (*handle_syscall) (struct kvm_vcpu *vcpu);
484 int (*handle_res_inst) (struct kvm_vcpu *vcpu);
485 int (*handle_break) (struct kvm_vcpu *vcpu);
486 int (*vm_init) (struct kvm *kvm);
487 int (*vcpu_init) (struct kvm_vcpu *vcpu);
488 int (*vcpu_setup) (struct kvm_vcpu *vcpu);
489 gpa_t(*gva_to_gpa) (gva_t gva);
490 void (*queue_timer_int) (struct kvm_vcpu *vcpu);
491 void (*dequeue_timer_int) (struct kvm_vcpu *vcpu);
492 void (*queue_io_int) (struct kvm_vcpu *vcpu,
493 struct kvm_mips_interrupt *irq);
494 void (*dequeue_io_int) (struct kvm_vcpu *vcpu,
495 struct kvm_mips_interrupt *irq);
496 int (*irq_deliver) (struct kvm_vcpu *vcpu, unsigned int priority,
497 uint32_t cause);
498 int (*irq_clear) (struct kvm_vcpu *vcpu, unsigned int priority,
499 uint32_t cause);
500 };
501 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
502 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
503
504 /* Debug: dump vcpu state */
505 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
506
507 /* Trampoline ASM routine to start running in "Guest" context */
508 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
509
510 /* TLB handling */
511 uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
512
513 uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
514
515 uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
516
517 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
518 struct kvm_vcpu *vcpu);
519
520 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
521 struct kvm_vcpu *vcpu);
522
523 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
524 struct kvm_mips_tlb *tlb,
525 unsigned long *hpa0,
526 unsigned long *hpa1);
527
528 extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
529 uint32_t *opc,
530 struct kvm_run *run,
531 struct kvm_vcpu *vcpu);
532
533 extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
534 uint32_t *opc,
535 struct kvm_run *run,
536 struct kvm_vcpu *vcpu);
537
538 extern void kvm_mips_dump_host_tlbs(void);
539 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
540 extern void kvm_mips_dump_shadow_tlbs(struct kvm_vcpu *vcpu);
541 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
542 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
543 extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
544
545 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
546 unsigned long entryhi);
547 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
548 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
549 unsigned long gva);
550 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
551 struct kvm_vcpu *vcpu);
552 extern void kvm_shadow_tlb_put(struct kvm_vcpu *vcpu);
553 extern void kvm_shadow_tlb_load(struct kvm_vcpu *vcpu);
554 extern void kvm_local_flush_tlb_all(void);
555 extern void kvm_mips_init_shadow_tlb(struct kvm_vcpu *vcpu);
556 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
557 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
558 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
559
560 /* Emulation */
561 uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
562 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
563
564 extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
565 uint32_t *opc,
566 struct kvm_run *run,
567 struct kvm_vcpu *vcpu);
568
569 extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
570 uint32_t *opc,
571 struct kvm_run *run,
572 struct kvm_vcpu *vcpu);
573
574 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
575 uint32_t *opc,
576 struct kvm_run *run,
577 struct kvm_vcpu *vcpu);
578
579 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
580 uint32_t *opc,
581 struct kvm_run *run,
582 struct kvm_vcpu *vcpu);
583
584 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
585 uint32_t *opc,
586 struct kvm_run *run,
587 struct kvm_vcpu *vcpu);
588
589 extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
590 uint32_t *opc,
591 struct kvm_run *run,
592 struct kvm_vcpu *vcpu);
593
594 extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
595 uint32_t *opc,
596 struct kvm_run *run,
597 struct kvm_vcpu *vcpu);
598
599 extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
600 uint32_t *opc,
601 struct kvm_run *run,
602 struct kvm_vcpu *vcpu);
603
604 extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
605 uint32_t *opc,
606 struct kvm_run *run,
607 struct kvm_vcpu *vcpu);
608
609 extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
610 uint32_t *opc,
611 struct kvm_run *run,
612 struct kvm_vcpu *vcpu);
613
614 extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
615 uint32_t *opc,
616 struct kvm_run *run,
617 struct kvm_vcpu *vcpu);
618
619 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
620 struct kvm_run *run);
621
622 enum emulation_result kvm_mips_emulate_count(struct kvm_vcpu *vcpu);
623
624 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
625 uint32_t *opc,
626 struct kvm_run *run,
627 struct kvm_vcpu *vcpu);
628
629 enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
630 uint32_t *opc,
631 uint32_t cause,
632 struct kvm_run *run,
633 struct kvm_vcpu *vcpu);
634 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
635 uint32_t *opc,
636 uint32_t cause,
637 struct kvm_run *run,
638 struct kvm_vcpu *vcpu);
639 enum emulation_result kvm_mips_emulate_store(uint32_t inst,
640 uint32_t cause,
641 struct kvm_run *run,
642 struct kvm_vcpu *vcpu);
643 enum emulation_result kvm_mips_emulate_load(uint32_t inst,
644 uint32_t cause,
645 struct kvm_run *run,
646 struct kvm_vcpu *vcpu);
647
648 /* Dynamic binary translation */
649 extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
650 struct kvm_vcpu *vcpu);
651 extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
652 struct kvm_vcpu *vcpu);
653 extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
654 struct kvm_vcpu *vcpu);
655 extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
656 struct kvm_vcpu *vcpu);
657
658 /* Misc */
659 extern void mips32_SyncICache(unsigned long addr, unsigned long size);
660 extern int kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
661 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
662
663
664 #endif /* __MIPS_KVM_HOST_H__ */
Linux with added FPC-III support