2 * sleep.c - x86-specific ACPI sleep support.
4 * Copyright (C) 2001-2003 Patrick Mochel
5 * Copyright (C) 2001-2003 Pavel Machek <pavel@ucw.cz>
8 #include <linux/acpi.h>
9 #include <linux/bootmem.h>
10 #include <linux/memblock.h>
11 #include <linux/dmi.h>
12 #include <linux/cpumask.h>
13 #include <asm/segment.h>
15 #include <asm/pgtable.h>
16 #include <asm/cacheflush.h>
17 #include <asm/realmode.h>
19 #include <linux/ftrace.h>
20 #include "../../realmode/rm/wakeup.h"
23 unsigned long acpi_realmode_flags
;
25 #if defined(CONFIG_SMP) && defined(CONFIG_64BIT)
26 static char temp_stack
[4096];
30 * x86_acpi_suspend_lowlevel - save kernel state
32 * Create an identity mapped page table and copy the wakeup routine to
35 int x86_acpi_suspend_lowlevel(void)
37 struct wakeup_header
*header
=
38 (struct wakeup_header
*) __va(real_mode_header
->wakeup_header
);
40 if (header
->signature
!= WAKEUP_HEADER_SIGNATURE
) {
41 printk(KERN_ERR
"wakeup header does not match\n");
45 header
->video_mode
= saved_video_mode
;
47 header
->pmode_behavior
= 0;
50 native_store_gdt((struct desc_ptr
*)&header
->pmode_gdt
);
53 * We have to check that we can write back the value, and not
54 * just read it. At least on 90 nm Pentium M (Family 6, Model
55 * 13), reading an invalid MSR is not guaranteed to trap, see
56 * Erratum X4 in "Intel Pentium M Processor on 90 nm Process
57 * with 2-MB L2 Cache and IntelĀ® Processor A100 and A110 on 90
58 * nm process with 512-KB L2 Cache Specification Update".
60 if (!rdmsr_safe(MSR_EFER
,
61 &header
->pmode_efer_low
,
62 &header
->pmode_efer_high
) &&
64 header
->pmode_efer_low
,
65 header
->pmode_efer_high
))
66 header
->pmode_behavior
|= (1 << WAKEUP_BEHAVIOR_RESTORE_EFER
);
67 #endif /* !CONFIG_64BIT */
69 header
->pmode_cr0
= read_cr0();
70 if (__this_cpu_read(cpu_info
.cpuid_level
) >= 0) {
71 header
->pmode_cr4
= read_cr4();
72 header
->pmode_behavior
|= (1 << WAKEUP_BEHAVIOR_RESTORE_CR4
);
74 if (!rdmsr_safe(MSR_IA32_MISC_ENABLE
,
75 &header
->pmode_misc_en_low
,
76 &header
->pmode_misc_en_high
) &&
77 !wrmsr_safe(MSR_IA32_MISC_ENABLE
,
78 header
->pmode_misc_en_low
,
79 header
->pmode_misc_en_high
))
80 header
->pmode_behavior
|=
81 (1 << WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE
);
82 header
->realmode_flags
= acpi_realmode_flags
;
83 header
->real_magic
= 0x12345678;
86 header
->pmode_entry
= (u32
)&wakeup_pmode_return
;
87 header
->pmode_cr3
= (u32
)__pa_symbol(initial_page_table
);
88 saved_magic
= 0x12345678;
89 #else /* CONFIG_64BIT */
91 stack_start
= (unsigned long)temp_stack
+ sizeof(temp_stack
);
92 early_gdt_descr
.address
=
93 (unsigned long)get_cpu_gdt_table(smp_processor_id());
94 initial_gs
= per_cpu_offset(smp_processor_id());
96 initial_code
= (unsigned long)wakeup_long64
;
97 saved_magic
= 0x123456789abcdef0L
;
98 #endif /* CONFIG_64BIT */
101 * Pause/unpause graph tracing around do_suspend_lowlevel as it has
102 * inconsistent call/return info after it jumps to the wakeup vector.
104 pause_graph_tracing();
105 do_suspend_lowlevel();
106 unpause_graph_tracing();
110 static int __init
acpi_sleep_setup(char *str
)
112 while ((str
!= NULL
) && (*str
!= '\0')) {
113 if (strncmp(str
, "s3_bios", 7) == 0)
114 acpi_realmode_flags
|= 1;
115 if (strncmp(str
, "s3_mode", 7) == 0)
116 acpi_realmode_flags
|= 2;
117 if (strncmp(str
, "s3_beep", 7) == 0)
118 acpi_realmode_flags
|= 4;
119 #ifdef CONFIG_HIBERNATION
120 if (strncmp(str
, "s4_nohwsig", 10) == 0)
121 acpi_no_s4_hw_signature();
123 if (strncmp(str
, "nonvs", 5) == 0)
125 if (strncmp(str
, "nonvs_s3", 8) == 0)
126 acpi_nvs_nosave_s3();
127 if (strncmp(str
, "old_ordering", 12) == 0)
128 acpi_old_suspend_ordering();
129 str
= strchr(str
, ',');
131 str
+= strspn(str
, ", \t");
136 __setup("acpi_sleep=", acpi_sleep_setup
);