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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / arch / x86 / kvm / emulate.c
blobcad86cd56f826292481a6e23918937b75f1c0337
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
25 #include <linux/module.h>
26 #include <asm/kvm_emulate.h>
27 #include <linux/stringify.h>
28
29 #include "x86.h"
30 #include "tss.h"
31
32 /*
33 * Operand types
34 */
35 #define OpNone 0ull
36 #define OpImplicit 1ull /* No generic decode */
37 #define OpReg 2ull /* Register */
38 #define OpMem 3ull /* Memory */
39 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40 #define OpDI 5ull /* ES:DI/EDI/RDI */
41 #define OpMem64 6ull /* Memory, 64-bit */
42 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43 #define OpDX 8ull /* DX register */
44 #define OpCL 9ull /* CL register (for shifts) */
45 #define OpImmByte 10ull /* 8-bit sign extended immediate */
46 #define OpOne 11ull /* Implied 1 */
47 #define OpImm 12ull /* Sign extended up to 32-bit immediate */
48 #define OpMem16 13ull /* Memory operand (16-bit). */
49 #define OpMem32 14ull /* Memory operand (32-bit). */
50 #define OpImmU 15ull /* Immediate operand, zero extended */
51 #define OpSI 16ull /* SI/ESI/RSI */
52 #define OpImmFAddr 17ull /* Immediate far address */
53 #define OpMemFAddr 18ull /* Far address in memory */
54 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
55 #define OpES 20ull /* ES */
56 #define OpCS 21ull /* CS */
57 #define OpSS 22ull /* SS */
58 #define OpDS 23ull /* DS */
59 #define OpFS 24ull /* FS */
60 #define OpGS 25ull /* GS */
61 #define OpMem8 26ull /* 8-bit zero extended memory operand */
62 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
63 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
64 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
66
67 #define OpBits 5 /* Width of operand field */
68 #define OpMask ((1ull << OpBits) - 1)
69
70 /*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79 /* Operand sizes: 8-bit operands or specified/overridden size. */
80 #define ByteOp (1<<0) /* 8-bit operands. */
81 /* Destination operand type. */
82 #define DstShift 1
83 #define ImplicitOps (OpImplicit << DstShift)
84 #define DstReg (OpReg << DstShift)
85 #define DstMem (OpMem << DstShift)
86 #define DstAcc (OpAcc << DstShift)
87 #define DstDI (OpDI << DstShift)
88 #define DstMem64 (OpMem64 << DstShift)
89 #define DstImmUByte (OpImmUByte << DstShift)
90 #define DstDX (OpDX << DstShift)
91 #define DstAccLo (OpAccLo << DstShift)
92 #define DstMask (OpMask << DstShift)
93 /* Source operand type. */
94 #define SrcShift 6
95 #define SrcNone (OpNone << SrcShift)
96 #define SrcReg (OpReg << SrcShift)
97 #define SrcMem (OpMem << SrcShift)
98 #define SrcMem16 (OpMem16 << SrcShift)
99 #define SrcMem32 (OpMem32 << SrcShift)
100 #define SrcImm (OpImm << SrcShift)
101 #define SrcImmByte (OpImmByte << SrcShift)
102 #define SrcOne (OpOne << SrcShift)
103 #define SrcImmUByte (OpImmUByte << SrcShift)
104 #define SrcImmU (OpImmU << SrcShift)
105 #define SrcSI (OpSI << SrcShift)
106 #define SrcXLat (OpXLat << SrcShift)
107 #define SrcImmFAddr (OpImmFAddr << SrcShift)
108 #define SrcMemFAddr (OpMemFAddr << SrcShift)
109 #define SrcAcc (OpAcc << SrcShift)
110 #define SrcImmU16 (OpImmU16 << SrcShift)
111 #define SrcImm64 (OpImm64 << SrcShift)
112 #define SrcDX (OpDX << SrcShift)
113 #define SrcMem8 (OpMem8 << SrcShift)
114 #define SrcAccHi (OpAccHi << SrcShift)
115 #define SrcMask (OpMask << SrcShift)
116 #define BitOp (1<<11)
117 #define MemAbs (1<<12) /* Memory operand is absolute displacement */
118 #define String (1<<13) /* String instruction (rep capable) */
119 #define Stack (1<<14) /* Stack instruction (push/pop) */
120 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
125 #define Escape (5<<15) /* Escape to coprocessor instruction */
126 #define Sse (1<<18) /* SSE Vector instruction */
127 /* Generic ModRM decode. */
128 #define ModRM (1<<19)
129 /* Destination is only written; never read. */
130 #define Mov (1<<20)
131 /* Misc flags */
132 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
133 #define VendorSpecific (1<<22) /* Vendor specific instruction */
134 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
135 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
136 #define Undefined (1<<25) /* No Such Instruction */
137 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
138 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
139 #define No64 (1<<28)
140 #define PageTable (1 << 29) /* instruction used to write page table */
141 #define NotImpl (1 << 30) /* instruction is not implemented */
142 /* Source 2 operand type */
143 #define Src2Shift (31)
144 #define Src2None (OpNone << Src2Shift)
145 #define Src2Mem (OpMem << Src2Shift)
146 #define Src2CL (OpCL << Src2Shift)
147 #define Src2ImmByte (OpImmByte << Src2Shift)
148 #define Src2One (OpOne << Src2Shift)
149 #define Src2Imm (OpImm << Src2Shift)
150 #define Src2ES (OpES << Src2Shift)
151 #define Src2CS (OpCS << Src2Shift)
152 #define Src2SS (OpSS << Src2Shift)
153 #define Src2DS (OpDS << Src2Shift)
154 #define Src2FS (OpFS << Src2Shift)
155 #define Src2GS (OpGS << Src2Shift)
156 #define Src2Mask (OpMask << Src2Shift)
157 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */
158 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159 #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160 #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
161 #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
162 #define NoWrite ((u64)1 << 45) /* No writeback */
163 #define SrcWrite ((u64)1 << 46) /* Write back src operand */
164 #define NearBranch ((u64)1 << 52) /* Near branches */
165
166 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
167
168 #define X2(x...) x, x
169 #define X3(x...) X2(x), x
170 #define X4(x...) X2(x), X2(x)
171 #define X5(x...) X4(x), x
172 #define X6(x...) X4(x), X2(x)
173 #define X7(x...) X4(x), X3(x)
174 #define X8(x...) X4(x), X4(x)
175 #define X16(x...) X8(x), X8(x)
176
177 #define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
178 #define FASTOP_SIZE 8
179
180 /*
181 * fastop functions have a special calling convention:
182 *
183 * dst: rax (in/out)
184 * src: rdx (in/out)
185 * src2: rcx (in)
186 * flags: rflags (in/out)
187 * ex: rsi (in:fastop pointer, out:zero if exception)
188 *
189 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
190 * different operand sizes can be reached by calculation, rather than a jump
191 * table (which would be bigger than the code).
192 *
193 * fastop functions are declared as taking a never-defined fastop parameter,
194 * so they can't be called from C directly.
195 */
196
197 struct fastop;
198
199 struct opcode {
200 u64 flags : 56;
201 u64 intercept : 8;
202 union {
203 int (*execute)(struct x86_emulate_ctxt *ctxt);
204 const struct opcode *group;
205 const struct group_dual *gdual;
206 const struct gprefix *gprefix;
207 const struct escape *esc;
208 void (*fastop)(struct fastop *fake);
209 } u;
210 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
211 };
212
213 struct group_dual {
214 struct opcode mod012[8];
215 struct opcode mod3[8];
216 };
217
218 struct gprefix {
219 struct opcode pfx_no;
220 struct opcode pfx_66;
221 struct opcode pfx_f2;
222 struct opcode pfx_f3;
223 };
224
225 struct escape {
226 struct opcode op[8];
227 struct opcode high[64];
228 };
229
230 /* EFLAGS bit definitions. */
231 #define EFLG_ID (1<<21)
232 #define EFLG_VIP (1<<20)
233 #define EFLG_VIF (1<<19)
234 #define EFLG_AC (1<<18)
235 #define EFLG_VM (1<<17)
236 #define EFLG_RF (1<<16)
237 #define EFLG_IOPL (3<<12)
238 #define EFLG_NT (1<<14)
239 #define EFLG_OF (1<<11)
240 #define EFLG_DF (1<<10)
241 #define EFLG_IF (1<<9)
242 #define EFLG_TF (1<<8)
243 #define EFLG_SF (1<<7)
244 #define EFLG_ZF (1<<6)
245 #define EFLG_AF (1<<4)
246 #define EFLG_PF (1<<2)
247 #define EFLG_CF (1<<0)
248
249 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
250 #define EFLG_RESERVED_ONE_MASK 2
251
252 static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
253 {
254 if (!(ctxt->regs_valid & (1 << nr))) {
255 ctxt->regs_valid |= 1 << nr;
256 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
257 }
258 return ctxt->_regs[nr];
259 }
260
261 static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
262 {
263 ctxt->regs_valid |= 1 << nr;
264 ctxt->regs_dirty |= 1 << nr;
265 return &ctxt->_regs[nr];
266 }
267
268 static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
269 {
270 reg_read(ctxt, nr);
271 return reg_write(ctxt, nr);
272 }
273
274 static void writeback_registers(struct x86_emulate_ctxt *ctxt)
275 {
276 unsigned reg;
277
278 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
279 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
280 }
281
282 static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
283 {
284 ctxt->regs_dirty = 0;
285 ctxt->regs_valid = 0;
286 }
287
288 /*
289 * These EFLAGS bits are restored from saved value during emulation, and
290 * any changes are written back to the saved value after emulation.
291 */
292 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
293
294 #ifdef CONFIG_X86_64
295 #define ON64(x) x
296 #else
297 #define ON64(x)
298 #endif
299
300 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
301
302 #define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
303 #define FOP_RET "ret \n\t"
304
305 #define FOP_START(op) \
306 extern void em_##op(struct fastop *fake); \
307 asm(".pushsection .text, \"ax\" \n\t" \
308 ".global em_" #op " \n\t" \
309 FOP_ALIGN \
310 "em_" #op ": \n\t"
311
312 #define FOP_END \
313 ".popsection")
314
315 #define FOPNOP() FOP_ALIGN FOP_RET
316
317 #define FOP1E(op, dst) \
318 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
319
320 #define FOP1EEX(op, dst) \
321 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
322
323 #define FASTOP1(op) \
324 FOP_START(op) \
325 FOP1E(op##b, al) \
326 FOP1E(op##w, ax) \
327 FOP1E(op##l, eax) \
328 ON64(FOP1E(op##q, rax)) \
329 FOP_END
330
331 /* 1-operand, using src2 (for MUL/DIV r/m) */
332 #define FASTOP1SRC2(op, name) \
333 FOP_START(name) \
334 FOP1E(op, cl) \
335 FOP1E(op, cx) \
336 FOP1E(op, ecx) \
337 ON64(FOP1E(op, rcx)) \
338 FOP_END
339
340 /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
341 #define FASTOP1SRC2EX(op, name) \
342 FOP_START(name) \
343 FOP1EEX(op, cl) \
344 FOP1EEX(op, cx) \
345 FOP1EEX(op, ecx) \
346 ON64(FOP1EEX(op, rcx)) \
347 FOP_END
348
349 #define FOP2E(op, dst, src) \
350 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
351
352 #define FASTOP2(op) \
353 FOP_START(op) \
354 FOP2E(op##b, al, dl) \
355 FOP2E(op##w, ax, dx) \
356 FOP2E(op##l, eax, edx) \
357 ON64(FOP2E(op##q, rax, rdx)) \
358 FOP_END
359
360 /* 2 operand, word only */
361 #define FASTOP2W(op) \
362 FOP_START(op) \
363 FOPNOP() \
364 FOP2E(op##w, ax, dx) \
365 FOP2E(op##l, eax, edx) \
366 ON64(FOP2E(op##q, rax, rdx)) \
367 FOP_END
368
369 /* 2 operand, src is CL */
370 #define FASTOP2CL(op) \
371 FOP_START(op) \
372 FOP2E(op##b, al, cl) \
373 FOP2E(op##w, ax, cl) \
374 FOP2E(op##l, eax, cl) \
375 ON64(FOP2E(op##q, rax, cl)) \
376 FOP_END
377
378 #define FOP3E(op, dst, src, src2) \
379 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
380
381 /* 3-operand, word-only, src2=cl */
382 #define FASTOP3WCL(op) \
383 FOP_START(op) \
384 FOPNOP() \
385 FOP3E(op##w, ax, dx, cl) \
386 FOP3E(op##l, eax, edx, cl) \
387 ON64(FOP3E(op##q, rax, rdx, cl)) \
388 FOP_END
389
390 /* Special case for SETcc - 1 instruction per cc */
391 #define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
392
393 asm(".global kvm_fastop_exception \n"
394 "kvm_fastop_exception: xor %esi, %esi; ret");
395
396 FOP_START(setcc)
397 FOP_SETCC(seto)
398 FOP_SETCC(setno)
399 FOP_SETCC(setc)
400 FOP_SETCC(setnc)
401 FOP_SETCC(setz)
402 FOP_SETCC(setnz)
403 FOP_SETCC(setbe)
404 FOP_SETCC(setnbe)
405 FOP_SETCC(sets)
406 FOP_SETCC(setns)
407 FOP_SETCC(setp)
408 FOP_SETCC(setnp)
409 FOP_SETCC(setl)
410 FOP_SETCC(setnl)
411 FOP_SETCC(setle)
412 FOP_SETCC(setnle)
413 FOP_END;
414
415 FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
416 FOP_END;
417
418 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
419 enum x86_intercept intercept,
420 enum x86_intercept_stage stage)
421 {
422 struct x86_instruction_info info = {
423 .intercept = intercept,
424 .rep_prefix = ctxt->rep_prefix,
425 .modrm_mod = ctxt->modrm_mod,
426 .modrm_reg = ctxt->modrm_reg,
427 .modrm_rm = ctxt->modrm_rm,
428 .src_val = ctxt->src.val64,
429 .src_bytes = ctxt->src.bytes,
430 .dst_bytes = ctxt->dst.bytes,
431 .ad_bytes = ctxt->ad_bytes,
432 .next_rip = ctxt->eip,
433 };
434
435 return ctxt->ops->intercept(ctxt, &info, stage);
436 }
437
438 static void assign_masked(ulong *dest, ulong src, ulong mask)
439 {
440 *dest = (*dest & ~mask) | (src & mask);
441 }
442
443 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
444 {
445 return (1UL << (ctxt->ad_bytes << 3)) - 1;
446 }
447
448 static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
449 {
450 u16 sel;
451 struct desc_struct ss;
452
453 if (ctxt->mode == X86EMUL_MODE_PROT64)
454 return ~0UL;
455 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
456 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
457 }
458
459 static int stack_size(struct x86_emulate_ctxt *ctxt)
460 {
461 return (__fls(stack_mask(ctxt)) + 1) >> 3;
462 }
463
464 /* Access/update address held in a register, based on addressing mode. */
465 static inline unsigned long
466 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
467 {
468 if (ctxt->ad_bytes == sizeof(unsigned long))
469 return reg;
470 else
471 return reg & ad_mask(ctxt);
472 }
473
474 static inline unsigned long
475 register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
476 {
477 return address_mask(ctxt, reg);
478 }
479
480 static void masked_increment(ulong *reg, ulong mask, int inc)
481 {
482 assign_masked(reg, *reg + inc, mask);
483 }
484
485 static inline void
486 register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
487 {
488 ulong mask;
489
490 if (ctxt->ad_bytes == sizeof(unsigned long))
491 mask = ~0UL;
492 else
493 mask = ad_mask(ctxt);
494 masked_increment(reg, mask, inc);
495 }
496
497 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
498 {
499 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
500 }
501
502 static u32 desc_limit_scaled(struct desc_struct *desc)
503 {
504 u32 limit = get_desc_limit(desc);
505
506 return desc->g ? (limit << 12) | 0xfff : limit;
507 }
508
509 static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
510 {
511 ctxt->has_seg_override = true;
512 ctxt->seg_override = seg;
513 }
514
515 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
516 {
517 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
518 return 0;
519
520 return ctxt->ops->get_cached_segment_base(ctxt, seg);
521 }
522
523 static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
524 {
525 if (!ctxt->has_seg_override)
526 return 0;
527
528 return ctxt->seg_override;
529 }
530
531 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
532 u32 error, bool valid)
533 {
534 ctxt->exception.vector = vec;
535 ctxt->exception.error_code = error;
536 ctxt->exception.error_code_valid = valid;
537 return X86EMUL_PROPAGATE_FAULT;
538 }
539
540 static int emulate_db(struct x86_emulate_ctxt *ctxt)
541 {
542 return emulate_exception(ctxt, DB_VECTOR, 0, false);
543 }
544
545 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
546 {
547 return emulate_exception(ctxt, GP_VECTOR, err, true);
548 }
549
550 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
551 {
552 return emulate_exception(ctxt, SS_VECTOR, err, true);
553 }
554
555 static int emulate_ud(struct x86_emulate_ctxt *ctxt)
556 {
557 return emulate_exception(ctxt, UD_VECTOR, 0, false);
558 }
559
560 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
561 {
562 return emulate_exception(ctxt, TS_VECTOR, err, true);
563 }
564
565 static int emulate_de(struct x86_emulate_ctxt *ctxt)
566 {
567 return emulate_exception(ctxt, DE_VECTOR, 0, false);
568 }
569
570 static int emulate_nm(struct x86_emulate_ctxt *ctxt)
571 {
572 return emulate_exception(ctxt, NM_VECTOR, 0, false);
573 }
574
575 static inline int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
576 int cs_l)
577 {
578 switch (ctxt->op_bytes) {
579 case 2:
580 ctxt->_eip = (u16)dst;
581 break;
582 case 4:
583 ctxt->_eip = (u32)dst;
584 break;
585 #ifdef CONFIG_X86_64
586 case 8:
587 if ((cs_l && is_noncanonical_address(dst)) ||
588 (!cs_l && (dst >> 32) != 0))
589 return emulate_gp(ctxt, 0);
590 ctxt->_eip = dst;
591 break;
592 #endif
593 default:
594 WARN(1, "unsupported eip assignment size\n");
595 }
596 return X86EMUL_CONTINUE;
597 }
598
599 static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
600 {
601 return assign_eip_far(ctxt, dst, ctxt->mode == X86EMUL_MODE_PROT64);
602 }
603
604 static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
605 {
606 return assign_eip_near(ctxt, ctxt->_eip + rel);
607 }
608
609 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
610 {
611 u16 selector;
612 struct desc_struct desc;
613
614 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
615 return selector;
616 }
617
618 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
619 unsigned seg)
620 {
621 u16 dummy;
622 u32 base3;
623 struct desc_struct desc;
624
625 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
626 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
627 }
628
629 /*
630 * x86 defines three classes of vector instructions: explicitly
631 * aligned, explicitly unaligned, and the rest, which change behaviour
632 * depending on whether they're AVX encoded or not.
633 *
634 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
635 * subject to the same check.
636 */
637 static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
638 {
639 if (likely(size < 16))
640 return false;
641
642 if (ctxt->d & Aligned)
643 return true;
644 else if (ctxt->d & Unaligned)
645 return false;
646 else if (ctxt->d & Avx)
647 return false;
648 else
649 return true;
650 }
651
652 static int __linearize(struct x86_emulate_ctxt *ctxt,
653 struct segmented_address addr,
654 unsigned size, bool write, bool fetch,
655 ulong *linear)
656 {
657 struct desc_struct desc;
658 bool usable;
659 ulong la;
660 u32 lim;
661 u16 sel;
662 unsigned cpl;
663
664 la = seg_base(ctxt, addr.seg) + addr.ea;
665 switch (ctxt->mode) {
666 case X86EMUL_MODE_PROT64:
667 if (is_noncanonical_address(la))
668 return emulate_gp(ctxt, 0);
669 break;
670 default:
671 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
672 addr.seg);
673 if (!usable)
674 goto bad;
675 /* code segment in protected mode or read-only data segment */
676 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
677 || !(desc.type & 2)) && write)
678 goto bad;
679 /* unreadable code segment */
680 if (!fetch && (desc.type & 8) && !(desc.type & 2))
681 goto bad;
682 lim = desc_limit_scaled(&desc);
683 if ((desc.type & 8) || !(desc.type & 4)) {
684 /* expand-up segment */
685 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
686 goto bad;
687 } else {
688 /* expand-down segment */
689 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
690 goto bad;
691 lim = desc.d ? 0xffffffff : 0xffff;
692 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
693 goto bad;
694 }
695 cpl = ctxt->ops->cpl(ctxt);
696 if (!(desc.type & 8)) {
697 /* data segment */
698 if (cpl > desc.dpl)
699 goto bad;
700 } else if ((desc.type & 8) && !(desc.type & 4)) {
701 /* nonconforming code segment */
702 if (cpl != desc.dpl)
703 goto bad;
704 } else if ((desc.type & 8) && (desc.type & 4)) {
705 /* conforming code segment */
706 if (cpl < desc.dpl)
707 goto bad;
708 }
709 break;
710 }
711 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
712 la &= (u32)-1;
713 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
714 return emulate_gp(ctxt, 0);
715 *linear = la;
716 return X86EMUL_CONTINUE;
717 bad:
718 if (addr.seg == VCPU_SREG_SS)
719 return emulate_ss(ctxt, sel);
720 else
721 return emulate_gp(ctxt, sel);
722 }
723
724 static int linearize(struct x86_emulate_ctxt *ctxt,
725 struct segmented_address addr,
726 unsigned size, bool write,
727 ulong *linear)
728 {
729 return __linearize(ctxt, addr, size, write, false, linear);
730 }
731
732
733 static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
734 struct segmented_address addr,
735 void *data,
736 unsigned size)
737 {
738 int rc;
739 ulong linear;
740
741 rc = linearize(ctxt, addr, size, false, &linear);
742 if (rc != X86EMUL_CONTINUE)
743 return rc;
744 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
745 }
746
747 /*
748 * Fetch the next byte of the instruction being emulated which is pointed to
749 * by ctxt->_eip, then increment ctxt->_eip.
750 *
751 * Also prefetch the remaining bytes of the instruction without crossing page
752 * boundary if they are not in fetch_cache yet.
753 */
754 static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
755 {
756 struct fetch_cache *fc = &ctxt->fetch;
757 int rc;
758 int size, cur_size;
759
760 if (ctxt->_eip == fc->end) {
761 unsigned long linear;
762 struct segmented_address addr = { .seg = VCPU_SREG_CS,
763 .ea = ctxt->_eip };
764 cur_size = fc->end - fc->start;
765 size = min(15UL - cur_size,
766 PAGE_SIZE - offset_in_page(ctxt->_eip));
767 rc = __linearize(ctxt, addr, size, false, true, &linear);
768 if (unlikely(rc != X86EMUL_CONTINUE))
769 return rc;
770 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
771 size, &ctxt->exception);
772 if (unlikely(rc != X86EMUL_CONTINUE))
773 return rc;
774 fc->end += size;
775 }
776 *dest = fc->data[ctxt->_eip - fc->start];
777 ctxt->_eip++;
778 return X86EMUL_CONTINUE;
779 }
780
781 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
782 void *dest, unsigned size)
783 {
784 int rc;
785
786 /* x86 instructions are limited to 15 bytes. */
787 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
788 return X86EMUL_UNHANDLEABLE;
789 while (size--) {
790 rc = do_insn_fetch_byte(ctxt, dest++);
791 if (rc != X86EMUL_CONTINUE)
792 return rc;
793 }
794 return X86EMUL_CONTINUE;
795 }
796
797 /* Fetch next part of the instruction being emulated. */
798 #define insn_fetch(_type, _ctxt) \
799 ({ unsigned long _x; \
800 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
801 if (rc != X86EMUL_CONTINUE) \
802 goto done; \
803 (_type)_x; \
804 })
805
806 #define insn_fetch_arr(_arr, _size, _ctxt) \
807 ({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
808 if (rc != X86EMUL_CONTINUE) \
809 goto done; \
810 })
811
812 /*
813 * Given the 'reg' portion of a ModRM byte, and a register block, return a
814 * pointer into the block that addresses the relevant register.
815 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
816 */
817 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
818 int highbyte_regs)
819 {
820 void *p;
821
822 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
823 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
824 else
825 p = reg_rmw(ctxt, modrm_reg);
826 return p;
827 }
828
829 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
830 struct segmented_address addr,
831 u16 *size, unsigned long *address, int op_bytes)
832 {
833 int rc;
834
835 if (op_bytes == 2)
836 op_bytes = 3;
837 *address = 0;
838 rc = segmented_read_std(ctxt, addr, size, 2);
839 if (rc != X86EMUL_CONTINUE)
840 return rc;
841 addr.ea += 2;
842 rc = segmented_read_std(ctxt, addr, address, op_bytes);
843 return rc;
844 }
845
846 FASTOP2(add);
847 FASTOP2(or);
848 FASTOP2(adc);
849 FASTOP2(sbb);
850 FASTOP2(and);
851 FASTOP2(sub);
852 FASTOP2(xor);
853 FASTOP2(cmp);
854 FASTOP2(test);
855
856 FASTOP1SRC2(mul, mul_ex);
857 FASTOP1SRC2(imul, imul_ex);
858 FASTOP1SRC2EX(div, div_ex);
859 FASTOP1SRC2EX(idiv, idiv_ex);
860
861 FASTOP3WCL(shld);
862 FASTOP3WCL(shrd);
863
864 FASTOP2W(imul);
865
866 FASTOP1(not);
867 FASTOP1(neg);
868 FASTOP1(inc);
869 FASTOP1(dec);
870
871 FASTOP2CL(rol);
872 FASTOP2CL(ror);
873 FASTOP2CL(rcl);
874 FASTOP2CL(rcr);
875 FASTOP2CL(shl);
876 FASTOP2CL(shr);
877 FASTOP2CL(sar);
878
879 FASTOP2W(bsf);
880 FASTOP2W(bsr);
881 FASTOP2W(bt);
882 FASTOP2W(bts);
883 FASTOP2W(btr);
884 FASTOP2W(btc);
885
886 FASTOP2(xadd);
887
888 static u8 test_cc(unsigned int condition, unsigned long flags)
889 {
890 u8 rc;
891 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
892
893 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
894 asm("push %[flags]; popf; call *%[fastop]"
895 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
896 return rc;
897 }
898
899 static void fetch_register_operand(struct operand *op)
900 {
901 switch (op->bytes) {
902 case 1:
903 op->val = *(u8 *)op->addr.reg;
904 break;
905 case 2:
906 op->val = *(u16 *)op->addr.reg;
907 break;
908 case 4:
909 op->val = *(u32 *)op->addr.reg;
910 break;
911 case 8:
912 op->val = *(u64 *)op->addr.reg;
913 break;
914 }
915 }
916
917 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
918 {
919 ctxt->ops->get_fpu(ctxt);
920 switch (reg) {
921 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
922 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
923 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
924 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
925 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
926 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
927 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
928 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
929 #ifdef CONFIG_X86_64
930 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
931 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
932 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
933 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
934 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
935 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
936 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
937 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
938 #endif
939 default: BUG();
940 }
941 ctxt->ops->put_fpu(ctxt);
942 }
943
944 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
945 int reg)
946 {
947 ctxt->ops->get_fpu(ctxt);
948 switch (reg) {
949 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
950 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
951 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
952 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
953 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
954 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
955 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
956 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
957 #ifdef CONFIG_X86_64
958 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
959 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
960 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
961 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
962 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
963 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
964 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
965 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
966 #endif
967 default: BUG();
968 }
969 ctxt->ops->put_fpu(ctxt);
970 }
971
972 static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
973 {
974 ctxt->ops->get_fpu(ctxt);
975 switch (reg) {
976 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
977 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
978 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
979 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
980 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
981 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
982 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
983 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
984 default: BUG();
985 }
986 ctxt->ops->put_fpu(ctxt);
987 }
988
989 static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
990 {
991 ctxt->ops->get_fpu(ctxt);
992 switch (reg) {
993 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
994 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
995 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
996 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
997 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
998 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
999 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1000 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1001 default: BUG();
1002 }
1003 ctxt->ops->put_fpu(ctxt);
1004 }
1005
1006 static int em_fninit(struct x86_emulate_ctxt *ctxt)
1007 {
1008 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1009 return emulate_nm(ctxt);
1010
1011 ctxt->ops->get_fpu(ctxt);
1012 asm volatile("fninit");
1013 ctxt->ops->put_fpu(ctxt);
1014 return X86EMUL_CONTINUE;
1015 }
1016
1017 static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1018 {
1019 u16 fcw;
1020
1021 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1022 return emulate_nm(ctxt);
1023
1024 ctxt->ops->get_fpu(ctxt);
1025 asm volatile("fnstcw %0": "+m"(fcw));
1026 ctxt->ops->put_fpu(ctxt);
1027
1028 /* force 2 byte destination */
1029 ctxt->dst.bytes = 2;
1030 ctxt->dst.val = fcw;
1031
1032 return X86EMUL_CONTINUE;
1033 }
1034
1035 static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1036 {
1037 u16 fsw;
1038
1039 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1040 return emulate_nm(ctxt);
1041
1042 ctxt->ops->get_fpu(ctxt);
1043 asm volatile("fnstsw %0": "+m"(fsw));
1044 ctxt->ops->put_fpu(ctxt);
1045
1046 /* force 2 byte destination */
1047 ctxt->dst.bytes = 2;
1048 ctxt->dst.val = fsw;
1049
1050 return X86EMUL_CONTINUE;
1051 }
1052
1053 static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
1054 struct operand *op)
1055 {
1056 unsigned reg = ctxt->modrm_reg;
1057 int highbyte_regs = ctxt->rex_prefix == 0;
1058
1059 if (!(ctxt->d & ModRM))
1060 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1061
1062 if (ctxt->d & Sse) {
1063 op->type = OP_XMM;
1064 op->bytes = 16;
1065 op->addr.xmm = reg;
1066 read_sse_reg(ctxt, &op->vec_val, reg);
1067 return;
1068 }
1069 if (ctxt->d & Mmx) {
1070 reg &= 7;
1071 op->type = OP_MM;
1072 op->bytes = 8;
1073 op->addr.mm = reg;
1074 return;
1075 }
1076
1077 op->type = OP_REG;
1078 if (ctxt->d & ByteOp) {
1079 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
1080 op->bytes = 1;
1081 } else {
1082 op->addr.reg = decode_register(ctxt, reg, 0);
1083 op->bytes = ctxt->op_bytes;
1084 }
1085 fetch_register_operand(op);
1086 op->orig_val = op->val;
1087 }
1088
1089 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1090 {
1091 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1092 ctxt->modrm_seg = VCPU_SREG_SS;
1093 }
1094
1095 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
1096 struct operand *op)
1097 {
1098 u8 sib;
1099 int index_reg = 0, base_reg = 0, scale;
1100 int rc = X86EMUL_CONTINUE;
1101 ulong modrm_ea = 0;
1102
1103 if (ctxt->rex_prefix) {
1104 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1105 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1106 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1107 }
1108
1109 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1110 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1111 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1112 ctxt->modrm_seg = VCPU_SREG_DS;
1113
1114 if (ctxt->modrm_mod == 3) {
1115 int highbyte_regs = ctxt->rex_prefix == 0;
1116
1117 op->type = OP_REG;
1118 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1119 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
1120 highbyte_regs && (ctxt->d & ByteOp));
1121 if (ctxt->d & Sse) {
1122 op->type = OP_XMM;
1123 op->bytes = 16;
1124 op->addr.xmm = ctxt->modrm_rm;
1125 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1126 return rc;
1127 }
1128 if (ctxt->d & Mmx) {
1129 op->type = OP_MM;
1130 op->bytes = 8;
1131 op->addr.xmm = ctxt->modrm_rm & 7;
1132 return rc;
1133 }
1134 fetch_register_operand(op);
1135 return rc;
1136 }
1137
1138 op->type = OP_MEM;
1139
1140 if (ctxt->ad_bytes == 2) {
1141 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1142 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1143 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1144 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1145
1146 /* 16-bit ModR/M decode. */
1147 switch (ctxt->modrm_mod) {
1148 case 0:
1149 if (ctxt->modrm_rm == 6)
1150 modrm_ea += insn_fetch(u16, ctxt);
1151 break;
1152 case 1:
1153 modrm_ea += insn_fetch(s8, ctxt);
1154 break;
1155 case 2:
1156 modrm_ea += insn_fetch(u16, ctxt);
1157 break;
1158 }
1159 switch (ctxt->modrm_rm) {
1160 case 0:
1161 modrm_ea += bx + si;
1162 break;
1163 case 1:
1164 modrm_ea += bx + di;
1165 break;
1166 case 2:
1167 modrm_ea += bp + si;
1168 break;
1169 case 3:
1170 modrm_ea += bp + di;
1171 break;
1172 case 4:
1173 modrm_ea += si;
1174 break;
1175 case 5:
1176 modrm_ea += di;
1177 break;
1178 case 6:
1179 if (ctxt->modrm_mod != 0)
1180 modrm_ea += bp;
1181 break;
1182 case 7:
1183 modrm_ea += bx;
1184 break;
1185 }
1186 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1187 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1188 ctxt->modrm_seg = VCPU_SREG_SS;
1189 modrm_ea = (u16)modrm_ea;
1190 } else {
1191 /* 32/64-bit ModR/M decode. */
1192 if ((ctxt->modrm_rm & 7) == 4) {
1193 sib = insn_fetch(u8, ctxt);
1194 index_reg |= (sib >> 3) & 7;
1195 base_reg |= sib & 7;
1196 scale = sib >> 6;
1197
1198 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1199 modrm_ea += insn_fetch(s32, ctxt);
1200 else {
1201 modrm_ea += reg_read(ctxt, base_reg);
1202 adjust_modrm_seg(ctxt, base_reg);
1203 }
1204 if (index_reg != 4)
1205 modrm_ea += reg_read(ctxt, index_reg) << scale;
1206 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1207 if (ctxt->mode == X86EMUL_MODE_PROT64)
1208 ctxt->rip_relative = 1;
1209 } else {
1210 base_reg = ctxt->modrm_rm;
1211 modrm_ea += reg_read(ctxt, base_reg);
1212 adjust_modrm_seg(ctxt, base_reg);
1213 }
1214 switch (ctxt->modrm_mod) {
1215 case 0:
1216 if (ctxt->modrm_rm == 5)
1217 modrm_ea += insn_fetch(s32, ctxt);
1218 break;
1219 case 1:
1220 modrm_ea += insn_fetch(s8, ctxt);
1221 break;
1222 case 2:
1223 modrm_ea += insn_fetch(s32, ctxt);
1224 break;
1225 }
1226 }
1227 op->addr.mem.ea = modrm_ea;
1228 done:
1229 return rc;
1230 }
1231
1232 static int decode_abs(struct x86_emulate_ctxt *ctxt,
1233 struct operand *op)
1234 {
1235 int rc = X86EMUL_CONTINUE;
1236
1237 op->type = OP_MEM;
1238 switch (ctxt->ad_bytes) {
1239 case 2:
1240 op->addr.mem.ea = insn_fetch(u16, ctxt);
1241 break;
1242 case 4:
1243 op->addr.mem.ea = insn_fetch(u32, ctxt);
1244 break;
1245 case 8:
1246 op->addr.mem.ea = insn_fetch(u64, ctxt);
1247 break;
1248 }
1249 done:
1250 return rc;
1251 }
1252
1253 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1254 {
1255 long sv = 0, mask;
1256
1257 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1258 mask = ~(ctxt->dst.bytes * 8 - 1);
1259
1260 if (ctxt->src.bytes == 2)
1261 sv = (s16)ctxt->src.val & (s16)mask;
1262 else if (ctxt->src.bytes == 4)
1263 sv = (s32)ctxt->src.val & (s32)mask;
1264
1265 ctxt->dst.addr.mem.ea += (sv >> 3);
1266 }
1267
1268 /* only subword offset */
1269 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1270 }
1271
1272 static int read_emulated(struct x86_emulate_ctxt *ctxt,
1273 unsigned long addr, void *dest, unsigned size)
1274 {
1275 int rc;
1276 struct read_cache *mc = &ctxt->mem_read;
1277
1278 if (mc->pos < mc->end)
1279 goto read_cached;
1280
1281 WARN_ON((mc->end + size) >= sizeof(mc->data));
1282
1283 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1284 &ctxt->exception);
1285 if (rc != X86EMUL_CONTINUE)
1286 return rc;
1287
1288 mc->end += size;
1289
1290 read_cached:
1291 memcpy(dest, mc->data + mc->pos, size);
1292 mc->pos += size;
1293 return X86EMUL_CONTINUE;
1294 }
1295
1296 static int segmented_read(struct x86_emulate_ctxt *ctxt,
1297 struct segmented_address addr,
1298 void *data,
1299 unsigned size)
1300 {
1301 int rc;
1302 ulong linear;
1303
1304 rc = linearize(ctxt, addr, size, false, &linear);
1305 if (rc != X86EMUL_CONTINUE)
1306 return rc;
1307 return read_emulated(ctxt, linear, data, size);
1308 }
1309
1310 static int segmented_write(struct x86_emulate_ctxt *ctxt,
1311 struct segmented_address addr,
1312 const void *data,
1313 unsigned size)
1314 {
1315 int rc;
1316 ulong linear;
1317
1318 rc = linearize(ctxt, addr, size, true, &linear);
1319 if (rc != X86EMUL_CONTINUE)
1320 return rc;
1321 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1322 &ctxt->exception);
1323 }
1324
1325 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1326 struct segmented_address addr,
1327 const void *orig_data, const void *data,
1328 unsigned size)
1329 {
1330 int rc;
1331 ulong linear;
1332
1333 rc = linearize(ctxt, addr, size, true, &linear);
1334 if (rc != X86EMUL_CONTINUE)
1335 return rc;
1336 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1337 size, &ctxt->exception);
1338 }
1339
1340 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1341 unsigned int size, unsigned short port,
1342 void *dest)
1343 {
1344 struct read_cache *rc = &ctxt->io_read;
1345
1346 if (rc->pos == rc->end) { /* refill pio read ahead */
1347 unsigned int in_page, n;
1348 unsigned int count = ctxt->rep_prefix ?
1349 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
1350 in_page = (ctxt->eflags & EFLG_DF) ?
1351 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1352 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
1353 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1354 count);
1355 if (n == 0)
1356 n = 1;
1357 rc->pos = rc->end = 0;
1358 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1359 return 0;
1360 rc->end = n * size;
1361 }
1362
1363 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1364 ctxt->dst.data = rc->data + rc->pos;
1365 ctxt->dst.type = OP_MEM_STR;
1366 ctxt->dst.count = (rc->end - rc->pos) / size;
1367 rc->pos = rc->end;
1368 } else {
1369 memcpy(dest, rc->data + rc->pos, size);
1370 rc->pos += size;
1371 }
1372 return 1;
1373 }
1374
1375 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1376 u16 index, struct desc_struct *desc)
1377 {
1378 struct desc_ptr dt;
1379 ulong addr;
1380
1381 ctxt->ops->get_idt(ctxt, &dt);
1382
1383 if (dt.size < index * 8 + 7)
1384 return emulate_gp(ctxt, index << 3 | 0x2);
1385
1386 addr = dt.address + index * 8;
1387 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1388 &ctxt->exception);
1389 }
1390
1391 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1392 u16 selector, struct desc_ptr *dt)
1393 {
1394 const struct x86_emulate_ops *ops = ctxt->ops;
1395
1396 if (selector & 1 << 2) {
1397 struct desc_struct desc;
1398 u16 sel;
1399
1400 memset (dt, 0, sizeof *dt);
1401 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
1402 return;
1403
1404 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1405 dt->address = get_desc_base(&desc);
1406 } else
1407 ops->get_gdt(ctxt, dt);
1408 }
1409
1410 /* allowed just for 8 bytes segments */
1411 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1412 u16 selector, struct desc_struct *desc,
1413 ulong *desc_addr_p)
1414 {
1415 struct desc_ptr dt;
1416 u16 index = selector >> 3;
1417 ulong addr;
1418
1419 get_descriptor_table_ptr(ctxt, selector, &dt);
1420
1421 if (dt.size < index * 8 + 7)
1422 return emulate_gp(ctxt, selector & 0xfffc);
1423
1424 *desc_addr_p = addr = dt.address + index * 8;
1425 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1426 &ctxt->exception);
1427 }
1428
1429 /* allowed just for 8 bytes segments */
1430 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1431 u16 selector, struct desc_struct *desc)
1432 {
1433 struct desc_ptr dt;
1434 u16 index = selector >> 3;
1435 ulong addr;
1436
1437 get_descriptor_table_ptr(ctxt, selector, &dt);
1438
1439 if (dt.size < index * 8 + 7)
1440 return emulate_gp(ctxt, selector & 0xfffc);
1441
1442 addr = dt.address + index * 8;
1443 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1444 &ctxt->exception);
1445 }
1446
1447 /* Does not support long mode */
1448 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1449 u16 selector, int seg,
1450 struct desc_struct *desc)
1451 {
1452 struct desc_struct seg_desc, old_desc;
1453 u8 dpl, rpl, cpl;
1454 unsigned err_vec = GP_VECTOR;
1455 u32 err_code = 0;
1456 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1457 ulong desc_addr;
1458 int ret;
1459 u16 dummy;
1460
1461 memset(&seg_desc, 0, sizeof seg_desc);
1462
1463 if (ctxt->mode == X86EMUL_MODE_REAL) {
1464 /* set real mode segment descriptor (keep limit etc. for
1465 * unreal mode) */
1466 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
1467 set_desc_base(&seg_desc, selector << 4);
1468 goto load;
1469 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1470 /* VM86 needs a clean new segment descriptor */
1471 set_desc_base(&seg_desc, selector << 4);
1472 set_desc_limit(&seg_desc, 0xffff);
1473 seg_desc.type = 3;
1474 seg_desc.p = 1;
1475 seg_desc.s = 1;
1476 seg_desc.dpl = 3;
1477 goto load;
1478 }
1479
1480 rpl = selector & 3;
1481 cpl = ctxt->ops->cpl(ctxt);
1482
1483 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1484 if ((seg == VCPU_SREG_CS
1485 || (seg == VCPU_SREG_SS
1486 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1487 || seg == VCPU_SREG_TR)
1488 && null_selector)
1489 goto exception;
1490
1491 /* TR should be in GDT only */
1492 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1493 goto exception;
1494
1495 if (null_selector) /* for NULL selector skip all following checks */
1496 goto load;
1497
1498 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
1499 if (ret != X86EMUL_CONTINUE)
1500 return ret;
1501
1502 err_code = selector & 0xfffc;
1503 err_vec = GP_VECTOR;
1504
1505 /* can't load system descriptor into segment selector */
1506 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1507 goto exception;
1508
1509 if (!seg_desc.p) {
1510 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1511 goto exception;
1512 }
1513
1514 dpl = seg_desc.dpl;
1515
1516 switch (seg) {
1517 case VCPU_SREG_SS:
1518 /*
1519 * segment is not a writable data segment or segment
1520 * selector's RPL != CPL or segment selector's RPL != CPL
1521 */
1522 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1523 goto exception;
1524 break;
1525 case VCPU_SREG_CS:
1526 if (!(seg_desc.type & 8))
1527 goto exception;
1528
1529 if (seg_desc.type & 4) {
1530 /* conforming */
1531 if (dpl > cpl)
1532 goto exception;
1533 } else {
1534 /* nonconforming */
1535 if (rpl > cpl || dpl != cpl)
1536 goto exception;
1537 }
1538 /* in long-mode d/b must be clear if l is set */
1539 if (seg_desc.d && seg_desc.l) {
1540 u64 efer = 0;
1541
1542 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1543 if (efer & EFER_LMA)
1544 goto exception;
1545 }
1546
1547 /* CS(RPL) <- CPL */
1548 selector = (selector & 0xfffc) | cpl;
1549 break;
1550 case VCPU_SREG_TR:
1551 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1552 goto exception;
1553 old_desc = seg_desc;
1554 seg_desc.type |= 2; /* busy */
1555 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1556 sizeof(seg_desc), &ctxt->exception);
1557 if (ret != X86EMUL_CONTINUE)
1558 return ret;
1559 break;
1560 case VCPU_SREG_LDTR:
1561 if (seg_desc.s || seg_desc.type != 2)
1562 goto exception;
1563 break;
1564 default: /* DS, ES, FS, or GS */
1565 /*
1566 * segment is not a data or readable code segment or
1567 * ((segment is a data or nonconforming code segment)
1568 * and (both RPL and CPL > DPL))
1569 */
1570 if ((seg_desc.type & 0xa) == 0x8 ||
1571 (((seg_desc.type & 0xc) != 0xc) &&
1572 (rpl > dpl && cpl > dpl)))
1573 goto exception;
1574 break;
1575 }
1576
1577 if (seg_desc.s) {
1578 /* mark segment as accessed */
1579 seg_desc.type |= 1;
1580 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
1581 if (ret != X86EMUL_CONTINUE)
1582 return ret;
1583 }
1584 load:
1585 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
1586 if (desc)
1587 *desc = seg_desc;
1588 return X86EMUL_CONTINUE;
1589 exception:
1590 emulate_exception(ctxt, err_vec, err_code, true);
1591 return X86EMUL_PROPAGATE_FAULT;
1592 }
1593
1594 static void write_register_operand(struct operand *op)
1595 {
1596 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1597 switch (op->bytes) {
1598 case 1:
1599 *(u8 *)op->addr.reg = (u8)op->val;
1600 break;
1601 case 2:
1602 *(u16 *)op->addr.reg = (u16)op->val;
1603 break;
1604 case 4:
1605 *op->addr.reg = (u32)op->val;
1606 break; /* 64b: zero-extend */
1607 case 8:
1608 *op->addr.reg = op->val;
1609 break;
1610 }
1611 }
1612
1613 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
1614 {
1615 int rc;
1616
1617 switch (op->type) {
1618 case OP_REG:
1619 write_register_operand(op);
1620 break;
1621 case OP_MEM:
1622 if (ctxt->lock_prefix)
1623 rc = segmented_cmpxchg(ctxt,
1624 op->addr.mem,
1625 &op->orig_val,
1626 &op->val,
1627 op->bytes);
1628 else
1629 rc = segmented_write(ctxt,
1630 op->addr.mem,
1631 &op->val,
1632 op->bytes);
1633 if (rc != X86EMUL_CONTINUE)
1634 return rc;
1635 break;
1636 case OP_MEM_STR:
1637 rc = segmented_write(ctxt,
1638 op->addr.mem,
1639 op->data,
1640 op->bytes * op->count);
1641 if (rc != X86EMUL_CONTINUE)
1642 return rc;
1643 break;
1644 case OP_XMM:
1645 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1646 break;
1647 case OP_MM:
1648 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
1649 break;
1650 case OP_NONE:
1651 /* no writeback */
1652 break;
1653 default:
1654 break;
1655 }
1656 return X86EMUL_CONTINUE;
1657 }
1658
1659 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
1660 {
1661 struct segmented_address addr;
1662
1663 rsp_increment(ctxt, -bytes);
1664 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1665 addr.seg = VCPU_SREG_SS;
1666
1667 return segmented_write(ctxt, addr, data, bytes);
1668 }
1669
1670 static int em_push(struct x86_emulate_ctxt *ctxt)
1671 {
1672 /* Disable writeback. */
1673 ctxt->dst.type = OP_NONE;
1674 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
1675 }
1676
1677 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1678 void *dest, int len)
1679 {
1680 int rc;
1681 struct segmented_address addr;
1682
1683 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1684 addr.seg = VCPU_SREG_SS;
1685 rc = segmented_read(ctxt, addr, dest, len);
1686 if (rc != X86EMUL_CONTINUE)
1687 return rc;
1688
1689 rsp_increment(ctxt, len);
1690 return rc;
1691 }
1692
1693 static int em_pop(struct x86_emulate_ctxt *ctxt)
1694 {
1695 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1696 }
1697
1698 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1699 void *dest, int len)
1700 {
1701 int rc;
1702 unsigned long val, change_mask;
1703 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1704 int cpl = ctxt->ops->cpl(ctxt);
1705
1706 rc = emulate_pop(ctxt, &val, len);
1707 if (rc != X86EMUL_CONTINUE)
1708 return rc;
1709
1710 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1711 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1712
1713 switch(ctxt->mode) {
1714 case X86EMUL_MODE_PROT64:
1715 case X86EMUL_MODE_PROT32:
1716 case X86EMUL_MODE_PROT16:
1717 if (cpl == 0)
1718 change_mask |= EFLG_IOPL;
1719 if (cpl <= iopl)
1720 change_mask |= EFLG_IF;
1721 break;
1722 case X86EMUL_MODE_VM86:
1723 if (iopl < 3)
1724 return emulate_gp(ctxt, 0);
1725 change_mask |= EFLG_IF;
1726 break;
1727 default: /* real mode */
1728 change_mask |= (EFLG_IOPL | EFLG_IF);
1729 break;
1730 }
1731
1732 *(unsigned long *)dest =
1733 (ctxt->eflags & ~change_mask) | (val & change_mask);
1734
1735 return rc;
1736 }
1737
1738 static int em_popf(struct x86_emulate_ctxt *ctxt)
1739 {
1740 ctxt->dst.type = OP_REG;
1741 ctxt->dst.addr.reg = &ctxt->eflags;
1742 ctxt->dst.bytes = ctxt->op_bytes;
1743 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1744 }
1745
1746 static int em_enter(struct x86_emulate_ctxt *ctxt)
1747 {
1748 int rc;
1749 unsigned frame_size = ctxt->src.val;
1750 unsigned nesting_level = ctxt->src2.val & 31;
1751 ulong rbp;
1752
1753 if (nesting_level)
1754 return X86EMUL_UNHANDLEABLE;
1755
1756 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1757 rc = push(ctxt, &rbp, stack_size(ctxt));
1758 if (rc != X86EMUL_CONTINUE)
1759 return rc;
1760 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
1761 stack_mask(ctxt));
1762 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1763 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
1764 stack_mask(ctxt));
1765 return X86EMUL_CONTINUE;
1766 }
1767
1768 static int em_leave(struct x86_emulate_ctxt *ctxt)
1769 {
1770 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
1771 stack_mask(ctxt));
1772 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
1773 }
1774
1775 static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1776 {
1777 int seg = ctxt->src2.val;
1778
1779 ctxt->src.val = get_segment_selector(ctxt, seg);
1780
1781 return em_push(ctxt);
1782 }
1783
1784 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1785 {
1786 int seg = ctxt->src2.val;
1787 unsigned long selector;
1788 int rc;
1789
1790 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
1791 if (rc != X86EMUL_CONTINUE)
1792 return rc;
1793
1794 rc = load_segment_descriptor(ctxt, (u16)selector, seg, NULL);
1795 return rc;
1796 }
1797
1798 static int em_pusha(struct x86_emulate_ctxt *ctxt)
1799 {
1800 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
1801 int rc = X86EMUL_CONTINUE;
1802 int reg = VCPU_REGS_RAX;
1803
1804 while (reg <= VCPU_REGS_RDI) {
1805 (reg == VCPU_REGS_RSP) ?
1806 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
1807
1808 rc = em_push(ctxt);
1809 if (rc != X86EMUL_CONTINUE)
1810 return rc;
1811
1812 ++reg;
1813 }
1814
1815 return rc;
1816 }
1817
1818 static int em_pushf(struct x86_emulate_ctxt *ctxt)
1819 {
1820 ctxt->src.val = (unsigned long)ctxt->eflags;
1821 return em_push(ctxt);
1822 }
1823
1824 static int em_popa(struct x86_emulate_ctxt *ctxt)
1825 {
1826 int rc = X86EMUL_CONTINUE;
1827 int reg = VCPU_REGS_RDI;
1828
1829 while (reg >= VCPU_REGS_RAX) {
1830 if (reg == VCPU_REGS_RSP) {
1831 rsp_increment(ctxt, ctxt->op_bytes);
1832 --reg;
1833 }
1834
1835 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
1836 if (rc != X86EMUL_CONTINUE)
1837 break;
1838 --reg;
1839 }
1840 return rc;
1841 }
1842
1843 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1844 {
1845 const struct x86_emulate_ops *ops = ctxt->ops;
1846 int rc;
1847 struct desc_ptr dt;
1848 gva_t cs_addr;
1849 gva_t eip_addr;
1850 u16 cs, eip;
1851
1852 /* TODO: Add limit checks */
1853 ctxt->src.val = ctxt->eflags;
1854 rc = em_push(ctxt);
1855 if (rc != X86EMUL_CONTINUE)
1856 return rc;
1857
1858 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1859
1860 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
1861 rc = em_push(ctxt);
1862 if (rc != X86EMUL_CONTINUE)
1863 return rc;
1864
1865 ctxt->src.val = ctxt->_eip;
1866 rc = em_push(ctxt);
1867 if (rc != X86EMUL_CONTINUE)
1868 return rc;
1869
1870 ops->get_idt(ctxt, &dt);
1871
1872 eip_addr = dt.address + (irq << 2);
1873 cs_addr = dt.address + (irq << 2) + 2;
1874
1875 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1876 if (rc != X86EMUL_CONTINUE)
1877 return rc;
1878
1879 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1880 if (rc != X86EMUL_CONTINUE)
1881 return rc;
1882
1883 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS, NULL);
1884 if (rc != X86EMUL_CONTINUE)
1885 return rc;
1886
1887 ctxt->_eip = eip;
1888
1889 return rc;
1890 }
1891
1892 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1893 {
1894 int rc;
1895
1896 invalidate_registers(ctxt);
1897 rc = __emulate_int_real(ctxt, irq);
1898 if (rc == X86EMUL_CONTINUE)
1899 writeback_registers(ctxt);
1900 return rc;
1901 }
1902
1903 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
1904 {
1905 switch(ctxt->mode) {
1906 case X86EMUL_MODE_REAL:
1907 return __emulate_int_real(ctxt, irq);
1908 case X86EMUL_MODE_VM86:
1909 case X86EMUL_MODE_PROT16:
1910 case X86EMUL_MODE_PROT32:
1911 case X86EMUL_MODE_PROT64:
1912 default:
1913 /* Protected mode interrupts unimplemented yet */
1914 return X86EMUL_UNHANDLEABLE;
1915 }
1916 }
1917
1918 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
1919 {
1920 int rc = X86EMUL_CONTINUE;
1921 unsigned long temp_eip = 0;
1922 unsigned long temp_eflags = 0;
1923 unsigned long cs = 0;
1924 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1925 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1926 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1927 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1928
1929 /* TODO: Add stack limit check */
1930
1931 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
1932
1933 if (rc != X86EMUL_CONTINUE)
1934 return rc;
1935
1936 if (temp_eip & ~0xffff)
1937 return emulate_gp(ctxt, 0);
1938
1939 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1940
1941 if (rc != X86EMUL_CONTINUE)
1942 return rc;
1943
1944 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
1945
1946 if (rc != X86EMUL_CONTINUE)
1947 return rc;
1948
1949 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, NULL);
1950
1951 if (rc != X86EMUL_CONTINUE)
1952 return rc;
1953
1954 ctxt->_eip = temp_eip;
1955
1956
1957 if (ctxt->op_bytes == 4)
1958 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1959 else if (ctxt->op_bytes == 2) {
1960 ctxt->eflags &= ~0xffff;
1961 ctxt->eflags |= temp_eflags;
1962 }
1963
1964 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1965 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1966
1967 return rc;
1968 }
1969
1970 static int em_iret(struct x86_emulate_ctxt *ctxt)
1971 {
1972 switch(ctxt->mode) {
1973 case X86EMUL_MODE_REAL:
1974 return emulate_iret_real(ctxt);
1975 case X86EMUL_MODE_VM86:
1976 case X86EMUL_MODE_PROT16:
1977 case X86EMUL_MODE_PROT32:
1978 case X86EMUL_MODE_PROT64:
1979 default:
1980 /* iret from protected mode unimplemented yet */
1981 return X86EMUL_UNHANDLEABLE;
1982 }
1983 }
1984
1985 static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1986 {
1987 int rc;
1988 unsigned short sel, old_sel;
1989 struct desc_struct old_desc, new_desc;
1990 const struct x86_emulate_ops *ops = ctxt->ops;
1991
1992 /* Assignment of RIP may only fail in 64-bit mode */
1993 if (ctxt->mode == X86EMUL_MODE_PROT64)
1994 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
1995 VCPU_SREG_CS);
1996
1997 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
1998
1999 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, &new_desc);
2000 if (rc != X86EMUL_CONTINUE)
2001 return rc;
2002
2003 rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
2004 if (rc != X86EMUL_CONTINUE) {
2005 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
2006 /* assigning eip failed; restore the old cs */
2007 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2008 return rc;
2009 }
2010 return rc;
2011 }
2012
2013 static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
2014 {
2015 return assign_eip_near(ctxt, ctxt->src.val);
2016 }
2017
2018 static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2019 {
2020 int rc;
2021 long int old_eip;
2022
2023 old_eip = ctxt->_eip;
2024 rc = assign_eip_near(ctxt, ctxt->src.val);
2025 if (rc != X86EMUL_CONTINUE)
2026 return rc;
2027 ctxt->src.val = old_eip;
2028 rc = em_push(ctxt);
2029 return rc;
2030 }
2031
2032 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
2033 {
2034 u64 old = ctxt->dst.orig_val64;
2035
2036 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2037 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2038 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2039 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
2040 ctxt->eflags &= ~EFLG_ZF;
2041 } else {
2042 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2043 (u32) reg_read(ctxt, VCPU_REGS_RBX);
2044
2045 ctxt->eflags |= EFLG_ZF;
2046 }
2047 return X86EMUL_CONTINUE;
2048 }
2049
2050 static int em_ret(struct x86_emulate_ctxt *ctxt)
2051 {
2052 int rc;
2053 unsigned long eip;
2054
2055 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2056 if (rc != X86EMUL_CONTINUE)
2057 return rc;
2058
2059 return assign_eip_near(ctxt, eip);
2060 }
2061
2062 static int em_ret_far(struct x86_emulate_ctxt *ctxt)
2063 {
2064 int rc;
2065 unsigned long eip, cs;
2066 u16 old_cs;
2067 int cpl = ctxt->ops->cpl(ctxt);
2068 struct desc_struct old_desc, new_desc;
2069 const struct x86_emulate_ops *ops = ctxt->ops;
2070
2071 if (ctxt->mode == X86EMUL_MODE_PROT64)
2072 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2073 VCPU_SREG_CS);
2074
2075 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2076 if (rc != X86EMUL_CONTINUE)
2077 return rc;
2078 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2079 if (rc != X86EMUL_CONTINUE)
2080 return rc;
2081 /* Outer-privilege level return is not implemented */
2082 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2083 return X86EMUL_UNHANDLEABLE;
2084 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, &new_desc);
2085 if (rc != X86EMUL_CONTINUE)
2086 return rc;
2087 rc = assign_eip_far(ctxt, eip, new_desc.l);
2088 if (rc != X86EMUL_CONTINUE) {
2089 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
2090 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2091 }
2092 return rc;
2093 }
2094
2095 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2096 {
2097 int rc;
2098
2099 rc = em_ret_far(ctxt);
2100 if (rc != X86EMUL_CONTINUE)
2101 return rc;
2102 rsp_increment(ctxt, ctxt->src.val);
2103 return X86EMUL_CONTINUE;
2104 }
2105
2106 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2107 {
2108 /* Save real source value, then compare EAX against destination. */
2109 ctxt->src.orig_val = ctxt->src.val;
2110 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
2111 fastop(ctxt, em_cmp);
2112
2113 if (ctxt->eflags & EFLG_ZF) {
2114 /* Success: write back to memory. */
2115 ctxt->dst.val = ctxt->src.orig_val;
2116 } else {
2117 /* Failure: write the value we saw to EAX. */
2118 ctxt->dst.type = OP_REG;
2119 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2120 }
2121 return X86EMUL_CONTINUE;
2122 }
2123
2124 static int em_lseg(struct x86_emulate_ctxt *ctxt)
2125 {
2126 int seg = ctxt->src2.val;
2127 unsigned short sel;
2128 int rc;
2129
2130 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2131
2132 rc = load_segment_descriptor(ctxt, sel, seg, NULL);
2133 if (rc != X86EMUL_CONTINUE)
2134 return rc;
2135
2136 ctxt->dst.val = ctxt->src.val;
2137 return rc;
2138 }
2139
2140 static void
2141 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
2142 struct desc_struct *cs, struct desc_struct *ss)
2143 {
2144 cs->l = 0; /* will be adjusted later */
2145 set_desc_base(cs, 0); /* flat segment */
2146 cs->g = 1; /* 4kb granularity */
2147 set_desc_limit(cs, 0xfffff); /* 4GB limit */
2148 cs->type = 0x0b; /* Read, Execute, Accessed */
2149 cs->s = 1;
2150 cs->dpl = 0; /* will be adjusted later */
2151 cs->p = 1;
2152 cs->d = 1;
2153 cs->avl = 0;
2154
2155 set_desc_base(ss, 0); /* flat segment */
2156 set_desc_limit(ss, 0xfffff); /* 4GB limit */
2157 ss->g = 1; /* 4kb granularity */
2158 ss->s = 1;
2159 ss->type = 0x03; /* Read/Write, Accessed */
2160 ss->d = 1; /* 32bit stack segment */
2161 ss->dpl = 0;
2162 ss->p = 1;
2163 ss->l = 0;
2164 ss->avl = 0;
2165 }
2166
2167 static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2168 {
2169 u32 eax, ebx, ecx, edx;
2170
2171 eax = ecx = 0;
2172 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2173 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
2174 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2175 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2176 }
2177
2178 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2179 {
2180 const struct x86_emulate_ops *ops = ctxt->ops;
2181 u32 eax, ebx, ecx, edx;
2182
2183 /*
2184 * syscall should always be enabled in longmode - so only become
2185 * vendor specific (cpuid) if other modes are active...
2186 */
2187 if (ctxt->mode == X86EMUL_MODE_PROT64)
2188 return true;
2189
2190 eax = 0x00000000;
2191 ecx = 0x00000000;
2192 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2193 /*
2194 * Intel ("GenuineIntel")
2195 * remark: Intel CPUs only support "syscall" in 64bit
2196 * longmode. Also an 64bit guest with a
2197 * 32bit compat-app running will #UD !! While this
2198 * behaviour can be fixed (by emulating) into AMD
2199 * response - CPUs of AMD can't behave like Intel.
2200 */
2201 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2202 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2203 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2204 return false;
2205
2206 /* AMD ("AuthenticAMD") */
2207 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2208 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2209 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2210 return true;
2211
2212 /* AMD ("AMDisbetter!") */
2213 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2214 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2215 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2216 return true;
2217
2218 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2219 return false;
2220 }
2221
2222 static int em_syscall(struct x86_emulate_ctxt *ctxt)
2223 {
2224 const struct x86_emulate_ops *ops = ctxt->ops;
2225 struct desc_struct cs, ss;
2226 u64 msr_data;
2227 u16 cs_sel, ss_sel;
2228 u64 efer = 0;
2229
2230 /* syscall is not available in real mode */
2231 if (ctxt->mode == X86EMUL_MODE_REAL ||
2232 ctxt->mode == X86EMUL_MODE_VM86)
2233 return emulate_ud(ctxt);
2234
2235 if (!(em_syscall_is_enabled(ctxt)))
2236 return emulate_ud(ctxt);
2237
2238 ops->get_msr(ctxt, MSR_EFER, &efer);
2239 setup_syscalls_segments(ctxt, &cs, &ss);
2240
2241 if (!(efer & EFER_SCE))
2242 return emulate_ud(ctxt);
2243
2244 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2245 msr_data >>= 32;
2246 cs_sel = (u16)(msr_data & 0xfffc);
2247 ss_sel = (u16)(msr_data + 8);
2248
2249 if (efer & EFER_LMA) {
2250 cs.d = 0;
2251 cs.l = 1;
2252 }
2253 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2254 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2255
2256 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
2257 if (efer & EFER_LMA) {
2258 #ifdef CONFIG_X86_64
2259 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
2260
2261 ops->get_msr(ctxt,
2262 ctxt->mode == X86EMUL_MODE_PROT64 ?
2263 MSR_LSTAR : MSR_CSTAR, &msr_data);
2264 ctxt->_eip = msr_data;
2265
2266 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2267 ctxt->eflags &= ~(msr_data | EFLG_RF);
2268 #endif
2269 } else {
2270 /* legacy mode */
2271 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2272 ctxt->_eip = (u32)msr_data;
2273
2274 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2275 }
2276
2277 return X86EMUL_CONTINUE;
2278 }
2279
2280 static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2281 {
2282 const struct x86_emulate_ops *ops = ctxt->ops;
2283 struct desc_struct cs, ss;
2284 u64 msr_data;
2285 u16 cs_sel, ss_sel;
2286 u64 efer = 0;
2287
2288 ops->get_msr(ctxt, MSR_EFER, &efer);
2289 /* inject #GP if in real mode */
2290 if (ctxt->mode == X86EMUL_MODE_REAL)
2291 return emulate_gp(ctxt, 0);
2292
2293 /*
2294 * Not recognized on AMD in compat mode (but is recognized in legacy
2295 * mode).
2296 */
2297 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
2298 && !vendor_intel(ctxt))
2299 return emulate_ud(ctxt);
2300
2301 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2302 * Therefore, we inject an #UD.
2303 */
2304 if (ctxt->mode == X86EMUL_MODE_PROT64)
2305 return emulate_ud(ctxt);
2306
2307 setup_syscalls_segments(ctxt, &cs, &ss);
2308
2309 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2310 if ((msr_data & 0xfffc) == 0x0)
2311 return emulate_gp(ctxt, 0);
2312
2313 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2314 cs_sel = (u16)msr_data & ~SELECTOR_RPL_MASK;
2315 ss_sel = cs_sel + 8;
2316 if (efer & EFER_LMA) {
2317 cs.d = 0;
2318 cs.l = 1;
2319 }
2320
2321 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2322 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2323
2324 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2325 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
2326
2327 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2328 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2329 (u32)msr_data;
2330
2331 return X86EMUL_CONTINUE;
2332 }
2333
2334 static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2335 {
2336 const struct x86_emulate_ops *ops = ctxt->ops;
2337 struct desc_struct cs, ss;
2338 u64 msr_data, rcx, rdx;
2339 int usermode;
2340 u16 cs_sel = 0, ss_sel = 0;
2341
2342 /* inject #GP if in real mode or Virtual 8086 mode */
2343 if (ctxt->mode == X86EMUL_MODE_REAL ||
2344 ctxt->mode == X86EMUL_MODE_VM86)
2345 return emulate_gp(ctxt, 0);
2346
2347 setup_syscalls_segments(ctxt, &cs, &ss);
2348
2349 if ((ctxt->rex_prefix & 0x8) != 0x0)
2350 usermode = X86EMUL_MODE_PROT64;
2351 else
2352 usermode = X86EMUL_MODE_PROT32;
2353
2354 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2355 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2356
2357 cs.dpl = 3;
2358 ss.dpl = 3;
2359 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2360 switch (usermode) {
2361 case X86EMUL_MODE_PROT32:
2362 cs_sel = (u16)(msr_data + 16);
2363 if ((msr_data & 0xfffc) == 0x0)
2364 return emulate_gp(ctxt, 0);
2365 ss_sel = (u16)(msr_data + 24);
2366 rcx = (u32)rcx;
2367 rdx = (u32)rdx;
2368 break;
2369 case X86EMUL_MODE_PROT64:
2370 cs_sel = (u16)(msr_data + 32);
2371 if (msr_data == 0x0)
2372 return emulate_gp(ctxt, 0);
2373 ss_sel = cs_sel + 8;
2374 cs.d = 0;
2375 cs.l = 1;
2376 if (is_noncanonical_address(rcx) ||
2377 is_noncanonical_address(rdx))
2378 return emulate_gp(ctxt, 0);
2379 break;
2380 }
2381 cs_sel |= SELECTOR_RPL_MASK;
2382 ss_sel |= SELECTOR_RPL_MASK;
2383
2384 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2385 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2386
2387 ctxt->_eip = rdx;
2388 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
2389
2390 return X86EMUL_CONTINUE;
2391 }
2392
2393 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2394 {
2395 int iopl;
2396 if (ctxt->mode == X86EMUL_MODE_REAL)
2397 return false;
2398 if (ctxt->mode == X86EMUL_MODE_VM86)
2399 return true;
2400 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2401 return ctxt->ops->cpl(ctxt) > iopl;
2402 }
2403
2404 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2405 u16 port, u16 len)
2406 {
2407 const struct x86_emulate_ops *ops = ctxt->ops;
2408 struct desc_struct tr_seg;
2409 u32 base3;
2410 int r;
2411 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2412 unsigned mask = (1 << len) - 1;
2413 unsigned long base;
2414
2415 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2416 if (!tr_seg.p)
2417 return false;
2418 if (desc_limit_scaled(&tr_seg) < 103)
2419 return false;
2420 base = get_desc_base(&tr_seg);
2421 #ifdef CONFIG_X86_64
2422 base |= ((u64)base3) << 32;
2423 #endif
2424 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2425 if (r != X86EMUL_CONTINUE)
2426 return false;
2427 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2428 return false;
2429 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2430 if (r != X86EMUL_CONTINUE)
2431 return false;
2432 if ((perm >> bit_idx) & mask)
2433 return false;
2434 return true;
2435 }
2436
2437 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2438 u16 port, u16 len)
2439 {
2440 if (ctxt->perm_ok)
2441 return true;
2442
2443 if (emulator_bad_iopl(ctxt))
2444 if (!emulator_io_port_access_allowed(ctxt, port, len))
2445 return false;
2446
2447 ctxt->perm_ok = true;
2448
2449 return true;
2450 }
2451
2452 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2453 struct tss_segment_16 *tss)
2454 {
2455 tss->ip = ctxt->_eip;
2456 tss->flag = ctxt->eflags;
2457 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2458 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2459 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2460 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2461 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2462 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2463 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2464 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
2465
2466 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2467 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2468 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2469 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2470 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2471 }
2472
2473 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2474 struct tss_segment_16 *tss)
2475 {
2476 int ret;
2477
2478 ctxt->_eip = tss->ip;
2479 ctxt->eflags = tss->flag | 2;
2480 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2481 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2482 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2483 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2484 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2485 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2486 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2487 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
2488
2489 /*
2490 * SDM says that segment selectors are loaded before segment
2491 * descriptors
2492 */
2493 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2494 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2495 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2496 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2497 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2498
2499 /*
2500 * Now load segment descriptors. If fault happens at this stage
2501 * it is handled in a context of new task
2502 */
2503 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, NULL);
2504 if (ret != X86EMUL_CONTINUE)
2505 return ret;
2506 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, NULL);
2507 if (ret != X86EMUL_CONTINUE)
2508 return ret;
2509 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, NULL);
2510 if (ret != X86EMUL_CONTINUE)
2511 return ret;
2512 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, NULL);
2513 if (ret != X86EMUL_CONTINUE)
2514 return ret;
2515 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, NULL);
2516 if (ret != X86EMUL_CONTINUE)
2517 return ret;
2518
2519 return X86EMUL_CONTINUE;
2520 }
2521
2522 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2523 u16 tss_selector, u16 old_tss_sel,
2524 ulong old_tss_base, struct desc_struct *new_desc)
2525 {
2526 const struct x86_emulate_ops *ops = ctxt->ops;
2527 struct tss_segment_16 tss_seg;
2528 int ret;
2529 u32 new_tss_base = get_desc_base(new_desc);
2530
2531 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2532 &ctxt->exception);
2533 if (ret != X86EMUL_CONTINUE)
2534 /* FIXME: need to provide precise fault address */
2535 return ret;
2536
2537 save_state_to_tss16(ctxt, &tss_seg);
2538
2539 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2540 &ctxt->exception);
2541 if (ret != X86EMUL_CONTINUE)
2542 /* FIXME: need to provide precise fault address */
2543 return ret;
2544
2545 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2546 &ctxt->exception);
2547 if (ret != X86EMUL_CONTINUE)
2548 /* FIXME: need to provide precise fault address */
2549 return ret;
2550
2551 if (old_tss_sel != 0xffff) {
2552 tss_seg.prev_task_link = old_tss_sel;
2553
2554 ret = ops->write_std(ctxt, new_tss_base,
2555 &tss_seg.prev_task_link,
2556 sizeof tss_seg.prev_task_link,
2557 &ctxt->exception);
2558 if (ret != X86EMUL_CONTINUE)
2559 /* FIXME: need to provide precise fault address */
2560 return ret;
2561 }
2562
2563 return load_state_from_tss16(ctxt, &tss_seg);
2564 }
2565
2566 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2567 struct tss_segment_32 *tss)
2568 {
2569 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
2570 tss->eip = ctxt->_eip;
2571 tss->eflags = ctxt->eflags;
2572 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2573 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2574 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2575 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2576 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2577 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2578 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2579 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
2580
2581 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2582 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2583 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2584 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2585 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2586 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2587 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2588 }
2589
2590 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2591 struct tss_segment_32 *tss)
2592 {
2593 int ret;
2594
2595 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
2596 return emulate_gp(ctxt, 0);
2597 ctxt->_eip = tss->eip;
2598 ctxt->eflags = tss->eflags | 2;
2599
2600 /* General purpose registers */
2601 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2602 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2603 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2604 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2605 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2606 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2607 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2608 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
2609
2610 /*
2611 * SDM says that segment selectors are loaded before segment
2612 * descriptors
2613 */
2614 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2615 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2616 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2617 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2618 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2619 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2620 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2621
2622 /*
2623 * If we're switching between Protected Mode and VM86, we need to make
2624 * sure to update the mode before loading the segment descriptors so
2625 * that the selectors are interpreted correctly.
2626 *
2627 * Need to get rflags to the vcpu struct immediately because it
2628 * influences the CPL which is checked at least when loading the segment
2629 * descriptors and when pushing an error code to the new kernel stack.
2630 *
2631 * TODO Introduce a separate ctxt->ops->set_cpl callback
2632 */
2633 if (ctxt->eflags & X86_EFLAGS_VM)
2634 ctxt->mode = X86EMUL_MODE_VM86;
2635 else
2636 ctxt->mode = X86EMUL_MODE_PROT32;
2637
2638 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2639
2640 /*
2641 * Now load segment descriptors. If fault happenes at this stage
2642 * it is handled in a context of new task
2643 */
2644 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
2645 NULL);
2646 if (ret != X86EMUL_CONTINUE)
2647 return ret;
2648 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, NULL);
2649 if (ret != X86EMUL_CONTINUE)
2650 return ret;
2651 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, NULL);
2652 if (ret != X86EMUL_CONTINUE)
2653 return ret;
2654 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, NULL);
2655 if (ret != X86EMUL_CONTINUE)
2656 return ret;
2657 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, NULL);
2658 if (ret != X86EMUL_CONTINUE)
2659 return ret;
2660 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, NULL);
2661 if (ret != X86EMUL_CONTINUE)
2662 return ret;
2663 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, NULL);
2664 if (ret != X86EMUL_CONTINUE)
2665 return ret;
2666
2667 return X86EMUL_CONTINUE;
2668 }
2669
2670 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2671 u16 tss_selector, u16 old_tss_sel,
2672 ulong old_tss_base, struct desc_struct *new_desc)
2673 {
2674 const struct x86_emulate_ops *ops = ctxt->ops;
2675 struct tss_segment_32 tss_seg;
2676 int ret;
2677 u32 new_tss_base = get_desc_base(new_desc);
2678
2679 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2680 &ctxt->exception);
2681 if (ret != X86EMUL_CONTINUE)
2682 /* FIXME: need to provide precise fault address */
2683 return ret;
2684
2685 save_state_to_tss32(ctxt, &tss_seg);
2686
2687 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2688 &ctxt->exception);
2689 if (ret != X86EMUL_CONTINUE)
2690 /* FIXME: need to provide precise fault address */
2691 return ret;
2692
2693 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2694 &ctxt->exception);
2695 if (ret != X86EMUL_CONTINUE)
2696 /* FIXME: need to provide precise fault address */
2697 return ret;
2698
2699 if (old_tss_sel != 0xffff) {
2700 tss_seg.prev_task_link = old_tss_sel;
2701
2702 ret = ops->write_std(ctxt, new_tss_base,
2703 &tss_seg.prev_task_link,
2704 sizeof tss_seg.prev_task_link,
2705 &ctxt->exception);
2706 if (ret != X86EMUL_CONTINUE)
2707 /* FIXME: need to provide precise fault address */
2708 return ret;
2709 }
2710
2711 return load_state_from_tss32(ctxt, &tss_seg);
2712 }
2713
2714 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2715 u16 tss_selector, int idt_index, int reason,
2716 bool has_error_code, u32 error_code)
2717 {
2718 const struct x86_emulate_ops *ops = ctxt->ops;
2719 struct desc_struct curr_tss_desc, next_tss_desc;
2720 int ret;
2721 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
2722 ulong old_tss_base =
2723 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2724 u32 desc_limit;
2725 ulong desc_addr;
2726
2727 /* FIXME: old_tss_base == ~0 ? */
2728
2729 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
2730 if (ret != X86EMUL_CONTINUE)
2731 return ret;
2732 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
2733 if (ret != X86EMUL_CONTINUE)
2734 return ret;
2735
2736 /* FIXME: check that next_tss_desc is tss */
2737
2738 /*
2739 * Check privileges. The three cases are task switch caused by...
2740 *
2741 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2742 * 2. Exception/IRQ/iret: No check is performed
2743 * 3. jmp/call to TSS: Check against DPL of the TSS
2744 */
2745 if (reason == TASK_SWITCH_GATE) {
2746 if (idt_index != -1) {
2747 /* Software interrupts */
2748 struct desc_struct task_gate_desc;
2749 int dpl;
2750
2751 ret = read_interrupt_descriptor(ctxt, idt_index,
2752 &task_gate_desc);
2753 if (ret != X86EMUL_CONTINUE)
2754 return ret;
2755
2756 dpl = task_gate_desc.dpl;
2757 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2758 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2759 }
2760 } else if (reason != TASK_SWITCH_IRET) {
2761 int dpl = next_tss_desc.dpl;
2762 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2763 return emulate_gp(ctxt, tss_selector);
2764 }
2765
2766
2767 desc_limit = desc_limit_scaled(&next_tss_desc);
2768 if (!next_tss_desc.p ||
2769 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2770 desc_limit < 0x2b)) {
2771 emulate_ts(ctxt, tss_selector & 0xfffc);
2772 return X86EMUL_PROPAGATE_FAULT;
2773 }
2774
2775 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2776 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2777 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2778 }
2779
2780 if (reason == TASK_SWITCH_IRET)
2781 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2782
2783 /* set back link to prev task only if NT bit is set in eflags
2784 note that old_tss_sel is not used after this point */
2785 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2786 old_tss_sel = 0xffff;
2787
2788 if (next_tss_desc.type & 8)
2789 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
2790 old_tss_base, &next_tss_desc);
2791 else
2792 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
2793 old_tss_base, &next_tss_desc);
2794 if (ret != X86EMUL_CONTINUE)
2795 return ret;
2796
2797 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2798 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2799
2800 if (reason != TASK_SWITCH_IRET) {
2801 next_tss_desc.type |= (1 << 1); /* set busy flag */
2802 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2803 }
2804
2805 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
2806 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
2807
2808 if (has_error_code) {
2809 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2810 ctxt->lock_prefix = 0;
2811 ctxt->src.val = (unsigned long) error_code;
2812 ret = em_push(ctxt);
2813 }
2814
2815 return ret;
2816 }
2817
2818 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2819 u16 tss_selector, int idt_index, int reason,
2820 bool has_error_code, u32 error_code)
2821 {
2822 int rc;
2823
2824 invalidate_registers(ctxt);
2825 ctxt->_eip = ctxt->eip;
2826 ctxt->dst.type = OP_NONE;
2827
2828 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
2829 has_error_code, error_code);
2830
2831 if (rc == X86EMUL_CONTINUE) {
2832 ctxt->eip = ctxt->_eip;
2833 writeback_registers(ctxt);
2834 }
2835
2836 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2837 }
2838
2839 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2840 struct operand *op)
2841 {
2842 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
2843
2844 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2845 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
2846 }
2847
2848 static int em_das(struct x86_emulate_ctxt *ctxt)
2849 {
2850 u8 al, old_al;
2851 bool af, cf, old_cf;
2852
2853 cf = ctxt->eflags & X86_EFLAGS_CF;
2854 al = ctxt->dst.val;
2855
2856 old_al = al;
2857 old_cf = cf;
2858 cf = false;
2859 af = ctxt->eflags & X86_EFLAGS_AF;
2860 if ((al & 0x0f) > 9 || af) {
2861 al -= 6;
2862 cf = old_cf | (al >= 250);
2863 af = true;
2864 } else {
2865 af = false;
2866 }
2867 if (old_al > 0x99 || old_cf) {
2868 al -= 0x60;
2869 cf = true;
2870 }
2871
2872 ctxt->dst.val = al;
2873 /* Set PF, ZF, SF */
2874 ctxt->src.type = OP_IMM;
2875 ctxt->src.val = 0;
2876 ctxt->src.bytes = 1;
2877 fastop(ctxt, em_or);
2878 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2879 if (cf)
2880 ctxt->eflags |= X86_EFLAGS_CF;
2881 if (af)
2882 ctxt->eflags |= X86_EFLAGS_AF;
2883 return X86EMUL_CONTINUE;
2884 }
2885
2886 static int em_aam(struct x86_emulate_ctxt *ctxt)
2887 {
2888 u8 al, ah;
2889
2890 if (ctxt->src.val == 0)
2891 return emulate_de(ctxt);
2892
2893 al = ctxt->dst.val & 0xff;
2894 ah = al / ctxt->src.val;
2895 al %= ctxt->src.val;
2896
2897 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2898
2899 /* Set PF, ZF, SF */
2900 ctxt->src.type = OP_IMM;
2901 ctxt->src.val = 0;
2902 ctxt->src.bytes = 1;
2903 fastop(ctxt, em_or);
2904
2905 return X86EMUL_CONTINUE;
2906 }
2907
2908 static int em_aad(struct x86_emulate_ctxt *ctxt)
2909 {
2910 u8 al = ctxt->dst.val & 0xff;
2911 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2912
2913 al = (al + (ah * ctxt->src.val)) & 0xff;
2914
2915 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2916
2917 /* Set PF, ZF, SF */
2918 ctxt->src.type = OP_IMM;
2919 ctxt->src.val = 0;
2920 ctxt->src.bytes = 1;
2921 fastop(ctxt, em_or);
2922
2923 return X86EMUL_CONTINUE;
2924 }
2925
2926 static int em_call(struct x86_emulate_ctxt *ctxt)
2927 {
2928 int rc;
2929 long rel = ctxt->src.val;
2930
2931 ctxt->src.val = (unsigned long)ctxt->_eip;
2932 rc = jmp_rel(ctxt, rel);
2933 if (rc != X86EMUL_CONTINUE)
2934 return rc;
2935 return em_push(ctxt);
2936 }
2937
2938 static int em_call_far(struct x86_emulate_ctxt *ctxt)
2939 {
2940 u16 sel, old_cs;
2941 ulong old_eip;
2942 int rc;
2943 struct desc_struct old_desc, new_desc;
2944 const struct x86_emulate_ops *ops = ctxt->ops;
2945
2946 old_eip = ctxt->_eip;
2947 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
2948
2949 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2950 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, &new_desc);
2951 if (rc != X86EMUL_CONTINUE)
2952 return X86EMUL_CONTINUE;
2953
2954 rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
2955 if (rc != X86EMUL_CONTINUE)
2956 goto fail;
2957
2958 ctxt->src.val = old_cs;
2959 rc = em_push(ctxt);
2960 if (rc != X86EMUL_CONTINUE)
2961 goto fail;
2962
2963 ctxt->src.val = old_eip;
2964 rc = em_push(ctxt);
2965 /* If we failed, we tainted the memory, but the very least we should
2966 restore cs */
2967 if (rc != X86EMUL_CONTINUE)
2968 goto fail;
2969 return rc;
2970 fail:
2971 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2972 return rc;
2973
2974 }
2975
2976 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2977 {
2978 int rc;
2979 unsigned long eip;
2980
2981 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2982 if (rc != X86EMUL_CONTINUE)
2983 return rc;
2984 rc = assign_eip_near(ctxt, eip);
2985 if (rc != X86EMUL_CONTINUE)
2986 return rc;
2987 rsp_increment(ctxt, ctxt->src.val);
2988 return X86EMUL_CONTINUE;
2989 }
2990
2991 static int em_xchg(struct x86_emulate_ctxt *ctxt)
2992 {
2993 /* Write back the register source. */
2994 ctxt->src.val = ctxt->dst.val;
2995 write_register_operand(&ctxt->src);
2996
2997 /* Write back the memory destination with implicit LOCK prefix. */
2998 ctxt->dst.val = ctxt->src.orig_val;
2999 ctxt->lock_prefix = 1;
3000 return X86EMUL_CONTINUE;
3001 }
3002
3003 static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3004 {
3005 ctxt->dst.val = ctxt->src2.val;
3006 return fastop(ctxt, em_imul);
3007 }
3008
3009 static int em_cwd(struct x86_emulate_ctxt *ctxt)
3010 {
3011 ctxt->dst.type = OP_REG;
3012 ctxt->dst.bytes = ctxt->src.bytes;
3013 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
3014 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
3015
3016 return X86EMUL_CONTINUE;
3017 }
3018
3019 static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3020 {
3021 u64 tsc = 0;
3022
3023 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
3024 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3025 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
3026 return X86EMUL_CONTINUE;
3027 }
3028
3029 static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3030 {
3031 u64 pmc;
3032
3033 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
3034 return emulate_gp(ctxt, 0);
3035 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3036 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
3037 return X86EMUL_CONTINUE;
3038 }
3039
3040 static int em_mov(struct x86_emulate_ctxt *ctxt)
3041 {
3042 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
3043 return X86EMUL_CONTINUE;
3044 }
3045
3046 static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3047 {
3048 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3049 return emulate_gp(ctxt, 0);
3050
3051 /* Disable writeback. */
3052 ctxt->dst.type = OP_NONE;
3053 return X86EMUL_CONTINUE;
3054 }
3055
3056 static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3057 {
3058 unsigned long val;
3059
3060 if (ctxt->mode == X86EMUL_MODE_PROT64)
3061 val = ctxt->src.val & ~0ULL;
3062 else
3063 val = ctxt->src.val & ~0U;
3064
3065 /* #UD condition is already handled. */
3066 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3067 return emulate_gp(ctxt, 0);
3068
3069 /* Disable writeback. */
3070 ctxt->dst.type = OP_NONE;
3071 return X86EMUL_CONTINUE;
3072 }
3073
3074 static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3075 {
3076 u64 msr_data;
3077
3078 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3079 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3080 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
3081 return emulate_gp(ctxt, 0);
3082
3083 return X86EMUL_CONTINUE;
3084 }
3085
3086 static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3087 {
3088 u64 msr_data;
3089
3090 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
3091 return emulate_gp(ctxt, 0);
3092
3093 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3094 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
3095 return X86EMUL_CONTINUE;
3096 }
3097
3098 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3099 {
3100 if (ctxt->modrm_reg > VCPU_SREG_GS)
3101 return emulate_ud(ctxt);
3102
3103 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
3104 return X86EMUL_CONTINUE;
3105 }
3106
3107 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3108 {
3109 u16 sel = ctxt->src.val;
3110
3111 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
3112 return emulate_ud(ctxt);
3113
3114 if (ctxt->modrm_reg == VCPU_SREG_SS)
3115 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3116
3117 /* Disable writeback. */
3118 ctxt->dst.type = OP_NONE;
3119 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg, NULL);
3120 }
3121
3122 static int em_lldt(struct x86_emulate_ctxt *ctxt)
3123 {
3124 u16 sel = ctxt->src.val;
3125
3126 /* Disable writeback. */
3127 ctxt->dst.type = OP_NONE;
3128 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR, NULL);
3129 }
3130
3131 static int em_ltr(struct x86_emulate_ctxt *ctxt)
3132 {
3133 u16 sel = ctxt->src.val;
3134
3135 /* Disable writeback. */
3136 ctxt->dst.type = OP_NONE;
3137 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR, NULL);
3138 }
3139
3140 static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3141 {
3142 int rc;
3143 ulong linear;
3144
3145 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
3146 if (rc == X86EMUL_CONTINUE)
3147 ctxt->ops->invlpg(ctxt, linear);
3148 /* Disable writeback. */
3149 ctxt->dst.type = OP_NONE;
3150 return X86EMUL_CONTINUE;
3151 }
3152
3153 static int em_clts(struct x86_emulate_ctxt *ctxt)
3154 {
3155 ulong cr0;
3156
3157 cr0 = ctxt->ops->get_cr(ctxt, 0);
3158 cr0 &= ~X86_CR0_TS;
3159 ctxt->ops->set_cr(ctxt, 0, cr0);
3160 return X86EMUL_CONTINUE;
3161 }
3162
3163 static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3164 {
3165 int rc;
3166
3167 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
3168 return X86EMUL_UNHANDLEABLE;
3169
3170 rc = ctxt->ops->fix_hypercall(ctxt);
3171 if (rc != X86EMUL_CONTINUE)
3172 return rc;
3173
3174 /* Let the processor re-execute the fixed hypercall */
3175 ctxt->_eip = ctxt->eip;
3176 /* Disable writeback. */
3177 ctxt->dst.type = OP_NONE;
3178 return X86EMUL_CONTINUE;
3179 }
3180
3181 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3182 void (*get)(struct x86_emulate_ctxt *ctxt,
3183 struct desc_ptr *ptr))
3184 {
3185 struct desc_ptr desc_ptr;
3186
3187 if (ctxt->mode == X86EMUL_MODE_PROT64)
3188 ctxt->op_bytes = 8;
3189 get(ctxt, &desc_ptr);
3190 if (ctxt->op_bytes == 2) {
3191 ctxt->op_bytes = 4;
3192 desc_ptr.address &= 0x00ffffff;
3193 }
3194 /* Disable writeback. */
3195 ctxt->dst.type = OP_NONE;
3196 return segmented_write(ctxt, ctxt->dst.addr.mem,
3197 &desc_ptr, 2 + ctxt->op_bytes);
3198 }
3199
3200 static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3201 {
3202 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3203 }
3204
3205 static int em_sidt(struct x86_emulate_ctxt *ctxt)
3206 {
3207 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3208 }
3209
3210 static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3211 {
3212 struct desc_ptr desc_ptr;
3213 int rc;
3214
3215 if (ctxt->mode == X86EMUL_MODE_PROT64)
3216 ctxt->op_bytes = 8;
3217 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3218 &desc_ptr.size, &desc_ptr.address,
3219 ctxt->op_bytes);
3220 if (rc != X86EMUL_CONTINUE)
3221 return rc;
3222 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3223 /* Disable writeback. */
3224 ctxt->dst.type = OP_NONE;
3225 return X86EMUL_CONTINUE;
3226 }
3227
3228 static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
3229 {
3230 int rc;
3231
3232 rc = ctxt->ops->fix_hypercall(ctxt);
3233
3234 /* Disable writeback. */
3235 ctxt->dst.type = OP_NONE;
3236 return rc;
3237 }
3238
3239 static int em_lidt(struct x86_emulate_ctxt *ctxt)
3240 {
3241 struct desc_ptr desc_ptr;
3242 int rc;
3243
3244 if (ctxt->mode == X86EMUL_MODE_PROT64)
3245 ctxt->op_bytes = 8;
3246 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3247 &desc_ptr.size, &desc_ptr.address,
3248 ctxt->op_bytes);
3249 if (rc != X86EMUL_CONTINUE)
3250 return rc;
3251 ctxt->ops->set_idt(ctxt, &desc_ptr);
3252 /* Disable writeback. */
3253 ctxt->dst.type = OP_NONE;
3254 return X86EMUL_CONTINUE;
3255 }
3256
3257 static int em_smsw(struct x86_emulate_ctxt *ctxt)
3258 {
3259 ctxt->dst.bytes = 2;
3260 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3261 return X86EMUL_CONTINUE;
3262 }
3263
3264 static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3265 {
3266 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3267 | (ctxt->src.val & 0x0f));
3268 ctxt->dst.type = OP_NONE;
3269 return X86EMUL_CONTINUE;
3270 }
3271
3272 static int em_loop(struct x86_emulate_ctxt *ctxt)
3273 {
3274 int rc = X86EMUL_CONTINUE;
3275
3276 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3277 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
3278 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3279 rc = jmp_rel(ctxt, ctxt->src.val);
3280
3281 return rc;
3282 }
3283
3284 static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3285 {
3286 int rc = X86EMUL_CONTINUE;
3287
3288 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
3289 rc = jmp_rel(ctxt, ctxt->src.val);
3290
3291 return rc;
3292 }
3293
3294 static int em_in(struct x86_emulate_ctxt *ctxt)
3295 {
3296 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3297 &ctxt->dst.val))
3298 return X86EMUL_IO_NEEDED;
3299
3300 return X86EMUL_CONTINUE;
3301 }
3302
3303 static int em_out(struct x86_emulate_ctxt *ctxt)
3304 {
3305 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3306 &ctxt->src.val, 1);
3307 /* Disable writeback. */
3308 ctxt->dst.type = OP_NONE;
3309 return X86EMUL_CONTINUE;
3310 }
3311
3312 static int em_cli(struct x86_emulate_ctxt *ctxt)
3313 {
3314 if (emulator_bad_iopl(ctxt))
3315 return emulate_gp(ctxt, 0);
3316
3317 ctxt->eflags &= ~X86_EFLAGS_IF;
3318 return X86EMUL_CONTINUE;
3319 }
3320
3321 static int em_sti(struct x86_emulate_ctxt *ctxt)
3322 {
3323 if (emulator_bad_iopl(ctxt))
3324 return emulate_gp(ctxt, 0);
3325
3326 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3327 ctxt->eflags |= X86_EFLAGS_IF;
3328 return X86EMUL_CONTINUE;
3329 }
3330
3331 static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3332 {
3333 u32 eax, ebx, ecx, edx;
3334
3335 eax = reg_read(ctxt, VCPU_REGS_RAX);
3336 ecx = reg_read(ctxt, VCPU_REGS_RCX);
3337 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3338 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3339 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3340 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3341 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
3342 return X86EMUL_CONTINUE;
3343 }
3344
3345 static int em_lahf(struct x86_emulate_ctxt *ctxt)
3346 {
3347 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3348 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
3349 return X86EMUL_CONTINUE;
3350 }
3351
3352 static int em_bswap(struct x86_emulate_ctxt *ctxt)
3353 {
3354 switch (ctxt->op_bytes) {
3355 #ifdef CONFIG_X86_64
3356 case 8:
3357 asm("bswap %0" : "+r"(ctxt->dst.val));
3358 break;
3359 #endif
3360 default:
3361 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3362 break;
3363 }
3364 return X86EMUL_CONTINUE;
3365 }
3366
3367 static bool valid_cr(int nr)
3368 {
3369 switch (nr) {
3370 case 0:
3371 case 2 ... 4:
3372 case 8:
3373 return true;
3374 default:
3375 return false;
3376 }
3377 }
3378
3379 static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3380 {
3381 if (!valid_cr(ctxt->modrm_reg))
3382 return emulate_ud(ctxt);
3383
3384 return X86EMUL_CONTINUE;
3385 }
3386
3387 static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3388 {
3389 u64 new_val = ctxt->src.val64;
3390 int cr = ctxt->modrm_reg;
3391 u64 efer = 0;
3392
3393 static u64 cr_reserved_bits[] = {
3394 0xffffffff00000000ULL,
3395 0, 0, 0, /* CR3 checked later */
3396 CR4_RESERVED_BITS,
3397 0, 0, 0,
3398 CR8_RESERVED_BITS,
3399 };
3400
3401 if (!valid_cr(cr))
3402 return emulate_ud(ctxt);
3403
3404 if (new_val & cr_reserved_bits[cr])
3405 return emulate_gp(ctxt, 0);
3406
3407 switch (cr) {
3408 case 0: {
3409 u64 cr4;
3410 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3411 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3412 return emulate_gp(ctxt, 0);
3413
3414 cr4 = ctxt->ops->get_cr(ctxt, 4);
3415 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3416
3417 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3418 !(cr4 & X86_CR4_PAE))
3419 return emulate_gp(ctxt, 0);
3420
3421 break;
3422 }
3423 case 3: {
3424 u64 rsvd = 0;
3425
3426 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3427 if (efer & EFER_LMA)
3428 rsvd = CR3_L_MODE_RESERVED_BITS;
3429 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
3430 rsvd = CR3_PAE_RESERVED_BITS;
3431 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
3432 rsvd = CR3_NONPAE_RESERVED_BITS;
3433
3434 if (new_val & rsvd)
3435 return emulate_gp(ctxt, 0);
3436
3437 break;
3438 }
3439 case 4: {
3440 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3441
3442 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3443 return emulate_gp(ctxt, 0);
3444
3445 break;
3446 }
3447 }
3448
3449 return X86EMUL_CONTINUE;
3450 }
3451
3452 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3453 {
3454 unsigned long dr7;
3455
3456 ctxt->ops->get_dr(ctxt, 7, &dr7);
3457
3458 /* Check if DR7.Global_Enable is set */
3459 return dr7 & (1 << 13);
3460 }
3461
3462 static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3463 {
3464 int dr = ctxt->modrm_reg;
3465 u64 cr4;
3466
3467 if (dr > 7)
3468 return emulate_ud(ctxt);
3469
3470 cr4 = ctxt->ops->get_cr(ctxt, 4);
3471 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3472 return emulate_ud(ctxt);
3473
3474 if (check_dr7_gd(ctxt))
3475 return emulate_db(ctxt);
3476
3477 return X86EMUL_CONTINUE;
3478 }
3479
3480 static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3481 {
3482 u64 new_val = ctxt->src.val64;
3483 int dr = ctxt->modrm_reg;
3484
3485 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3486 return emulate_gp(ctxt, 0);
3487
3488 return check_dr_read(ctxt);
3489 }
3490
3491 static int check_svme(struct x86_emulate_ctxt *ctxt)
3492 {
3493 u64 efer;
3494
3495 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3496
3497 if (!(efer & EFER_SVME))
3498 return emulate_ud(ctxt);
3499
3500 return X86EMUL_CONTINUE;
3501 }
3502
3503 static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3504 {
3505 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
3506
3507 /* Valid physical address? */
3508 if (rax & 0xffff000000000000ULL)
3509 return emulate_gp(ctxt, 0);
3510
3511 return check_svme(ctxt);
3512 }
3513
3514 static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3515 {
3516 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3517
3518 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
3519 return emulate_ud(ctxt);
3520
3521 return X86EMUL_CONTINUE;
3522 }
3523
3524 static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3525 {
3526 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3527 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
3528
3529 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
3530 (rcx > 3))
3531 return emulate_gp(ctxt, 0);
3532
3533 return X86EMUL_CONTINUE;
3534 }
3535
3536 static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3537 {
3538 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3539 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
3540 return emulate_gp(ctxt, 0);
3541
3542 return X86EMUL_CONTINUE;
3543 }
3544
3545 static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3546 {
3547 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3548 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
3549 return emulate_gp(ctxt, 0);
3550
3551 return X86EMUL_CONTINUE;
3552 }
3553
3554 #define D(_y) { .flags = (_y) }
3555 #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
3556 #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3557 .check_perm = (_p) }
3558 #define N D(NotImpl)
3559 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
3560 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3561 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
3562 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
3563 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
3564 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
3565 #define II(_f, _e, _i) \
3566 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
3567 #define IIP(_f, _e, _i, _p) \
3568 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3569 .check_perm = (_p) }
3570 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
3571
3572 #define D2bv(_f) D((_f) | ByteOp), D(_f)
3573 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
3574 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
3575 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
3576 #define I2bvIP(_f, _e, _i, _p) \
3577 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
3578
3579 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3580 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3581 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
3582
3583 static const struct opcode group7_rm1[] = {
3584 DI(SrcNone | Priv, monitor),
3585 DI(SrcNone | Priv, mwait),
3586 N, N, N, N, N, N,
3587 };
3588
3589 static const struct opcode group7_rm3[] = {
3590 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3591 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3592 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3593 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3594 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3595 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3596 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3597 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
3598 };
3599
3600 static const struct opcode group7_rm7[] = {
3601 N,
3602 DIP(SrcNone, rdtscp, check_rdtsc),
3603 N, N, N, N, N, N,
3604 };
3605
3606 static const struct opcode group1[] = {
3607 F(Lock, em_add),
3608 F(Lock | PageTable, em_or),
3609 F(Lock, em_adc),
3610 F(Lock, em_sbb),
3611 F(Lock | PageTable, em_and),
3612 F(Lock, em_sub),
3613 F(Lock, em_xor),
3614 F(NoWrite, em_cmp),
3615 };
3616
3617 static const struct opcode group1A[] = {
3618 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
3619 };
3620
3621 static const struct opcode group2[] = {
3622 F(DstMem | ModRM, em_rol),
3623 F(DstMem | ModRM, em_ror),
3624 F(DstMem | ModRM, em_rcl),
3625 F(DstMem | ModRM, em_rcr),
3626 F(DstMem | ModRM, em_shl),
3627 F(DstMem | ModRM, em_shr),
3628 F(DstMem | ModRM, em_shl),
3629 F(DstMem | ModRM, em_sar),
3630 };
3631
3632 static const struct opcode group3[] = {
3633 F(DstMem | SrcImm | NoWrite, em_test),
3634 F(DstMem | SrcImm | NoWrite, em_test),
3635 F(DstMem | SrcNone | Lock, em_not),
3636 F(DstMem | SrcNone | Lock, em_neg),
3637 F(DstXacc | Src2Mem, em_mul_ex),
3638 F(DstXacc | Src2Mem, em_imul_ex),
3639 F(DstXacc | Src2Mem, em_div_ex),
3640 F(DstXacc | Src2Mem, em_idiv_ex),
3641 };
3642
3643 static const struct opcode group4[] = {
3644 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3645 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
3646 N, N, N, N, N, N,
3647 };
3648
3649 static const struct opcode group5[] = {
3650 F(DstMem | SrcNone | Lock, em_inc),
3651 F(DstMem | SrcNone | Lock, em_dec),
3652 I(SrcMem | NearBranch, em_call_near_abs),
3653 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3654 I(SrcMem | NearBranch, em_jmp_abs),
3655 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3656 I(SrcMem | Stack, em_push), D(Undefined),
3657 };
3658
3659 static const struct opcode group6[] = {
3660 DI(Prot, sldt),
3661 DI(Prot, str),
3662 II(Prot | Priv | SrcMem16, em_lldt, lldt),
3663 II(Prot | Priv | SrcMem16, em_ltr, ltr),
3664 N, N, N, N,
3665 };
3666
3667 static const struct group_dual group7 = { {
3668 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3669 II(Mov | DstMem | Priv, em_sidt, sidt),
3670 II(SrcMem | Priv, em_lgdt, lgdt),
3671 II(SrcMem | Priv, em_lidt, lidt),
3672 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3673 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3674 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
3675 }, {
3676 I(SrcNone | Priv | VendorSpecific, em_vmcall),
3677 EXT(0, group7_rm1),
3678 N, EXT(0, group7_rm3),
3679 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3680 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3681 EXT(0, group7_rm7),
3682 } };
3683
3684 static const struct opcode group8[] = {
3685 N, N, N, N,
3686 F(DstMem | SrcImmByte | NoWrite, em_bt),
3687 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3688 F(DstMem | SrcImmByte | Lock, em_btr),
3689 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
3690 };
3691
3692 static const struct group_dual group9 = { {
3693 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
3694 }, {
3695 N, N, N, N, N, N, N, N,
3696 } };
3697
3698 static const struct opcode group11[] = {
3699 I(DstMem | SrcImm | Mov | PageTable, em_mov),
3700 X7(D(Undefined)),
3701 };
3702
3703 static const struct gprefix pfx_0f_6f_0f_7f = {
3704 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
3705 };
3706
3707 static const struct gprefix pfx_vmovntpx = {
3708 I(0, em_mov), N, N, N,
3709 };
3710
3711 static const struct escape escape_d9 = { {
3712 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3713 }, {
3714 /* 0xC0 - 0xC7 */
3715 N, N, N, N, N, N, N, N,
3716 /* 0xC8 - 0xCF */
3717 N, N, N, N, N, N, N, N,
3718 /* 0xD0 - 0xC7 */
3719 N, N, N, N, N, N, N, N,
3720 /* 0xD8 - 0xDF */
3721 N, N, N, N, N, N, N, N,
3722 /* 0xE0 - 0xE7 */
3723 N, N, N, N, N, N, N, N,
3724 /* 0xE8 - 0xEF */
3725 N, N, N, N, N, N, N, N,
3726 /* 0xF0 - 0xF7 */
3727 N, N, N, N, N, N, N, N,
3728 /* 0xF8 - 0xFF */
3729 N, N, N, N, N, N, N, N,
3730 } };
3731
3732 static const struct escape escape_db = { {
3733 N, N, N, N, N, N, N, N,
3734 }, {
3735 /* 0xC0 - 0xC7 */
3736 N, N, N, N, N, N, N, N,
3737 /* 0xC8 - 0xCF */
3738 N, N, N, N, N, N, N, N,
3739 /* 0xD0 - 0xC7 */
3740 N, N, N, N, N, N, N, N,
3741 /* 0xD8 - 0xDF */
3742 N, N, N, N, N, N, N, N,
3743 /* 0xE0 - 0xE7 */
3744 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3745 /* 0xE8 - 0xEF */
3746 N, N, N, N, N, N, N, N,
3747 /* 0xF0 - 0xF7 */
3748 N, N, N, N, N, N, N, N,
3749 /* 0xF8 - 0xFF */
3750 N, N, N, N, N, N, N, N,
3751 } };
3752
3753 static const struct escape escape_dd = { {
3754 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3755 }, {
3756 /* 0xC0 - 0xC7 */
3757 N, N, N, N, N, N, N, N,
3758 /* 0xC8 - 0xCF */
3759 N, N, N, N, N, N, N, N,
3760 /* 0xD0 - 0xC7 */
3761 N, N, N, N, N, N, N, N,
3762 /* 0xD8 - 0xDF */
3763 N, N, N, N, N, N, N, N,
3764 /* 0xE0 - 0xE7 */
3765 N, N, N, N, N, N, N, N,
3766 /* 0xE8 - 0xEF */
3767 N, N, N, N, N, N, N, N,
3768 /* 0xF0 - 0xF7 */
3769 N, N, N, N, N, N, N, N,
3770 /* 0xF8 - 0xFF */
3771 N, N, N, N, N, N, N, N,
3772 } };
3773
3774 static const struct opcode opcode_table[256] = {
3775 /* 0x00 - 0x07 */
3776 F6ALU(Lock, em_add),
3777 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3778 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
3779 /* 0x08 - 0x0F */
3780 F6ALU(Lock | PageTable, em_or),
3781 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3782 N,
3783 /* 0x10 - 0x17 */
3784 F6ALU(Lock, em_adc),
3785 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3786 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
3787 /* 0x18 - 0x1F */
3788 F6ALU(Lock, em_sbb),
3789 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3790 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
3791 /* 0x20 - 0x27 */
3792 F6ALU(Lock | PageTable, em_and), N, N,
3793 /* 0x28 - 0x2F */
3794 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
3795 /* 0x30 - 0x37 */
3796 F6ALU(Lock, em_xor), N, N,
3797 /* 0x38 - 0x3F */
3798 F6ALU(NoWrite, em_cmp), N, N,
3799 /* 0x40 - 0x4F */
3800 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
3801 /* 0x50 - 0x57 */
3802 X8(I(SrcReg | Stack, em_push)),
3803 /* 0x58 - 0x5F */
3804 X8(I(DstReg | Stack, em_pop)),
3805 /* 0x60 - 0x67 */
3806 I(ImplicitOps | Stack | No64, em_pusha),
3807 I(ImplicitOps | Stack | No64, em_popa),
3808 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3809 N, N, N, N,
3810 /* 0x68 - 0x6F */
3811 I(SrcImm | Mov | Stack, em_push),
3812 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
3813 I(SrcImmByte | Mov | Stack, em_push),
3814 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
3815 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
3816 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
3817 /* 0x70 - 0x7F */
3818 X16(D(SrcImmByte | NearBranch)),
3819 /* 0x80 - 0x87 */
3820 G(ByteOp | DstMem | SrcImm, group1),
3821 G(DstMem | SrcImm, group1),
3822 G(ByteOp | DstMem | SrcImm | No64, group1),
3823 G(DstMem | SrcImmByte, group1),
3824 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
3825 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
3826 /* 0x88 - 0x8F */
3827 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
3828 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
3829 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
3830 D(ModRM | SrcMem | NoAccess | DstReg),
3831 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3832 G(0, group1A),
3833 /* 0x90 - 0x97 */
3834 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
3835 /* 0x98 - 0x9F */
3836 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
3837 I(SrcImmFAddr | No64, em_call_far), N,
3838 II(ImplicitOps | Stack, em_pushf, pushf),
3839 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
3840 /* 0xA0 - 0xA7 */
3841 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3842 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
3843 I2bv(SrcSI | DstDI | Mov | String, em_mov),
3844 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
3845 /* 0xA8 - 0xAF */
3846 F2bv(DstAcc | SrcImm | NoWrite, em_test),
3847 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3848 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
3849 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
3850 /* 0xB0 - 0xB7 */
3851 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
3852 /* 0xB8 - 0xBF */
3853 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
3854 /* 0xC0 - 0xC7 */
3855 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
3856 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
3857 I(ImplicitOps | NearBranch, em_ret),
3858 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3859 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
3860 G(ByteOp, group11), G(0, group11),
3861 /* 0xC8 - 0xCF */
3862 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3863 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3864 I(ImplicitOps | Stack, em_ret_far),
3865 D(ImplicitOps), DI(SrcImmByte, intn),
3866 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
3867 /* 0xD0 - 0xD7 */
3868 G(Src2One | ByteOp, group2), G(Src2One, group2),
3869 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
3870 I(DstAcc | SrcImmUByte | No64, em_aam),
3871 I(DstAcc | SrcImmUByte | No64, em_aad),
3872 F(DstAcc | ByteOp | No64, em_salc),
3873 I(DstAcc | SrcXLat | ByteOp, em_mov),
3874 /* 0xD8 - 0xDF */
3875 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
3876 /* 0xE0 - 0xE7 */
3877 X3(I(SrcImmByte, em_loop)),
3878 I(SrcImmByte | NearBranch, em_jcxz),
3879 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3880 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
3881 /* 0xE8 - 0xEF */
3882 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps),
3883 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
3884 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3885 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
3886 /* 0xF0 - 0xF7 */
3887 N, DI(ImplicitOps, icebp), N, N,
3888 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3889 G(ByteOp, group3), G(0, group3),
3890 /* 0xF8 - 0xFF */
3891 D(ImplicitOps), D(ImplicitOps),
3892 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
3893 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3894 };
3895
3896 static const struct opcode twobyte_table[256] = {
3897 /* 0x00 - 0x0F */
3898 G(0, group6), GD(0, &group7), N, N,
3899 N, I(ImplicitOps | VendorSpecific, em_syscall),
3900 II(ImplicitOps | Priv, em_clts, clts), N,
3901 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3902 N, D(ImplicitOps | ModRM), N, N,
3903 /* 0x10 - 0x1F */
3904 N, N, N, N, N, N, N, N,
3905 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
3906 /* 0x20 - 0x2F */
3907 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3908 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
3909 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3910 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
3911 N, N, N, N,
3912 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3913 N, N, N, N,
3914 /* 0x30 - 0x3F */
3915 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
3916 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3917 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
3918 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
3919 I(ImplicitOps | VendorSpecific, em_sysenter),
3920 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
3921 N, N,
3922 N, N, N, N, N, N, N, N,
3923 /* 0x40 - 0x4F */
3924 X16(D(DstReg | SrcMem | ModRM | Mov)),
3925 /* 0x50 - 0x5F */
3926 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3927 /* 0x60 - 0x6F */
3928 N, N, N, N,
3929 N, N, N, N,
3930 N, N, N, N,
3931 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
3932 /* 0x70 - 0x7F */
3933 N, N, N, N,
3934 N, N, N, N,
3935 N, N, N, N,
3936 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
3937 /* 0x80 - 0x8F */
3938 X16(D(SrcImm)),
3939 /* 0x90 - 0x9F */
3940 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
3941 /* 0xA0 - 0xA7 */
3942 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
3943 II(ImplicitOps, em_cpuid, cpuid),
3944 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
3945 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3946 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
3947 /* 0xA8 - 0xAF */
3948 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
3949 DI(ImplicitOps, rsm),
3950 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
3951 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3952 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
3953 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
3954 /* 0xB0 - 0xB7 */
3955 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
3956 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
3957 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
3958 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3959 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
3960 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3961 /* 0xB8 - 0xBF */
3962 N, N,
3963 G(BitOp, group8),
3964 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3965 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
3966 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3967 /* 0xC0 - 0xC7 */
3968 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
3969 N, D(DstMem | SrcReg | ModRM | Mov),
3970 N, N, N, GD(0, &group9),
3971 /* 0xC8 - 0xCF */
3972 X8(I(DstReg, em_bswap)),
3973 /* 0xD0 - 0xDF */
3974 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3975 /* 0xE0 - 0xEF */
3976 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3977 /* 0xF0 - 0xFF */
3978 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3979 };
3980
3981 #undef D
3982 #undef N
3983 #undef G
3984 #undef GD
3985 #undef I
3986 #undef GP
3987 #undef EXT
3988
3989 #undef D2bv
3990 #undef D2bvIP
3991 #undef I2bv
3992 #undef I2bvIP
3993 #undef I6ALU
3994
3995 static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
3996 {
3997 unsigned size;
3998
3999 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4000 if (size == 8)
4001 size = 4;
4002 return size;
4003 }
4004
4005 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4006 unsigned size, bool sign_extension)
4007 {
4008 int rc = X86EMUL_CONTINUE;
4009
4010 op->type = OP_IMM;
4011 op->bytes = size;
4012 op->addr.mem.ea = ctxt->_eip;
4013 /* NB. Immediates are sign-extended as necessary. */
4014 switch (op->bytes) {
4015 case 1:
4016 op->val = insn_fetch(s8, ctxt);
4017 break;
4018 case 2:
4019 op->val = insn_fetch(s16, ctxt);
4020 break;
4021 case 4:
4022 op->val = insn_fetch(s32, ctxt);
4023 break;
4024 case 8:
4025 op->val = insn_fetch(s64, ctxt);
4026 break;
4027 }
4028 if (!sign_extension) {
4029 switch (op->bytes) {
4030 case 1:
4031 op->val &= 0xff;
4032 break;
4033 case 2:
4034 op->val &= 0xffff;
4035 break;
4036 case 4:
4037 op->val &= 0xffffffff;
4038 break;
4039 }
4040 }
4041 done:
4042 return rc;
4043 }
4044
4045 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4046 unsigned d)
4047 {
4048 int rc = X86EMUL_CONTINUE;
4049
4050 switch (d) {
4051 case OpReg:
4052 decode_register_operand(ctxt, op);
4053 break;
4054 case OpImmUByte:
4055 rc = decode_imm(ctxt, op, 1, false);
4056 break;
4057 case OpMem:
4058 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4059 mem_common:
4060 *op = ctxt->memop;
4061 ctxt->memopp = op;
4062 if ((ctxt->d & BitOp) && op == &ctxt->dst)
4063 fetch_bit_operand(ctxt);
4064 op->orig_val = op->val;
4065 break;
4066 case OpMem64:
4067 ctxt->memop.bytes = 8;
4068 goto mem_common;
4069 case OpAcc:
4070 op->type = OP_REG;
4071 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4072 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4073 fetch_register_operand(op);
4074 op->orig_val = op->val;
4075 break;
4076 case OpAccLo:
4077 op->type = OP_REG;
4078 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4079 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4080 fetch_register_operand(op);
4081 op->orig_val = op->val;
4082 break;
4083 case OpAccHi:
4084 if (ctxt->d & ByteOp) {
4085 op->type = OP_NONE;
4086 break;
4087 }
4088 op->type = OP_REG;
4089 op->bytes = ctxt->op_bytes;
4090 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4091 fetch_register_operand(op);
4092 op->orig_val = op->val;
4093 break;
4094 case OpDI:
4095 op->type = OP_MEM;
4096 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4097 op->addr.mem.ea =
4098 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
4099 op->addr.mem.seg = VCPU_SREG_ES;
4100 op->val = 0;
4101 op->count = 1;
4102 break;
4103 case OpDX:
4104 op->type = OP_REG;
4105 op->bytes = 2;
4106 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4107 fetch_register_operand(op);
4108 break;
4109 case OpCL:
4110 op->bytes = 1;
4111 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4112 break;
4113 case OpImmByte:
4114 rc = decode_imm(ctxt, op, 1, true);
4115 break;
4116 case OpOne:
4117 op->bytes = 1;
4118 op->val = 1;
4119 break;
4120 case OpImm:
4121 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4122 break;
4123 case OpImm64:
4124 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4125 break;
4126 case OpMem8:
4127 ctxt->memop.bytes = 1;
4128 if (ctxt->memop.type == OP_REG) {
4129 int highbyte_regs = ctxt->rex_prefix == 0;
4130
4131 ctxt->memop.addr.reg = decode_register(ctxt, ctxt->modrm_rm,
4132 highbyte_regs);
4133 fetch_register_operand(&ctxt->memop);
4134 }
4135 goto mem_common;
4136 case OpMem16:
4137 ctxt->memop.bytes = 2;
4138 goto mem_common;
4139 case OpMem32:
4140 ctxt->memop.bytes = 4;
4141 goto mem_common;
4142 case OpImmU16:
4143 rc = decode_imm(ctxt, op, 2, false);
4144 break;
4145 case OpImmU:
4146 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4147 break;
4148 case OpSI:
4149 op->type = OP_MEM;
4150 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4151 op->addr.mem.ea =
4152 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
4153 op->addr.mem.seg = seg_override(ctxt);
4154 op->val = 0;
4155 op->count = 1;
4156 break;
4157 case OpXLat:
4158 op->type = OP_MEM;
4159 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4160 op->addr.mem.ea =
4161 register_address(ctxt,
4162 reg_read(ctxt, VCPU_REGS_RBX) +
4163 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4164 op->addr.mem.seg = seg_override(ctxt);
4165 op->val = 0;
4166 break;
4167 case OpImmFAddr:
4168 op->type = OP_IMM;
4169 op->addr.mem.ea = ctxt->_eip;
4170 op->bytes = ctxt->op_bytes + 2;
4171 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4172 break;
4173 case OpMemFAddr:
4174 ctxt->memop.bytes = ctxt->op_bytes + 2;
4175 goto mem_common;
4176 case OpES:
4177 op->val = VCPU_SREG_ES;
4178 break;
4179 case OpCS:
4180 op->val = VCPU_SREG_CS;
4181 break;
4182 case OpSS:
4183 op->val = VCPU_SREG_SS;
4184 break;
4185 case OpDS:
4186 op->val = VCPU_SREG_DS;
4187 break;
4188 case OpFS:
4189 op->val = VCPU_SREG_FS;
4190 break;
4191 case OpGS:
4192 op->val = VCPU_SREG_GS;
4193 break;
4194 case OpImplicit:
4195 /* Special instructions do their own operand decoding. */
4196 default:
4197 op->type = OP_NONE; /* Disable writeback. */
4198 break;
4199 }
4200
4201 done:
4202 return rc;
4203 }
4204
4205 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
4206 {
4207 int rc = X86EMUL_CONTINUE;
4208 int mode = ctxt->mode;
4209 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
4210 bool op_prefix = false;
4211 struct opcode opcode;
4212
4213 ctxt->memop.type = OP_NONE;
4214 ctxt->memopp = NULL;
4215 ctxt->_eip = ctxt->eip;
4216 ctxt->fetch.start = ctxt->_eip;
4217 ctxt->fetch.end = ctxt->fetch.start + insn_len;
4218 if (insn_len > 0)
4219 memcpy(ctxt->fetch.data, insn, insn_len);
4220
4221 switch (mode) {
4222 case X86EMUL_MODE_REAL:
4223 case X86EMUL_MODE_VM86:
4224 case X86EMUL_MODE_PROT16:
4225 def_op_bytes = def_ad_bytes = 2;
4226 break;
4227 case X86EMUL_MODE_PROT32:
4228 def_op_bytes = def_ad_bytes = 4;
4229 break;
4230 #ifdef CONFIG_X86_64
4231 case X86EMUL_MODE_PROT64:
4232 def_op_bytes = 4;
4233 def_ad_bytes = 8;
4234 break;
4235 #endif
4236 default:
4237 return EMULATION_FAILED;
4238 }
4239
4240 ctxt->op_bytes = def_op_bytes;
4241 ctxt->ad_bytes = def_ad_bytes;
4242
4243 /* Legacy prefixes. */
4244 for (;;) {
4245 switch (ctxt->b = insn_fetch(u8, ctxt)) {
4246 case 0x66: /* operand-size override */
4247 op_prefix = true;
4248 /* switch between 2/4 bytes */
4249 ctxt->op_bytes = def_op_bytes ^ 6;
4250 break;
4251 case 0x67: /* address-size override */
4252 if (mode == X86EMUL_MODE_PROT64)
4253 /* switch between 4/8 bytes */
4254 ctxt->ad_bytes = def_ad_bytes ^ 12;
4255 else
4256 /* switch between 2/4 bytes */
4257 ctxt->ad_bytes = def_ad_bytes ^ 6;
4258 break;
4259 case 0x26: /* ES override */
4260 case 0x2e: /* CS override */
4261 case 0x36: /* SS override */
4262 case 0x3e: /* DS override */
4263 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
4264 break;
4265 case 0x64: /* FS override */
4266 case 0x65: /* GS override */
4267 set_seg_override(ctxt, ctxt->b & 7);
4268 break;
4269 case 0x40 ... 0x4f: /* REX */
4270 if (mode != X86EMUL_MODE_PROT64)
4271 goto done_prefixes;
4272 ctxt->rex_prefix = ctxt->b;
4273 continue;
4274 case 0xf0: /* LOCK */
4275 ctxt->lock_prefix = 1;
4276 break;
4277 case 0xf2: /* REPNE/REPNZ */
4278 case 0xf3: /* REP/REPE/REPZ */
4279 ctxt->rep_prefix = ctxt->b;
4280 break;
4281 default:
4282 goto done_prefixes;
4283 }
4284
4285 /* Any legacy prefix after a REX prefix nullifies its effect. */
4286
4287 ctxt->rex_prefix = 0;
4288 }
4289
4290 done_prefixes:
4291
4292 /* REX prefix. */
4293 if (ctxt->rex_prefix & 8)
4294 ctxt->op_bytes = 8; /* REX.W */
4295
4296 /* Opcode byte(s). */
4297 opcode = opcode_table[ctxt->b];
4298 /* Two-byte opcode? */
4299 if (ctxt->b == 0x0f) {
4300 ctxt->twobyte = 1;
4301 ctxt->b = insn_fetch(u8, ctxt);
4302 opcode = twobyte_table[ctxt->b];
4303 }
4304 ctxt->d = opcode.flags;
4305
4306 if (ctxt->d & ModRM)
4307 ctxt->modrm = insn_fetch(u8, ctxt);
4308
4309 while (ctxt->d & GroupMask) {
4310 switch (ctxt->d & GroupMask) {
4311 case Group:
4312 goffset = (ctxt->modrm >> 3) & 7;
4313 opcode = opcode.u.group[goffset];
4314 break;
4315 case GroupDual:
4316 goffset = (ctxt->modrm >> 3) & 7;
4317 if ((ctxt->modrm >> 6) == 3)
4318 opcode = opcode.u.gdual->mod3[goffset];
4319 else
4320 opcode = opcode.u.gdual->mod012[goffset];
4321 break;
4322 case RMExt:
4323 goffset = ctxt->modrm & 7;
4324 opcode = opcode.u.group[goffset];
4325 break;
4326 case Prefix:
4327 if (ctxt->rep_prefix && op_prefix)
4328 return EMULATION_FAILED;
4329 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
4330 switch (simd_prefix) {
4331 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4332 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4333 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4334 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4335 }
4336 break;
4337 case Escape:
4338 if (ctxt->modrm > 0xbf)
4339 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4340 else
4341 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4342 break;
4343 default:
4344 return EMULATION_FAILED;
4345 }
4346
4347 ctxt->d &= ~(u64)GroupMask;
4348 ctxt->d |= opcode.flags;
4349 }
4350
4351 ctxt->execute = opcode.u.execute;
4352 ctxt->check_perm = opcode.check_perm;
4353 ctxt->intercept = opcode.intercept;
4354
4355 /* Unrecognised? */
4356 if (ctxt->d == 0 || (ctxt->d & NotImpl))
4357 return EMULATION_FAILED;
4358
4359 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
4360 return EMULATION_FAILED;
4361
4362 if (mode == X86EMUL_MODE_PROT64) {
4363 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4364 ctxt->op_bytes = 8;
4365 else if (ctxt->d & NearBranch)
4366 ctxt->op_bytes = 8;
4367 }
4368
4369 if (ctxt->d & Op3264) {
4370 if (mode == X86EMUL_MODE_PROT64)
4371 ctxt->op_bytes = 8;
4372 else
4373 ctxt->op_bytes = 4;
4374 }
4375
4376 if (ctxt->d & Sse)
4377 ctxt->op_bytes = 16;
4378 else if (ctxt->d & Mmx)
4379 ctxt->op_bytes = 8;
4380
4381 /* ModRM and SIB bytes. */
4382 if (ctxt->d & ModRM) {
4383 rc = decode_modrm(ctxt, &ctxt->memop);
4384 if (!ctxt->has_seg_override)
4385 set_seg_override(ctxt, ctxt->modrm_seg);
4386 } else if (ctxt->d & MemAbs)
4387 rc = decode_abs(ctxt, &ctxt->memop);
4388 if (rc != X86EMUL_CONTINUE)
4389 goto done;
4390
4391 if (!ctxt->has_seg_override)
4392 set_seg_override(ctxt, VCPU_SREG_DS);
4393
4394 ctxt->memop.addr.mem.seg = seg_override(ctxt);
4395
4396 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4397 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
4398
4399 /*
4400 * Decode and fetch the source operand: register, memory
4401 * or immediate.
4402 */
4403 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
4404 if (rc != X86EMUL_CONTINUE)
4405 goto done;
4406
4407 /*
4408 * Decode and fetch the second source operand: register, memory
4409 * or immediate.
4410 */
4411 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
4412 if (rc != X86EMUL_CONTINUE)
4413 goto done;
4414
4415 /* Decode and fetch the destination operand: register or memory. */
4416 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
4417
4418 done:
4419 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4420 ctxt->memopp->addr.mem.ea += ctxt->_eip;
4421
4422 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
4423 }
4424
4425 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4426 {
4427 return ctxt->d & PageTable;
4428 }
4429
4430 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4431 {
4432 /* The second termination condition only applies for REPE
4433 * and REPNE. Test if the repeat string operation prefix is
4434 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4435 * corresponding termination condition according to:
4436 * - if REPE/REPZ and ZF = 0 then done
4437 * - if REPNE/REPNZ and ZF = 1 then done
4438 */
4439 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4440 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4441 && (((ctxt->rep_prefix == REPE_PREFIX) &&
4442 ((ctxt->eflags & EFLG_ZF) == 0))
4443 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
4444 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4445 return true;
4446
4447 return false;
4448 }
4449
4450 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4451 {
4452 bool fault = false;
4453
4454 ctxt->ops->get_fpu(ctxt);
4455 asm volatile("1: fwait \n\t"
4456 "2: \n\t"
4457 ".pushsection .fixup,\"ax\" \n\t"
4458 "3: \n\t"
4459 "movb $1, %[fault] \n\t"
4460 "jmp 2b \n\t"
4461 ".popsection \n\t"
4462 _ASM_EXTABLE(1b, 3b)
4463 : [fault]"+qm"(fault));
4464 ctxt->ops->put_fpu(ctxt);
4465
4466 if (unlikely(fault))
4467 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4468
4469 return X86EMUL_CONTINUE;
4470 }
4471
4472 static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4473 struct operand *op)
4474 {
4475 if (op->type == OP_MM)
4476 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4477 }
4478
4479 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4480 {
4481 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4482 if (!(ctxt->d & ByteOp))
4483 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4484 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4485 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4486 [fastop]"+S"(fop)
4487 : "c"(ctxt->src2.val));
4488 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4489 if (!fop) /* exception is returned in fop variable */
4490 return emulate_de(ctxt);
4491 return X86EMUL_CONTINUE;
4492 }
4493
4494 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
4495 {
4496 const struct x86_emulate_ops *ops = ctxt->ops;
4497 int rc = X86EMUL_CONTINUE;
4498 int saved_dst_type = ctxt->dst.type;
4499
4500 ctxt->mem_read.pos = 0;
4501
4502 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4503 (ctxt->d & Undefined)) {
4504 rc = emulate_ud(ctxt);
4505 goto done;
4506 }
4507
4508 /* LOCK prefix is allowed only with some instructions */
4509 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
4510 rc = emulate_ud(ctxt);
4511 goto done;
4512 }
4513
4514 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
4515 rc = emulate_ud(ctxt);
4516 goto done;
4517 }
4518
4519 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4520 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4521 rc = emulate_ud(ctxt);
4522 goto done;
4523 }
4524
4525 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4526 rc = emulate_nm(ctxt);
4527 goto done;
4528 }
4529
4530 if (ctxt->d & Mmx) {
4531 rc = flush_pending_x87_faults(ctxt);
4532 if (rc != X86EMUL_CONTINUE)
4533 goto done;
4534 /*
4535 * Now that we know the fpu is exception safe, we can fetch
4536 * operands from it.
4537 */
4538 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4539 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4540 if (!(ctxt->d & Mov))
4541 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4542 }
4543
4544 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4545 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4546 X86_ICPT_PRE_EXCEPT);
4547 if (rc != X86EMUL_CONTINUE)
4548 goto done;
4549 }
4550
4551 /* Privileged instruction can be executed only in CPL=0 */
4552 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
4553 rc = emulate_gp(ctxt, 0);
4554 goto done;
4555 }
4556
4557 /* Instruction can only be executed in protected mode */
4558 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4559 rc = emulate_ud(ctxt);
4560 goto done;
4561 }
4562
4563 /* Do instruction specific permission checks */
4564 if (ctxt->check_perm) {
4565 rc = ctxt->check_perm(ctxt);
4566 if (rc != X86EMUL_CONTINUE)
4567 goto done;
4568 }
4569
4570 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4571 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4572 X86_ICPT_POST_EXCEPT);
4573 if (rc != X86EMUL_CONTINUE)
4574 goto done;
4575 }
4576
4577 if (ctxt->rep_prefix && (ctxt->d & String)) {
4578 /* All REP prefixes have the same first termination condition */
4579 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4580 ctxt->eip = ctxt->_eip;
4581 goto done;
4582 }
4583 }
4584
4585 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4586 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4587 ctxt->src.valptr, ctxt->src.bytes);
4588 if (rc != X86EMUL_CONTINUE)
4589 goto done;
4590 ctxt->src.orig_val64 = ctxt->src.val64;
4591 }
4592
4593 if (ctxt->src2.type == OP_MEM) {
4594 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4595 &ctxt->src2.val, ctxt->src2.bytes);
4596 if (rc != X86EMUL_CONTINUE)
4597 goto done;
4598 }
4599
4600 if ((ctxt->d & DstMask) == ImplicitOps)
4601 goto special_insn;
4602
4603
4604 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
4605 /* optimisation - avoid slow emulated read if Mov */
4606 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4607 &ctxt->dst.val, ctxt->dst.bytes);
4608 if (rc != X86EMUL_CONTINUE)
4609 goto done;
4610 }
4611 /* Copy full 64-bit value for CMPXCHG8B. */
4612 ctxt->dst.orig_val64 = ctxt->dst.val64;
4613
4614 special_insn:
4615
4616 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4617 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4618 X86_ICPT_POST_MEMACCESS);
4619 if (rc != X86EMUL_CONTINUE)
4620 goto done;
4621 }
4622
4623 if (ctxt->execute) {
4624 if (ctxt->d & Fastop) {
4625 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4626 rc = fastop(ctxt, fop);
4627 if (rc != X86EMUL_CONTINUE)
4628 goto done;
4629 goto writeback;
4630 }
4631 rc = ctxt->execute(ctxt);
4632 if (rc != X86EMUL_CONTINUE)
4633 goto done;
4634 goto writeback;
4635 }
4636
4637 if (ctxt->twobyte)
4638 goto twobyte_insn;
4639
4640 switch (ctxt->b) {
4641 case 0x63: /* movsxd */
4642 if (ctxt->mode != X86EMUL_MODE_PROT64)
4643 goto cannot_emulate;
4644 ctxt->dst.val = (s32) ctxt->src.val;
4645 break;
4646 case 0x70 ... 0x7f: /* jcc (short) */
4647 if (test_cc(ctxt->b, ctxt->eflags))
4648 rc = jmp_rel(ctxt, ctxt->src.val);
4649 break;
4650 case 0x8d: /* lea r16/r32, m */
4651 ctxt->dst.val = ctxt->src.addr.mem.ea;
4652 break;
4653 case 0x90 ... 0x97: /* nop / xchg reg, rax */
4654 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
4655 break;
4656 rc = em_xchg(ctxt);
4657 break;
4658 case 0x98: /* cbw/cwde/cdqe */
4659 switch (ctxt->op_bytes) {
4660 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4661 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4662 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
4663 }
4664 break;
4665 case 0xcc: /* int3 */
4666 rc = emulate_int(ctxt, 3);
4667 break;
4668 case 0xcd: /* int n */
4669 rc = emulate_int(ctxt, ctxt->src.val);
4670 break;
4671 case 0xce: /* into */
4672 if (ctxt->eflags & EFLG_OF)
4673 rc = emulate_int(ctxt, 4);
4674 break;
4675 case 0xe9: /* jmp rel */
4676 case 0xeb: /* jmp rel short */
4677 rc = jmp_rel(ctxt, ctxt->src.val);
4678 ctxt->dst.type = OP_NONE; /* Disable writeback. */
4679 break;
4680 case 0xf4: /* hlt */
4681 ctxt->ops->halt(ctxt);
4682 break;
4683 case 0xf5: /* cmc */
4684 /* complement carry flag from eflags reg */
4685 ctxt->eflags ^= EFLG_CF;
4686 break;
4687 case 0xf8: /* clc */
4688 ctxt->eflags &= ~EFLG_CF;
4689 break;
4690 case 0xf9: /* stc */
4691 ctxt->eflags |= EFLG_CF;
4692 break;
4693 case 0xfc: /* cld */
4694 ctxt->eflags &= ~EFLG_DF;
4695 break;
4696 case 0xfd: /* std */
4697 ctxt->eflags |= EFLG_DF;
4698 break;
4699 default:
4700 goto cannot_emulate;
4701 }
4702
4703 if (rc != X86EMUL_CONTINUE)
4704 goto done;
4705
4706 writeback:
4707 if (!(ctxt->d & NoWrite)) {
4708 rc = writeback(ctxt, &ctxt->dst);
4709 if (rc != X86EMUL_CONTINUE)
4710 goto done;
4711 }
4712 if (ctxt->d & SrcWrite) {
4713 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4714 rc = writeback(ctxt, &ctxt->src);
4715 if (rc != X86EMUL_CONTINUE)
4716 goto done;
4717 }
4718
4719 /*
4720 * restore dst type in case the decoding will be reused
4721 * (happens for string instruction )
4722 */
4723 ctxt->dst.type = saved_dst_type;
4724
4725 if ((ctxt->d & SrcMask) == SrcSI)
4726 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
4727
4728 if ((ctxt->d & DstMask) == DstDI)
4729 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
4730
4731 if (ctxt->rep_prefix && (ctxt->d & String)) {
4732 unsigned int count;
4733 struct read_cache *r = &ctxt->io_read;
4734 if ((ctxt->d & SrcMask) == SrcSI)
4735 count = ctxt->src.count;
4736 else
4737 count = ctxt->dst.count;
4738 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4739 -count);
4740
4741 if (!string_insn_completed(ctxt)) {
4742 /*
4743 * Re-enter guest when pio read ahead buffer is empty
4744 * or, if it is not used, after each 1024 iteration.
4745 */
4746 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
4747 (r->end == 0 || r->end != r->pos)) {
4748 /*
4749 * Reset read cache. Usually happens before
4750 * decode, but since instruction is restarted
4751 * we have to do it here.
4752 */
4753 ctxt->mem_read.end = 0;
4754 writeback_registers(ctxt);
4755 return EMULATION_RESTART;
4756 }
4757 goto done; /* skip rip writeback */
4758 }
4759 }
4760
4761 ctxt->eip = ctxt->_eip;
4762
4763 done:
4764 if (rc == X86EMUL_PROPAGATE_FAULT)
4765 ctxt->have_exception = true;
4766 if (rc == X86EMUL_INTERCEPTED)
4767 return EMULATION_INTERCEPTED;
4768
4769 if (rc == X86EMUL_CONTINUE)
4770 writeback_registers(ctxt);
4771
4772 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
4773
4774 twobyte_insn:
4775 switch (ctxt->b) {
4776 case 0x09: /* wbinvd */
4777 (ctxt->ops->wbinvd)(ctxt);
4778 break;
4779 case 0x08: /* invd */
4780 case 0x0d: /* GrpP (prefetch) */
4781 case 0x18: /* Grp16 (prefetch/nop) */
4782 case 0x1f: /* nop */
4783 break;
4784 case 0x20: /* mov cr, reg */
4785 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
4786 break;
4787 case 0x21: /* mov from dr to reg */
4788 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
4789 break;
4790 case 0x40 ... 0x4f: /* cmov */
4791 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4792 if (!test_cc(ctxt->b, ctxt->eflags))
4793 ctxt->dst.type = OP_NONE; /* no writeback */
4794 break;
4795 case 0x80 ... 0x8f: /* jnz rel, etc*/
4796 if (test_cc(ctxt->b, ctxt->eflags))
4797 rc = jmp_rel(ctxt, ctxt->src.val);
4798 break;
4799 case 0x90 ... 0x9f: /* setcc r/m8 */
4800 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
4801 break;
4802 case 0xae: /* clflush */
4803 break;
4804 case 0xb6 ... 0xb7: /* movzx */
4805 ctxt->dst.bytes = ctxt->op_bytes;
4806 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
4807 : (u16) ctxt->src.val;
4808 break;
4809 case 0xbe ... 0xbf: /* movsx */
4810 ctxt->dst.bytes = ctxt->op_bytes;
4811 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
4812 (s16) ctxt->src.val;
4813 break;
4814 case 0xc3: /* movnti */
4815 ctxt->dst.bytes = ctxt->op_bytes;
4816 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4817 (u64) ctxt->src.val;
4818 break;
4819 default:
4820 goto cannot_emulate;
4821 }
4822
4823 if (rc != X86EMUL_CONTINUE)
4824 goto done;
4825
4826 goto writeback;
4827
4828 cannot_emulate:
4829 return EMULATION_FAILED;
4830 }
4831
4832 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4833 {
4834 invalidate_registers(ctxt);
4835 }
4836
4837 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4838 {
4839 writeback_registers(ctxt);
4840 }
Linux with added FPC-III support