?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / arch / x86 / kvm / svm.c
blob289897326da4790e3f7b3c990e330cbafcc1424e
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23 #include "cpuid.h"
24
25 #include <linux/module.h>
26 #include <linux/mod_devicetable.h>
27 #include <linux/kernel.h>
28 #include <linux/vmalloc.h>
29 #include <linux/highmem.h>
30 #include <linux/sched.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33
34 #include <asm/perf_event.h>
35 #include <asm/tlbflush.h>
36 #include <asm/desc.h>
37 #include <asm/kvm_para.h>
38
39 #include <asm/virtext.h>
40 #include "trace.h"
41
42 #define __ex(x) __kvm_handle_fault_on_reboot(x)
43
44 MODULE_AUTHOR("Qumranet");
45 MODULE_LICENSE("GPL");
46
47 static const struct x86_cpu_id svm_cpu_id[] = {
48 X86_FEATURE_MATCH(X86_FEATURE_SVM),
49 {}
50 };
51 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
52
53 #define IOPM_ALLOC_ORDER 2
54 #define MSRPM_ALLOC_ORDER 1
55
56 #define SEG_TYPE_LDT 2
57 #define SEG_TYPE_BUSY_TSS16 3
58
59 #define SVM_FEATURE_NPT (1 << 0)
60 #define SVM_FEATURE_LBRV (1 << 1)
61 #define SVM_FEATURE_SVML (1 << 2)
62 #define SVM_FEATURE_NRIP (1 << 3)
63 #define SVM_FEATURE_TSC_RATE (1 << 4)
64 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
65 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
66 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
67 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
68
69 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
70 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
71 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
72
73 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
74
75 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
76 #define TSC_RATIO_MIN 0x0000000000000001ULL
77 #define TSC_RATIO_MAX 0x000000ffffffffffULL
78
79 static bool erratum_383_found __read_mostly;
80
81 static const u32 host_save_user_msrs[] = {
82 #ifdef CONFIG_X86_64
83 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
84 MSR_FS_BASE,
85 #endif
86 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
87 };
88
89 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
90
91 struct kvm_vcpu;
92
93 struct nested_state {
94 struct vmcb *hsave;
95 u64 hsave_msr;
96 u64 vm_cr_msr;
97 u64 vmcb;
98
99 /* These are the merged vectors */
100 u32 *msrpm;
101
102 /* gpa pointers to the real vectors */
103 u64 vmcb_msrpm;
104 u64 vmcb_iopm;
105
106 /* A VMEXIT is required but not yet emulated */
107 bool exit_required;
108
109 /* cache for intercepts of the guest */
110 u32 intercept_cr;
111 u32 intercept_dr;
112 u32 intercept_exceptions;
113 u64 intercept;
114
115 /* Nested Paging related state */
116 u64 nested_cr3;
117 };
118
119 #define MSRPM_OFFSETS 16
120 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
121
122 /*
123 * Set osvw_len to higher value when updated Revision Guides
124 * are published and we know what the new status bits are
125 */
126 static uint64_t osvw_len = 4, osvw_status;
127
128 struct vcpu_svm {
129 struct kvm_vcpu vcpu;
130 struct vmcb *vmcb;
131 unsigned long vmcb_pa;
132 struct svm_cpu_data *svm_data;
133 uint64_t asid_generation;
134 uint64_t sysenter_esp;
135 uint64_t sysenter_eip;
136
137 u64 next_rip;
138
139 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
140 struct {
141 u16 fs;
142 u16 gs;
143 u16 ldt;
144 u64 gs_base;
145 } host;
146
147 u32 *msrpm;
148
149 ulong nmi_iret_rip;
150
151 struct nested_state nested;
152
153 bool nmi_singlestep;
154
155 unsigned int3_injected;
156 unsigned long int3_rip;
157 u32 apf_reason;
158
159 u64 tsc_ratio;
160 };
161
162 static DEFINE_PER_CPU(u64, current_tsc_ratio);
163 #define TSC_RATIO_DEFAULT 0x0100000000ULL
164
165 #define MSR_INVALID 0xffffffffU
166
167 static const struct svm_direct_access_msrs {
168 u32 index; /* Index of the MSR */
169 bool always; /* True if intercept is always on */
170 } direct_access_msrs[] = {
171 { .index = MSR_STAR, .always = true },
172 { .index = MSR_IA32_SYSENTER_CS, .always = true },
173 #ifdef CONFIG_X86_64
174 { .index = MSR_GS_BASE, .always = true },
175 { .index = MSR_FS_BASE, .always = true },
176 { .index = MSR_KERNEL_GS_BASE, .always = true },
177 { .index = MSR_LSTAR, .always = true },
178 { .index = MSR_CSTAR, .always = true },
179 { .index = MSR_SYSCALL_MASK, .always = true },
180 #endif
181 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
182 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
183 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
184 { .index = MSR_IA32_LASTINTTOIP, .always = false },
185 { .index = MSR_INVALID, .always = false },
186 };
187
188 /* enable NPT for AMD64 and X86 with PAE */
189 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
190 static bool npt_enabled = true;
191 #else
192 static bool npt_enabled;
193 #endif
194
195 /* allow nested paging (virtualized MMU) for all guests */
196 static int npt = true;
197 module_param(npt, int, S_IRUGO);
198
199 /* allow nested virtualization in KVM/SVM */
200 static int nested = true;
201 module_param(nested, int, S_IRUGO);
202
203 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
204 static void svm_complete_interrupts(struct vcpu_svm *svm);
205
206 static int nested_svm_exit_handled(struct vcpu_svm *svm);
207 static int nested_svm_intercept(struct vcpu_svm *svm);
208 static int nested_svm_vmexit(struct vcpu_svm *svm);
209 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
210 bool has_error_code, u32 error_code);
211 static u64 __scale_tsc(u64 ratio, u64 tsc);
212
213 enum {
214 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
215 pause filter count */
216 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
217 VMCB_ASID, /* ASID */
218 VMCB_INTR, /* int_ctl, int_vector */
219 VMCB_NPT, /* npt_en, nCR3, gPAT */
220 VMCB_CR, /* CR0, CR3, CR4, EFER */
221 VMCB_DR, /* DR6, DR7 */
222 VMCB_DT, /* GDT, IDT */
223 VMCB_SEG, /* CS, DS, SS, ES, CPL */
224 VMCB_CR2, /* CR2 only */
225 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
226 VMCB_DIRTY_MAX,
227 };
228
229 /* TPR and CR2 are always written before VMRUN */
230 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
231
232 static inline void mark_all_dirty(struct vmcb *vmcb)
233 {
234 vmcb->control.clean = 0;
235 }
236
237 static inline void mark_all_clean(struct vmcb *vmcb)
238 {
239 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
240 & ~VMCB_ALWAYS_DIRTY_MASK;
241 }
242
243 static inline void mark_dirty(struct vmcb *vmcb, int bit)
244 {
245 vmcb->control.clean &= ~(1 << bit);
246 }
247
248 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
249 {
250 return container_of(vcpu, struct vcpu_svm, vcpu);
251 }
252
253 static void recalc_intercepts(struct vcpu_svm *svm)
254 {
255 struct vmcb_control_area *c, *h;
256 struct nested_state *g;
257
258 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
259
260 if (!is_guest_mode(&svm->vcpu))
261 return;
262
263 c = &svm->vmcb->control;
264 h = &svm->nested.hsave->control;
265 g = &svm->nested;
266
267 c->intercept_cr = h->intercept_cr | g->intercept_cr;
268 c->intercept_dr = h->intercept_dr | g->intercept_dr;
269 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
270 c->intercept = h->intercept | g->intercept;
271 }
272
273 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
274 {
275 if (is_guest_mode(&svm->vcpu))
276 return svm->nested.hsave;
277 else
278 return svm->vmcb;
279 }
280
281 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
282 {
283 struct vmcb *vmcb = get_host_vmcb(svm);
284
285 vmcb->control.intercept_cr |= (1U << bit);
286
287 recalc_intercepts(svm);
288 }
289
290 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
291 {
292 struct vmcb *vmcb = get_host_vmcb(svm);
293
294 vmcb->control.intercept_cr &= ~(1U << bit);
295
296 recalc_intercepts(svm);
297 }
298
299 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
300 {
301 struct vmcb *vmcb = get_host_vmcb(svm);
302
303 return vmcb->control.intercept_cr & (1U << bit);
304 }
305
306 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
307 {
308 struct vmcb *vmcb = get_host_vmcb(svm);
309
310 vmcb->control.intercept_dr |= (1U << bit);
311
312 recalc_intercepts(svm);
313 }
314
315 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
316 {
317 struct vmcb *vmcb = get_host_vmcb(svm);
318
319 vmcb->control.intercept_dr &= ~(1U << bit);
320
321 recalc_intercepts(svm);
322 }
323
324 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
325 {
326 struct vmcb *vmcb = get_host_vmcb(svm);
327
328 vmcb->control.intercept_exceptions |= (1U << bit);
329
330 recalc_intercepts(svm);
331 }
332
333 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
334 {
335 struct vmcb *vmcb = get_host_vmcb(svm);
336
337 vmcb->control.intercept_exceptions &= ~(1U << bit);
338
339 recalc_intercepts(svm);
340 }
341
342 static inline void set_intercept(struct vcpu_svm *svm, int bit)
343 {
344 struct vmcb *vmcb = get_host_vmcb(svm);
345
346 vmcb->control.intercept |= (1ULL << bit);
347
348 recalc_intercepts(svm);
349 }
350
351 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
352 {
353 struct vmcb *vmcb = get_host_vmcb(svm);
354
355 vmcb->control.intercept &= ~(1ULL << bit);
356
357 recalc_intercepts(svm);
358 }
359
360 static inline void enable_gif(struct vcpu_svm *svm)
361 {
362 svm->vcpu.arch.hflags |= HF_GIF_MASK;
363 }
364
365 static inline void disable_gif(struct vcpu_svm *svm)
366 {
367 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
368 }
369
370 static inline bool gif_set(struct vcpu_svm *svm)
371 {
372 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
373 }
374
375 static unsigned long iopm_base;
376
377 struct kvm_ldttss_desc {
378 u16 limit0;
379 u16 base0;
380 unsigned base1:8, type:5, dpl:2, p:1;
381 unsigned limit1:4, zero0:3, g:1, base2:8;
382 u32 base3;
383 u32 zero1;
384 } __attribute__((packed));
385
386 struct svm_cpu_data {
387 int cpu;
388
389 u64 asid_generation;
390 u32 max_asid;
391 u32 next_asid;
392 struct kvm_ldttss_desc *tss_desc;
393
394 struct page *save_area;
395 };
396
397 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
398
399 struct svm_init_data {
400 int cpu;
401 int r;
402 };
403
404 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
405
406 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
407 #define MSRS_RANGE_SIZE 2048
408 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
409
410 static u32 svm_msrpm_offset(u32 msr)
411 {
412 u32 offset;
413 int i;
414
415 for (i = 0; i < NUM_MSR_MAPS; i++) {
416 if (msr < msrpm_ranges[i] ||
417 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
418 continue;
419
420 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
421 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
422
423 /* Now we have the u8 offset - but need the u32 offset */
424 return offset / 4;
425 }
426
427 /* MSR not in any range */
428 return MSR_INVALID;
429 }
430
431 #define MAX_INST_SIZE 15
432
433 static inline void clgi(void)
434 {
435 asm volatile (__ex(SVM_CLGI));
436 }
437
438 static inline void stgi(void)
439 {
440 asm volatile (__ex(SVM_STGI));
441 }
442
443 static inline void invlpga(unsigned long addr, u32 asid)
444 {
445 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
446 }
447
448 static int get_npt_level(void)
449 {
450 #ifdef CONFIG_X86_64
451 return PT64_ROOT_LEVEL;
452 #else
453 return PT32E_ROOT_LEVEL;
454 #endif
455 }
456
457 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
458 {
459 vcpu->arch.efer = efer;
460 if (!npt_enabled && !(efer & EFER_LMA))
461 efer &= ~EFER_LME;
462
463 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
464 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
465 }
466
467 static int is_external_interrupt(u32 info)
468 {
469 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
470 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
471 }
472
473 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
474 {
475 struct vcpu_svm *svm = to_svm(vcpu);
476 u32 ret = 0;
477
478 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
479 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
480 return ret & mask;
481 }
482
483 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
484 {
485 struct vcpu_svm *svm = to_svm(vcpu);
486
487 if (mask == 0)
488 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
489 else
490 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
491
492 }
493
494 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
495 {
496 struct vcpu_svm *svm = to_svm(vcpu);
497
498 if (svm->vmcb->control.next_rip != 0) {
499 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
500 svm->next_rip = svm->vmcb->control.next_rip;
501 }
502
503 if (!svm->next_rip) {
504 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
505 EMULATE_DONE)
506 printk(KERN_DEBUG "%s: NOP\n", __func__);
507 return;
508 }
509 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
510 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
511 __func__, kvm_rip_read(vcpu), svm->next_rip);
512
513 kvm_rip_write(vcpu, svm->next_rip);
514 svm_set_interrupt_shadow(vcpu, 0);
515 }
516
517 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
518 bool has_error_code, u32 error_code,
519 bool reinject)
520 {
521 struct vcpu_svm *svm = to_svm(vcpu);
522
523 /*
524 * If we are within a nested VM we'd better #VMEXIT and let the guest
525 * handle the exception
526 */
527 if (!reinject &&
528 nested_svm_check_exception(svm, nr, has_error_code, error_code))
529 return;
530
531 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
532 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
533
534 /*
535 * For guest debugging where we have to reinject #BP if some
536 * INT3 is guest-owned:
537 * Emulate nRIP by moving RIP forward. Will fail if injection
538 * raises a fault that is not intercepted. Still better than
539 * failing in all cases.
540 */
541 skip_emulated_instruction(&svm->vcpu);
542 rip = kvm_rip_read(&svm->vcpu);
543 svm->int3_rip = rip + svm->vmcb->save.cs.base;
544 svm->int3_injected = rip - old_rip;
545 }
546
547 svm->vmcb->control.event_inj = nr
548 | SVM_EVTINJ_VALID
549 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
550 | SVM_EVTINJ_TYPE_EXEPT;
551 svm->vmcb->control.event_inj_err = error_code;
552 }
553
554 static void svm_init_erratum_383(void)
555 {
556 u32 low, high;
557 int err;
558 u64 val;
559
560 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
561 return;
562
563 /* Use _safe variants to not break nested virtualization */
564 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
565 if (err)
566 return;
567
568 val |= (1ULL << 47);
569
570 low = lower_32_bits(val);
571 high = upper_32_bits(val);
572
573 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
574
575 erratum_383_found = true;
576 }
577
578 static void svm_init_osvw(struct kvm_vcpu *vcpu)
579 {
580 /*
581 * Guests should see errata 400 and 415 as fixed (assuming that
582 * HLT and IO instructions are intercepted).
583 */
584 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
585 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
586
587 /*
588 * By increasing VCPU's osvw.length to 3 we are telling the guest that
589 * all osvw.status bits inside that length, including bit 0 (which is
590 * reserved for erratum 298), are valid. However, if host processor's
591 * osvw_len is 0 then osvw_status[0] carries no information. We need to
592 * be conservative here and therefore we tell the guest that erratum 298
593 * is present (because we really don't know).
594 */
595 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
596 vcpu->arch.osvw.status |= 1;
597 }
598
599 static int has_svm(void)
600 {
601 const char *msg;
602
603 if (!cpu_has_svm(&msg)) {
604 printk(KERN_INFO "has_svm: %s\n", msg);
605 return 0;
606 }
607
608 return 1;
609 }
610
611 static void svm_hardware_disable(void *garbage)
612 {
613 /* Make sure we clean up behind us */
614 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
615 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
616
617 cpu_svm_disable();
618
619 amd_pmu_disable_virt();
620 }
621
622 static int svm_hardware_enable(void *garbage)
623 {
624
625 struct svm_cpu_data *sd;
626 uint64_t efer;
627 struct desc_ptr gdt_descr;
628 struct desc_struct *gdt;
629 int me = raw_smp_processor_id();
630
631 rdmsrl(MSR_EFER, efer);
632 if (efer & EFER_SVME)
633 return -EBUSY;
634
635 if (!has_svm()) {
636 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
637 return -EINVAL;
638 }
639 sd = per_cpu(svm_data, me);
640 if (!sd) {
641 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
642 return -EINVAL;
643 }
644
645 sd->asid_generation = 1;
646 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
647 sd->next_asid = sd->max_asid + 1;
648
649 native_store_gdt(&gdt_descr);
650 gdt = (struct desc_struct *)gdt_descr.address;
651 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
652
653 wrmsrl(MSR_EFER, efer | EFER_SVME);
654
655 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
656
657 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
658 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
659 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
660 }
661
662
663 /*
664 * Get OSVW bits.
665 *
666 * Note that it is possible to have a system with mixed processor
667 * revisions and therefore different OSVW bits. If bits are not the same
668 * on different processors then choose the worst case (i.e. if erratum
669 * is present on one processor and not on another then assume that the
670 * erratum is present everywhere).
671 */
672 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
673 uint64_t len, status = 0;
674 int err;
675
676 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
677 if (!err)
678 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
679 &err);
680
681 if (err)
682 osvw_status = osvw_len = 0;
683 else {
684 if (len < osvw_len)
685 osvw_len = len;
686 osvw_status |= status;
687 osvw_status &= (1ULL << osvw_len) - 1;
688 }
689 } else
690 osvw_status = osvw_len = 0;
691
692 svm_init_erratum_383();
693
694 amd_pmu_enable_virt();
695
696 return 0;
697 }
698
699 static void svm_cpu_uninit(int cpu)
700 {
701 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
702
703 if (!sd)
704 return;
705
706 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
707 __free_page(sd->save_area);
708 kfree(sd);
709 }
710
711 static int svm_cpu_init(int cpu)
712 {
713 struct svm_cpu_data *sd;
714 int r;
715
716 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
717 if (!sd)
718 return -ENOMEM;
719 sd->cpu = cpu;
720 sd->save_area = alloc_page(GFP_KERNEL);
721 r = -ENOMEM;
722 if (!sd->save_area)
723 goto err_1;
724
725 per_cpu(svm_data, cpu) = sd;
726
727 return 0;
728
729 err_1:
730 kfree(sd);
731 return r;
732
733 }
734
735 static bool valid_msr_intercept(u32 index)
736 {
737 int i;
738
739 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
740 if (direct_access_msrs[i].index == index)
741 return true;
742
743 return false;
744 }
745
746 static void set_msr_interception(u32 *msrpm, unsigned msr,
747 int read, int write)
748 {
749 u8 bit_read, bit_write;
750 unsigned long tmp;
751 u32 offset;
752
753 /*
754 * If this warning triggers extend the direct_access_msrs list at the
755 * beginning of the file
756 */
757 WARN_ON(!valid_msr_intercept(msr));
758
759 offset = svm_msrpm_offset(msr);
760 bit_read = 2 * (msr & 0x0f);
761 bit_write = 2 * (msr & 0x0f) + 1;
762 tmp = msrpm[offset];
763
764 BUG_ON(offset == MSR_INVALID);
765
766 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
767 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
768
769 msrpm[offset] = tmp;
770 }
771
772 static void svm_vcpu_init_msrpm(u32 *msrpm)
773 {
774 int i;
775
776 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
777
778 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
779 if (!direct_access_msrs[i].always)
780 continue;
781
782 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
783 }
784 }
785
786 static void add_msr_offset(u32 offset)
787 {
788 int i;
789
790 for (i = 0; i < MSRPM_OFFSETS; ++i) {
791
792 /* Offset already in list? */
793 if (msrpm_offsets[i] == offset)
794 return;
795
796 /* Slot used by another offset? */
797 if (msrpm_offsets[i] != MSR_INVALID)
798 continue;
799
800 /* Add offset to list */
801 msrpm_offsets[i] = offset;
802
803 return;
804 }
805
806 /*
807 * If this BUG triggers the msrpm_offsets table has an overflow. Just
808 * increase MSRPM_OFFSETS in this case.
809 */
810 BUG();
811 }
812
813 static void init_msrpm_offsets(void)
814 {
815 int i;
816
817 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
818
819 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
820 u32 offset;
821
822 offset = svm_msrpm_offset(direct_access_msrs[i].index);
823 BUG_ON(offset == MSR_INVALID);
824
825 add_msr_offset(offset);
826 }
827 }
828
829 static void svm_enable_lbrv(struct vcpu_svm *svm)
830 {
831 u32 *msrpm = svm->msrpm;
832
833 svm->vmcb->control.lbr_ctl = 1;
834 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
835 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
836 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
837 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
838 }
839
840 static void svm_disable_lbrv(struct vcpu_svm *svm)
841 {
842 u32 *msrpm = svm->msrpm;
843
844 svm->vmcb->control.lbr_ctl = 0;
845 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
846 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
847 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
848 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
849 }
850
851 static __init int svm_hardware_setup(void)
852 {
853 int cpu;
854 struct page *iopm_pages;
855 void *iopm_va;
856 int r;
857
858 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
859
860 if (!iopm_pages)
861 return -ENOMEM;
862
863 iopm_va = page_address(iopm_pages);
864 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
865 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
866
867 init_msrpm_offsets();
868
869 if (boot_cpu_has(X86_FEATURE_NX))
870 kvm_enable_efer_bits(EFER_NX);
871
872 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
873 kvm_enable_efer_bits(EFER_FFXSR);
874
875 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
876 u64 max;
877
878 kvm_has_tsc_control = true;
879
880 /*
881 * Make sure the user can only configure tsc_khz values that
882 * fit into a signed integer.
883 * A min value is not calculated needed because it will always
884 * be 1 on all machines and a value of 0 is used to disable
885 * tsc-scaling for the vcpu.
886 */
887 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
888
889 kvm_max_guest_tsc_khz = max;
890 }
891
892 if (nested) {
893 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
894 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
895 }
896
897 for_each_possible_cpu(cpu) {
898 r = svm_cpu_init(cpu);
899 if (r)
900 goto err;
901 }
902
903 if (!boot_cpu_has(X86_FEATURE_NPT))
904 npt_enabled = false;
905
906 if (npt_enabled && !npt) {
907 printk(KERN_INFO "kvm: Nested Paging disabled\n");
908 npt_enabled = false;
909 }
910
911 if (npt_enabled) {
912 printk(KERN_INFO "kvm: Nested Paging enabled\n");
913 kvm_enable_tdp();
914 } else
915 kvm_disable_tdp();
916
917 return 0;
918
919 err:
920 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
921 iopm_base = 0;
922 return r;
923 }
924
925 static __exit void svm_hardware_unsetup(void)
926 {
927 int cpu;
928
929 for_each_possible_cpu(cpu)
930 svm_cpu_uninit(cpu);
931
932 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
933 iopm_base = 0;
934 }
935
936 static void init_seg(struct vmcb_seg *seg)
937 {
938 seg->selector = 0;
939 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
940 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
941 seg->limit = 0xffff;
942 seg->base = 0;
943 }
944
945 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
946 {
947 seg->selector = 0;
948 seg->attrib = SVM_SELECTOR_P_MASK | type;
949 seg->limit = 0xffff;
950 seg->base = 0;
951 }
952
953 static u64 __scale_tsc(u64 ratio, u64 tsc)
954 {
955 u64 mult, frac, _tsc;
956
957 mult = ratio >> 32;
958 frac = ratio & ((1ULL << 32) - 1);
959
960 _tsc = tsc;
961 _tsc *= mult;
962 _tsc += (tsc >> 32) * frac;
963 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
964
965 return _tsc;
966 }
967
968 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
969 {
970 struct vcpu_svm *svm = to_svm(vcpu);
971 u64 _tsc = tsc;
972
973 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
974 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
975
976 return _tsc;
977 }
978
979 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
980 {
981 struct vcpu_svm *svm = to_svm(vcpu);
982 u64 ratio;
983 u64 khz;
984
985 /* Guest TSC same frequency as host TSC? */
986 if (!scale) {
987 svm->tsc_ratio = TSC_RATIO_DEFAULT;
988 return;
989 }
990
991 /* TSC scaling supported? */
992 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
993 if (user_tsc_khz > tsc_khz) {
994 vcpu->arch.tsc_catchup = 1;
995 vcpu->arch.tsc_always_catchup = 1;
996 } else
997 WARN(1, "user requested TSC rate below hardware speed\n");
998 return;
999 }
1000
1001 khz = user_tsc_khz;
1002
1003 /* TSC scaling required - calculate ratio */
1004 ratio = khz << 32;
1005 do_div(ratio, tsc_khz);
1006
1007 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1008 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1009 user_tsc_khz);
1010 return;
1011 }
1012 svm->tsc_ratio = ratio;
1013 }
1014
1015 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1016 {
1017 struct vcpu_svm *svm = to_svm(vcpu);
1018
1019 return svm->vmcb->control.tsc_offset;
1020 }
1021
1022 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1023 {
1024 struct vcpu_svm *svm = to_svm(vcpu);
1025 u64 g_tsc_offset = 0;
1026
1027 if (is_guest_mode(vcpu)) {
1028 g_tsc_offset = svm->vmcb->control.tsc_offset -
1029 svm->nested.hsave->control.tsc_offset;
1030 svm->nested.hsave->control.tsc_offset = offset;
1031 } else
1032 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1033 svm->vmcb->control.tsc_offset,
1034 offset);
1035
1036 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1037
1038 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1039 }
1040
1041 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1042 {
1043 struct vcpu_svm *svm = to_svm(vcpu);
1044
1045 WARN_ON(adjustment < 0);
1046 if (host)
1047 adjustment = svm_scale_tsc(vcpu, adjustment);
1048
1049 svm->vmcb->control.tsc_offset += adjustment;
1050 if (is_guest_mode(vcpu))
1051 svm->nested.hsave->control.tsc_offset += adjustment;
1052 else
1053 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1054 svm->vmcb->control.tsc_offset - adjustment,
1055 svm->vmcb->control.tsc_offset);
1056
1057 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1058 }
1059
1060 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1061 {
1062 u64 tsc;
1063
1064 tsc = svm_scale_tsc(vcpu, native_read_tsc());
1065
1066 return target_tsc - tsc;
1067 }
1068
1069 static void init_vmcb(struct vcpu_svm *svm)
1070 {
1071 struct vmcb_control_area *control = &svm->vmcb->control;
1072 struct vmcb_save_area *save = &svm->vmcb->save;
1073
1074 svm->vcpu.fpu_active = 1;
1075 svm->vcpu.arch.hflags = 0;
1076
1077 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1078 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1079 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1080 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1081 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1082 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1083 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1084
1085 set_dr_intercept(svm, INTERCEPT_DR0_READ);
1086 set_dr_intercept(svm, INTERCEPT_DR1_READ);
1087 set_dr_intercept(svm, INTERCEPT_DR2_READ);
1088 set_dr_intercept(svm, INTERCEPT_DR3_READ);
1089 set_dr_intercept(svm, INTERCEPT_DR4_READ);
1090 set_dr_intercept(svm, INTERCEPT_DR5_READ);
1091 set_dr_intercept(svm, INTERCEPT_DR6_READ);
1092 set_dr_intercept(svm, INTERCEPT_DR7_READ);
1093
1094 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1095 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1096 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1097 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1098 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1099 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1100 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1101 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
1102
1103 set_exception_intercept(svm, PF_VECTOR);
1104 set_exception_intercept(svm, UD_VECTOR);
1105 set_exception_intercept(svm, MC_VECTOR);
1106 set_exception_intercept(svm, AC_VECTOR);
1107 set_exception_intercept(svm, DB_VECTOR);
1108
1109 set_intercept(svm, INTERCEPT_INTR);
1110 set_intercept(svm, INTERCEPT_NMI);
1111 set_intercept(svm, INTERCEPT_SMI);
1112 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1113 set_intercept(svm, INTERCEPT_RDPMC);
1114 set_intercept(svm, INTERCEPT_CPUID);
1115 set_intercept(svm, INTERCEPT_INVD);
1116 set_intercept(svm, INTERCEPT_HLT);
1117 set_intercept(svm, INTERCEPT_INVLPG);
1118 set_intercept(svm, INTERCEPT_INVLPGA);
1119 set_intercept(svm, INTERCEPT_IOIO_PROT);
1120 set_intercept(svm, INTERCEPT_MSR_PROT);
1121 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1122 set_intercept(svm, INTERCEPT_SHUTDOWN);
1123 set_intercept(svm, INTERCEPT_VMRUN);
1124 set_intercept(svm, INTERCEPT_VMMCALL);
1125 set_intercept(svm, INTERCEPT_VMLOAD);
1126 set_intercept(svm, INTERCEPT_VMSAVE);
1127 set_intercept(svm, INTERCEPT_STGI);
1128 set_intercept(svm, INTERCEPT_CLGI);
1129 set_intercept(svm, INTERCEPT_SKINIT);
1130 set_intercept(svm, INTERCEPT_WBINVD);
1131 set_intercept(svm, INTERCEPT_MONITOR);
1132 set_intercept(svm, INTERCEPT_MWAIT);
1133 set_intercept(svm, INTERCEPT_XSETBV);
1134
1135 control->iopm_base_pa = iopm_base;
1136 control->msrpm_base_pa = __pa(svm->msrpm);
1137 control->int_ctl = V_INTR_MASKING_MASK;
1138
1139 init_seg(&save->es);
1140 init_seg(&save->ss);
1141 init_seg(&save->ds);
1142 init_seg(&save->fs);
1143 init_seg(&save->gs);
1144
1145 save->cs.selector = 0xf000;
1146 save->cs.base = 0xffff0000;
1147 /* Executable/Readable Code Segment */
1148 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1149 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1150 save->cs.limit = 0xffff;
1151
1152 save->gdtr.limit = 0xffff;
1153 save->idtr.limit = 0xffff;
1154
1155 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1156 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1157
1158 svm_set_efer(&svm->vcpu, 0);
1159 save->dr6 = 0xffff0ff0;
1160 kvm_set_rflags(&svm->vcpu, 2);
1161 save->rip = 0x0000fff0;
1162 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1163
1164 /*
1165 * This is the guest-visible cr0 value.
1166 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1167 */
1168 svm->vcpu.arch.cr0 = 0;
1169 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1170
1171 save->cr4 = X86_CR4_PAE;
1172 /* rdx = ?? */
1173
1174 if (npt_enabled) {
1175 /* Setup VMCB for Nested Paging */
1176 control->nested_ctl = 1;
1177 clr_intercept(svm, INTERCEPT_INVLPG);
1178 clr_exception_intercept(svm, PF_VECTOR);
1179 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1180 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1181 save->g_pat = 0x0007040600070406ULL;
1182 save->cr3 = 0;
1183 save->cr4 = 0;
1184 }
1185 svm->asid_generation = 0;
1186
1187 svm->nested.vmcb = 0;
1188 svm->vcpu.arch.hflags = 0;
1189
1190 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1191 control->pause_filter_count = 3000;
1192 set_intercept(svm, INTERCEPT_PAUSE);
1193 }
1194
1195 mark_all_dirty(svm->vmcb);
1196
1197 enable_gif(svm);
1198 }
1199
1200 static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
1201 {
1202 struct vcpu_svm *svm = to_svm(vcpu);
1203 u32 dummy;
1204 u32 eax = 1;
1205
1206 init_vmcb(svm);
1207
1208 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1209 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1210 }
1211
1212 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1213 {
1214 struct vcpu_svm *svm;
1215 struct page *page;
1216 struct page *msrpm_pages;
1217 struct page *hsave_page;
1218 struct page *nested_msrpm_pages;
1219 int err;
1220
1221 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1222 if (!svm) {
1223 err = -ENOMEM;
1224 goto out;
1225 }
1226
1227 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1228
1229 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1230 if (err)
1231 goto free_svm;
1232
1233 err = -ENOMEM;
1234 page = alloc_page(GFP_KERNEL);
1235 if (!page)
1236 goto uninit;
1237
1238 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1239 if (!msrpm_pages)
1240 goto free_page1;
1241
1242 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1243 if (!nested_msrpm_pages)
1244 goto free_page2;
1245
1246 hsave_page = alloc_page(GFP_KERNEL);
1247 if (!hsave_page)
1248 goto free_page3;
1249
1250 svm->nested.hsave = page_address(hsave_page);
1251
1252 svm->msrpm = page_address(msrpm_pages);
1253 svm_vcpu_init_msrpm(svm->msrpm);
1254
1255 svm->nested.msrpm = page_address(nested_msrpm_pages);
1256 svm_vcpu_init_msrpm(svm->nested.msrpm);
1257
1258 svm->vmcb = page_address(page);
1259 clear_page(svm->vmcb);
1260 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1261 svm->asid_generation = 0;
1262 init_vmcb(svm);
1263
1264 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1265 if (kvm_vcpu_is_bsp(&svm->vcpu))
1266 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1267
1268 svm_init_osvw(&svm->vcpu);
1269
1270 return &svm->vcpu;
1271
1272 free_page3:
1273 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1274 free_page2:
1275 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1276 free_page1:
1277 __free_page(page);
1278 uninit:
1279 kvm_vcpu_uninit(&svm->vcpu);
1280 free_svm:
1281 kmem_cache_free(kvm_vcpu_cache, svm);
1282 out:
1283 return ERR_PTR(err);
1284 }
1285
1286 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1287 {
1288 struct vcpu_svm *svm = to_svm(vcpu);
1289
1290 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1291 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1292 __free_page(virt_to_page(svm->nested.hsave));
1293 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1294 kvm_vcpu_uninit(vcpu);
1295 kmem_cache_free(kvm_vcpu_cache, svm);
1296 }
1297
1298 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1299 {
1300 struct vcpu_svm *svm = to_svm(vcpu);
1301 int i;
1302
1303 if (unlikely(cpu != vcpu->cpu)) {
1304 svm->asid_generation = 0;
1305 mark_all_dirty(svm->vmcb);
1306 }
1307
1308 #ifdef CONFIG_X86_64
1309 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1310 #endif
1311 savesegment(fs, svm->host.fs);
1312 savesegment(gs, svm->host.gs);
1313 svm->host.ldt = kvm_read_ldt();
1314
1315 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1316 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1317
1318 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1319 svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1320 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1321 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1322 }
1323 }
1324
1325 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1326 {
1327 struct vcpu_svm *svm = to_svm(vcpu);
1328 int i;
1329
1330 ++vcpu->stat.host_state_reload;
1331 kvm_load_ldt(svm->host.ldt);
1332 #ifdef CONFIG_X86_64
1333 loadsegment(fs, svm->host.fs);
1334 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1335 load_gs_index(svm->host.gs);
1336 #else
1337 #ifdef CONFIG_X86_32_LAZY_GS
1338 loadsegment(gs, svm->host.gs);
1339 #endif
1340 #endif
1341 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1342 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1343 }
1344
1345 static void svm_update_cpl(struct kvm_vcpu *vcpu)
1346 {
1347 struct vcpu_svm *svm = to_svm(vcpu);
1348 int cpl;
1349
1350 if (!is_protmode(vcpu))
1351 cpl = 0;
1352 else if (svm->vmcb->save.rflags & X86_EFLAGS_VM)
1353 cpl = 3;
1354 else
1355 cpl = svm->vmcb->save.cs.selector & 0x3;
1356
1357 svm->vmcb->save.cpl = cpl;
1358 }
1359
1360 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1361 {
1362 return to_svm(vcpu)->vmcb->save.rflags;
1363 }
1364
1365 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1366 {
1367 unsigned long old_rflags = to_svm(vcpu)->vmcb->save.rflags;
1368
1369 to_svm(vcpu)->vmcb->save.rflags = rflags;
1370 if ((old_rflags ^ rflags) & X86_EFLAGS_VM)
1371 svm_update_cpl(vcpu);
1372 }
1373
1374 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1375 {
1376 switch (reg) {
1377 case VCPU_EXREG_PDPTR:
1378 BUG_ON(!npt_enabled);
1379 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1380 break;
1381 default:
1382 BUG();
1383 }
1384 }
1385
1386 static void svm_set_vintr(struct vcpu_svm *svm)
1387 {
1388 set_intercept(svm, INTERCEPT_VINTR);
1389 }
1390
1391 static void svm_clear_vintr(struct vcpu_svm *svm)
1392 {
1393 clr_intercept(svm, INTERCEPT_VINTR);
1394 }
1395
1396 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1397 {
1398 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1399
1400 switch (seg) {
1401 case VCPU_SREG_CS: return &save->cs;
1402 case VCPU_SREG_DS: return &save->ds;
1403 case VCPU_SREG_ES: return &save->es;
1404 case VCPU_SREG_FS: return &save->fs;
1405 case VCPU_SREG_GS: return &save->gs;
1406 case VCPU_SREG_SS: return &save->ss;
1407 case VCPU_SREG_TR: return &save->tr;
1408 case VCPU_SREG_LDTR: return &save->ldtr;
1409 }
1410 BUG();
1411 return NULL;
1412 }
1413
1414 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1415 {
1416 struct vmcb_seg *s = svm_seg(vcpu, seg);
1417
1418 return s->base;
1419 }
1420
1421 static void svm_get_segment(struct kvm_vcpu *vcpu,
1422 struct kvm_segment *var, int seg)
1423 {
1424 struct vmcb_seg *s = svm_seg(vcpu, seg);
1425
1426 var->base = s->base;
1427 var->limit = s->limit;
1428 var->selector = s->selector;
1429 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1430 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1431 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1432 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1433 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1434 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1435 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1436 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1437
1438 /*
1439 * AMD's VMCB does not have an explicit unusable field, so emulate it
1440 * for cross vendor migration purposes by "not present"
1441 */
1442 var->unusable = !var->present || (var->type == 0);
1443
1444 switch (seg) {
1445 case VCPU_SREG_CS:
1446 /*
1447 * SVM always stores 0 for the 'G' bit in the CS selector in
1448 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1449 * Intel's VMENTRY has a check on the 'G' bit.
1450 */
1451 var->g = s->limit > 0xfffff;
1452 break;
1453 case VCPU_SREG_TR:
1454 /*
1455 * Work around a bug where the busy flag in the tr selector
1456 * isn't exposed
1457 */
1458 var->type |= 0x2;
1459 break;
1460 case VCPU_SREG_DS:
1461 case VCPU_SREG_ES:
1462 case VCPU_SREG_FS:
1463 case VCPU_SREG_GS:
1464 /*
1465 * The accessed bit must always be set in the segment
1466 * descriptor cache, although it can be cleared in the
1467 * descriptor, the cached bit always remains at 1. Since
1468 * Intel has a check on this, set it here to support
1469 * cross-vendor migration.
1470 */
1471 if (!var->unusable)
1472 var->type |= 0x1;
1473 break;
1474 case VCPU_SREG_SS:
1475 /*
1476 * On AMD CPUs sometimes the DB bit in the segment
1477 * descriptor is left as 1, although the whole segment has
1478 * been made unusable. Clear it here to pass an Intel VMX
1479 * entry check when cross vendor migrating.
1480 */
1481 if (var->unusable)
1482 var->db = 0;
1483 break;
1484 }
1485 }
1486
1487 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1488 {
1489 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1490
1491 return save->cpl;
1492 }
1493
1494 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1495 {
1496 struct vcpu_svm *svm = to_svm(vcpu);
1497
1498 dt->size = svm->vmcb->save.idtr.limit;
1499 dt->address = svm->vmcb->save.idtr.base;
1500 }
1501
1502 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1503 {
1504 struct vcpu_svm *svm = to_svm(vcpu);
1505
1506 svm->vmcb->save.idtr.limit = dt->size;
1507 svm->vmcb->save.idtr.base = dt->address ;
1508 mark_dirty(svm->vmcb, VMCB_DT);
1509 }
1510
1511 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1512 {
1513 struct vcpu_svm *svm = to_svm(vcpu);
1514
1515 dt->size = svm->vmcb->save.gdtr.limit;
1516 dt->address = svm->vmcb->save.gdtr.base;
1517 }
1518
1519 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1520 {
1521 struct vcpu_svm *svm = to_svm(vcpu);
1522
1523 svm->vmcb->save.gdtr.limit = dt->size;
1524 svm->vmcb->save.gdtr.base = dt->address ;
1525 mark_dirty(svm->vmcb, VMCB_DT);
1526 }
1527
1528 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1529 {
1530 }
1531
1532 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1533 {
1534 }
1535
1536 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1537 {
1538 }
1539
1540 static void update_cr0_intercept(struct vcpu_svm *svm)
1541 {
1542 ulong gcr0 = svm->vcpu.arch.cr0;
1543 u64 *hcr0 = &svm->vmcb->save.cr0;
1544
1545 if (!svm->vcpu.fpu_active)
1546 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1547 else
1548 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1549 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1550
1551 mark_dirty(svm->vmcb, VMCB_CR);
1552
1553 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1554 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1555 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1556 } else {
1557 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1558 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1559 }
1560 }
1561
1562 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1563 {
1564 struct vcpu_svm *svm = to_svm(vcpu);
1565
1566 #ifdef CONFIG_X86_64
1567 if (vcpu->arch.efer & EFER_LME) {
1568 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1569 vcpu->arch.efer |= EFER_LMA;
1570 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1571 }
1572
1573 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1574 vcpu->arch.efer &= ~EFER_LMA;
1575 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1576 }
1577 }
1578 #endif
1579 vcpu->arch.cr0 = cr0;
1580
1581 if (!npt_enabled)
1582 cr0 |= X86_CR0_PG | X86_CR0_WP;
1583
1584 if (!vcpu->fpu_active)
1585 cr0 |= X86_CR0_TS;
1586 /*
1587 * re-enable caching here because the QEMU bios
1588 * does not do it - this results in some delay at
1589 * reboot
1590 */
1591 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1592 svm->vmcb->save.cr0 = cr0;
1593 mark_dirty(svm->vmcb, VMCB_CR);
1594 update_cr0_intercept(svm);
1595 }
1596
1597 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1598 {
1599 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1600 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1601
1602 if (cr4 & X86_CR4_VMXE)
1603 return 1;
1604
1605 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1606 svm_flush_tlb(vcpu);
1607
1608 vcpu->arch.cr4 = cr4;
1609 if (!npt_enabled)
1610 cr4 |= X86_CR4_PAE;
1611 cr4 |= host_cr4_mce;
1612 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1613 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1614 return 0;
1615 }
1616
1617 static void svm_set_segment(struct kvm_vcpu *vcpu,
1618 struct kvm_segment *var, int seg)
1619 {
1620 struct vcpu_svm *svm = to_svm(vcpu);
1621 struct vmcb_seg *s = svm_seg(vcpu, seg);
1622
1623 s->base = var->base;
1624 s->limit = var->limit;
1625 s->selector = var->selector;
1626 if (var->unusable)
1627 s->attrib = 0;
1628 else {
1629 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1630 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1631 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1632 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1633 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1634 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1635 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1636 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1637 }
1638 if (seg == VCPU_SREG_CS)
1639 svm_update_cpl(vcpu);
1640
1641 mark_dirty(svm->vmcb, VMCB_SEG);
1642 }
1643
1644 static void update_bp_intercept(struct kvm_vcpu *vcpu)
1645 {
1646 struct vcpu_svm *svm = to_svm(vcpu);
1647
1648 clr_exception_intercept(svm, BP_VECTOR);
1649
1650 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1651 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1652 set_exception_intercept(svm, BP_VECTOR);
1653 } else
1654 vcpu->guest_debug = 0;
1655 }
1656
1657 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1658 {
1659 if (sd->next_asid > sd->max_asid) {
1660 ++sd->asid_generation;
1661 sd->next_asid = 1;
1662 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1663 }
1664
1665 svm->asid_generation = sd->asid_generation;
1666 svm->vmcb->control.asid = sd->next_asid++;
1667
1668 mark_dirty(svm->vmcb, VMCB_ASID);
1669 }
1670
1671 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1672 {
1673 struct vcpu_svm *svm = to_svm(vcpu);
1674
1675 svm->vmcb->save.dr7 = value;
1676 mark_dirty(svm->vmcb, VMCB_DR);
1677 }
1678
1679 static int pf_interception(struct vcpu_svm *svm)
1680 {
1681 u64 fault_address = svm->vmcb->control.exit_info_2;
1682 u32 error_code;
1683 int r = 1;
1684
1685 switch (svm->apf_reason) {
1686 default:
1687 error_code = svm->vmcb->control.exit_info_1;
1688
1689 trace_kvm_page_fault(fault_address, error_code);
1690 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1691 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1692 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1693 svm->vmcb->control.insn_bytes,
1694 svm->vmcb->control.insn_len);
1695 break;
1696 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1697 svm->apf_reason = 0;
1698 local_irq_disable();
1699 kvm_async_pf_task_wait(fault_address);
1700 local_irq_enable();
1701 break;
1702 case KVM_PV_REASON_PAGE_READY:
1703 svm->apf_reason = 0;
1704 local_irq_disable();
1705 kvm_async_pf_task_wake(fault_address);
1706 local_irq_enable();
1707 break;
1708 }
1709 return r;
1710 }
1711
1712 static int db_interception(struct vcpu_svm *svm)
1713 {
1714 struct kvm_run *kvm_run = svm->vcpu.run;
1715
1716 if (!(svm->vcpu.guest_debug &
1717 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1718 !svm->nmi_singlestep) {
1719 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1720 return 1;
1721 }
1722
1723 if (svm->nmi_singlestep) {
1724 svm->nmi_singlestep = false;
1725 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1726 svm->vmcb->save.rflags &=
1727 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1728 }
1729
1730 if (svm->vcpu.guest_debug &
1731 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1732 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1733 kvm_run->debug.arch.pc =
1734 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1735 kvm_run->debug.arch.exception = DB_VECTOR;
1736 return 0;
1737 }
1738
1739 return 1;
1740 }
1741
1742 static int bp_interception(struct vcpu_svm *svm)
1743 {
1744 struct kvm_run *kvm_run = svm->vcpu.run;
1745
1746 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1747 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1748 kvm_run->debug.arch.exception = BP_VECTOR;
1749 return 0;
1750 }
1751
1752 static int ud_interception(struct vcpu_svm *svm)
1753 {
1754 int er;
1755
1756 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1757 if (er != EMULATE_DONE)
1758 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1759 return 1;
1760 }
1761
1762 static int ac_interception(struct vcpu_svm *svm)
1763 {
1764 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1765 return 1;
1766 }
1767
1768 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1769 {
1770 struct vcpu_svm *svm = to_svm(vcpu);
1771
1772 clr_exception_intercept(svm, NM_VECTOR);
1773
1774 svm->vcpu.fpu_active = 1;
1775 update_cr0_intercept(svm);
1776 }
1777
1778 static int nm_interception(struct vcpu_svm *svm)
1779 {
1780 svm_fpu_activate(&svm->vcpu);
1781 return 1;
1782 }
1783
1784 static bool is_erratum_383(void)
1785 {
1786 int err, i;
1787 u64 value;
1788
1789 if (!erratum_383_found)
1790 return false;
1791
1792 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1793 if (err)
1794 return false;
1795
1796 /* Bit 62 may or may not be set for this mce */
1797 value &= ~(1ULL << 62);
1798
1799 if (value != 0xb600000000010015ULL)
1800 return false;
1801
1802 /* Clear MCi_STATUS registers */
1803 for (i = 0; i < 6; ++i)
1804 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1805
1806 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1807 if (!err) {
1808 u32 low, high;
1809
1810 value &= ~(1ULL << 2);
1811 low = lower_32_bits(value);
1812 high = upper_32_bits(value);
1813
1814 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1815 }
1816
1817 /* Flush tlb to evict multi-match entries */
1818 __flush_tlb_all();
1819
1820 return true;
1821 }
1822
1823 static void svm_handle_mce(struct vcpu_svm *svm)
1824 {
1825 if (is_erratum_383()) {
1826 /*
1827 * Erratum 383 triggered. Guest state is corrupt so kill the
1828 * guest.
1829 */
1830 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1831
1832 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1833
1834 return;
1835 }
1836
1837 /*
1838 * On an #MC intercept the MCE handler is not called automatically in
1839 * the host. So do it by hand here.
1840 */
1841 asm volatile (
1842 "int $0x12\n");
1843 /* not sure if we ever come back to this point */
1844
1845 return;
1846 }
1847
1848 static int mc_interception(struct vcpu_svm *svm)
1849 {
1850 return 1;
1851 }
1852
1853 static int shutdown_interception(struct vcpu_svm *svm)
1854 {
1855 struct kvm_run *kvm_run = svm->vcpu.run;
1856
1857 /*
1858 * VMCB is undefined after a SHUTDOWN intercept
1859 * so reinitialize it.
1860 */
1861 clear_page(svm->vmcb);
1862 init_vmcb(svm);
1863
1864 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1865 return 0;
1866 }
1867
1868 static int io_interception(struct vcpu_svm *svm)
1869 {
1870 struct kvm_vcpu *vcpu = &svm->vcpu;
1871 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1872 int size, in, string;
1873 unsigned port;
1874
1875 ++svm->vcpu.stat.io_exits;
1876 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1877 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1878 if (string || in)
1879 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1880
1881 port = io_info >> 16;
1882 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1883 svm->next_rip = svm->vmcb->control.exit_info_2;
1884 skip_emulated_instruction(&svm->vcpu);
1885
1886 return kvm_fast_pio_out(vcpu, size, port);
1887 }
1888
1889 static int nmi_interception(struct vcpu_svm *svm)
1890 {
1891 return 1;
1892 }
1893
1894 static int intr_interception(struct vcpu_svm *svm)
1895 {
1896 ++svm->vcpu.stat.irq_exits;
1897 return 1;
1898 }
1899
1900 static int nop_on_interception(struct vcpu_svm *svm)
1901 {
1902 return 1;
1903 }
1904
1905 static int halt_interception(struct vcpu_svm *svm)
1906 {
1907 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1908 skip_emulated_instruction(&svm->vcpu);
1909 return kvm_emulate_halt(&svm->vcpu);
1910 }
1911
1912 static int vmmcall_interception(struct vcpu_svm *svm)
1913 {
1914 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1915 skip_emulated_instruction(&svm->vcpu);
1916 kvm_emulate_hypercall(&svm->vcpu);
1917 return 1;
1918 }
1919
1920 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1921 {
1922 struct vcpu_svm *svm = to_svm(vcpu);
1923
1924 return svm->nested.nested_cr3;
1925 }
1926
1927 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1928 {
1929 struct vcpu_svm *svm = to_svm(vcpu);
1930 u64 cr3 = svm->nested.nested_cr3;
1931 u64 pdpte;
1932 int ret;
1933
1934 ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1935 offset_in_page(cr3) + index * 8, 8);
1936 if (ret)
1937 return 0;
1938 return pdpte;
1939 }
1940
1941 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1942 unsigned long root)
1943 {
1944 struct vcpu_svm *svm = to_svm(vcpu);
1945
1946 svm->vmcb->control.nested_cr3 = root;
1947 mark_dirty(svm->vmcb, VMCB_NPT);
1948 svm_flush_tlb(vcpu);
1949 }
1950
1951 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1952 struct x86_exception *fault)
1953 {
1954 struct vcpu_svm *svm = to_svm(vcpu);
1955
1956 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1957 svm->vmcb->control.exit_code_hi = 0;
1958 svm->vmcb->control.exit_info_1 = fault->error_code;
1959 svm->vmcb->control.exit_info_2 = fault->address;
1960
1961 nested_svm_vmexit(svm);
1962 }
1963
1964 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1965 {
1966 int r;
1967
1968 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1969
1970 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1971 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1972 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
1973 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1974 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1975 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1976
1977 return r;
1978 }
1979
1980 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1981 {
1982 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1983 }
1984
1985 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1986 {
1987 if (!(svm->vcpu.arch.efer & EFER_SVME)
1988 || !is_paging(&svm->vcpu)) {
1989 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1990 return 1;
1991 }
1992
1993 if (svm->vmcb->save.cpl) {
1994 kvm_inject_gp(&svm->vcpu, 0);
1995 return 1;
1996 }
1997
1998 return 0;
1999 }
2000
2001 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2002 bool has_error_code, u32 error_code)
2003 {
2004 int vmexit;
2005
2006 if (!is_guest_mode(&svm->vcpu))
2007 return 0;
2008
2009 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2010 svm->vmcb->control.exit_code_hi = 0;
2011 svm->vmcb->control.exit_info_1 = error_code;
2012 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2013
2014 vmexit = nested_svm_intercept(svm);
2015 if (vmexit == NESTED_EXIT_DONE)
2016 svm->nested.exit_required = true;
2017
2018 return vmexit;
2019 }
2020
2021 /* This function returns true if it is save to enable the irq window */
2022 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2023 {
2024 if (!is_guest_mode(&svm->vcpu))
2025 return true;
2026
2027 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2028 return true;
2029
2030 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2031 return false;
2032
2033 /*
2034 * if vmexit was already requested (by intercepted exception
2035 * for instance) do not overwrite it with "external interrupt"
2036 * vmexit.
2037 */
2038 if (svm->nested.exit_required)
2039 return false;
2040
2041 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2042 svm->vmcb->control.exit_info_1 = 0;
2043 svm->vmcb->control.exit_info_2 = 0;
2044
2045 if (svm->nested.intercept & 1ULL) {
2046 /*
2047 * The #vmexit can't be emulated here directly because this
2048 * code path runs with irqs and preemption disabled. A
2049 * #vmexit emulation might sleep. Only signal request for
2050 * the #vmexit here.
2051 */
2052 svm->nested.exit_required = true;
2053 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2054 return false;
2055 }
2056
2057 return true;
2058 }
2059
2060 /* This function returns true if it is save to enable the nmi window */
2061 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2062 {
2063 if (!is_guest_mode(&svm->vcpu))
2064 return true;
2065
2066 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2067 return true;
2068
2069 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2070 svm->nested.exit_required = true;
2071
2072 return false;
2073 }
2074
2075 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2076 {
2077 struct page *page;
2078
2079 might_sleep();
2080
2081 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2082 if (is_error_page(page))
2083 goto error;
2084
2085 *_page = page;
2086
2087 return kmap(page);
2088
2089 error:
2090 kvm_inject_gp(&svm->vcpu, 0);
2091
2092 return NULL;
2093 }
2094
2095 static void nested_svm_unmap(struct page *page)
2096 {
2097 kunmap(page);
2098 kvm_release_page_dirty(page);
2099 }
2100
2101 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2102 {
2103 unsigned port;
2104 u8 val, bit;
2105 u64 gpa;
2106
2107 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2108 return NESTED_EXIT_HOST;
2109
2110 port = svm->vmcb->control.exit_info_1 >> 16;
2111 gpa = svm->nested.vmcb_iopm + (port / 8);
2112 bit = port % 8;
2113 val = 0;
2114
2115 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2116 val &= (1 << bit);
2117
2118 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2119 }
2120
2121 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2122 {
2123 u32 offset, msr, value;
2124 int write, mask;
2125
2126 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2127 return NESTED_EXIT_HOST;
2128
2129 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2130 offset = svm_msrpm_offset(msr);
2131 write = svm->vmcb->control.exit_info_1 & 1;
2132 mask = 1 << ((2 * (msr & 0xf)) + write);
2133
2134 if (offset == MSR_INVALID)
2135 return NESTED_EXIT_DONE;
2136
2137 /* Offset is in 32 bit units but need in 8 bit units */
2138 offset *= 4;
2139
2140 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2141 return NESTED_EXIT_DONE;
2142
2143 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2144 }
2145
2146 static int nested_svm_exit_special(struct vcpu_svm *svm)
2147 {
2148 u32 exit_code = svm->vmcb->control.exit_code;
2149
2150 switch (exit_code) {
2151 case SVM_EXIT_INTR:
2152 case SVM_EXIT_NMI:
2153 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2154 return NESTED_EXIT_HOST;
2155 case SVM_EXIT_NPF:
2156 /* For now we are always handling NPFs when using them */
2157 if (npt_enabled)
2158 return NESTED_EXIT_HOST;
2159 break;
2160 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2161 /* When we're shadowing, trap PFs, but not async PF */
2162 if (!npt_enabled && svm->apf_reason == 0)
2163 return NESTED_EXIT_HOST;
2164 break;
2165 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2166 nm_interception(svm);
2167 break;
2168 default:
2169 break;
2170 }
2171
2172 return NESTED_EXIT_CONTINUE;
2173 }
2174
2175 /*
2176 * If this function returns true, this #vmexit was already handled
2177 */
2178 static int nested_svm_intercept(struct vcpu_svm *svm)
2179 {
2180 u32 exit_code = svm->vmcb->control.exit_code;
2181 int vmexit = NESTED_EXIT_HOST;
2182
2183 switch (exit_code) {
2184 case SVM_EXIT_MSR:
2185 vmexit = nested_svm_exit_handled_msr(svm);
2186 break;
2187 case SVM_EXIT_IOIO:
2188 vmexit = nested_svm_intercept_ioio(svm);
2189 break;
2190 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2191 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2192 if (svm->nested.intercept_cr & bit)
2193 vmexit = NESTED_EXIT_DONE;
2194 break;
2195 }
2196 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2197 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2198 if (svm->nested.intercept_dr & bit)
2199 vmexit = NESTED_EXIT_DONE;
2200 break;
2201 }
2202 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2203 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2204 if (svm->nested.intercept_exceptions & excp_bits)
2205 vmexit = NESTED_EXIT_DONE;
2206 /* async page fault always cause vmexit */
2207 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2208 svm->apf_reason != 0)
2209 vmexit = NESTED_EXIT_DONE;
2210 break;
2211 }
2212 case SVM_EXIT_ERR: {
2213 vmexit = NESTED_EXIT_DONE;
2214 break;
2215 }
2216 default: {
2217 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2218 if (svm->nested.intercept & exit_bits)
2219 vmexit = NESTED_EXIT_DONE;
2220 }
2221 }
2222
2223 return vmexit;
2224 }
2225
2226 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2227 {
2228 int vmexit;
2229
2230 vmexit = nested_svm_intercept(svm);
2231
2232 if (vmexit == NESTED_EXIT_DONE)
2233 nested_svm_vmexit(svm);
2234
2235 return vmexit;
2236 }
2237
2238 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2239 {
2240 struct vmcb_control_area *dst = &dst_vmcb->control;
2241 struct vmcb_control_area *from = &from_vmcb->control;
2242
2243 dst->intercept_cr = from->intercept_cr;
2244 dst->intercept_dr = from->intercept_dr;
2245 dst->intercept_exceptions = from->intercept_exceptions;
2246 dst->intercept = from->intercept;
2247 dst->iopm_base_pa = from->iopm_base_pa;
2248 dst->msrpm_base_pa = from->msrpm_base_pa;
2249 dst->tsc_offset = from->tsc_offset;
2250 dst->asid = from->asid;
2251 dst->tlb_ctl = from->tlb_ctl;
2252 dst->int_ctl = from->int_ctl;
2253 dst->int_vector = from->int_vector;
2254 dst->int_state = from->int_state;
2255 dst->exit_code = from->exit_code;
2256 dst->exit_code_hi = from->exit_code_hi;
2257 dst->exit_info_1 = from->exit_info_1;
2258 dst->exit_info_2 = from->exit_info_2;
2259 dst->exit_int_info = from->exit_int_info;
2260 dst->exit_int_info_err = from->exit_int_info_err;
2261 dst->nested_ctl = from->nested_ctl;
2262 dst->event_inj = from->event_inj;
2263 dst->event_inj_err = from->event_inj_err;
2264 dst->nested_cr3 = from->nested_cr3;
2265 dst->lbr_ctl = from->lbr_ctl;
2266 }
2267
2268 static int nested_svm_vmexit(struct vcpu_svm *svm)
2269 {
2270 struct vmcb *nested_vmcb;
2271 struct vmcb *hsave = svm->nested.hsave;
2272 struct vmcb *vmcb = svm->vmcb;
2273 struct page *page;
2274
2275 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2276 vmcb->control.exit_info_1,
2277 vmcb->control.exit_info_2,
2278 vmcb->control.exit_int_info,
2279 vmcb->control.exit_int_info_err,
2280 KVM_ISA_SVM);
2281
2282 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2283 if (!nested_vmcb)
2284 return 1;
2285
2286 /* Exit Guest-Mode */
2287 leave_guest_mode(&svm->vcpu);
2288 svm->nested.vmcb = 0;
2289
2290 /* Give the current vmcb to the guest */
2291 disable_gif(svm);
2292
2293 nested_vmcb->save.es = vmcb->save.es;
2294 nested_vmcb->save.cs = vmcb->save.cs;
2295 nested_vmcb->save.ss = vmcb->save.ss;
2296 nested_vmcb->save.ds = vmcb->save.ds;
2297 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2298 nested_vmcb->save.idtr = vmcb->save.idtr;
2299 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2300 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2301 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2302 nested_vmcb->save.cr2 = vmcb->save.cr2;
2303 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2304 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2305 nested_vmcb->save.rip = vmcb->save.rip;
2306 nested_vmcb->save.rsp = vmcb->save.rsp;
2307 nested_vmcb->save.rax = vmcb->save.rax;
2308 nested_vmcb->save.dr7 = vmcb->save.dr7;
2309 nested_vmcb->save.dr6 = vmcb->save.dr6;
2310 nested_vmcb->save.cpl = vmcb->save.cpl;
2311
2312 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2313 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2314 nested_vmcb->control.int_state = vmcb->control.int_state;
2315 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2316 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2317 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2318 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2319 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2320 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2321 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2322
2323 /*
2324 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2325 * to make sure that we do not lose injected events. So check event_inj
2326 * here and copy it to exit_int_info if it is valid.
2327 * Exit_int_info and event_inj can't be both valid because the case
2328 * below only happens on a VMRUN instruction intercept which has
2329 * no valid exit_int_info set.
2330 */
2331 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2332 struct vmcb_control_area *nc = &nested_vmcb->control;
2333
2334 nc->exit_int_info = vmcb->control.event_inj;
2335 nc->exit_int_info_err = vmcb->control.event_inj_err;
2336 }
2337
2338 nested_vmcb->control.tlb_ctl = 0;
2339 nested_vmcb->control.event_inj = 0;
2340 nested_vmcb->control.event_inj_err = 0;
2341
2342 /* We always set V_INTR_MASKING and remember the old value in hflags */
2343 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2344 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2345
2346 /* Restore the original control entries */
2347 copy_vmcb_control_area(vmcb, hsave);
2348
2349 kvm_clear_exception_queue(&svm->vcpu);
2350 kvm_clear_interrupt_queue(&svm->vcpu);
2351
2352 svm->nested.nested_cr3 = 0;
2353
2354 /* Restore selected save entries */
2355 svm->vmcb->save.es = hsave->save.es;
2356 svm->vmcb->save.cs = hsave->save.cs;
2357 svm->vmcb->save.ss = hsave->save.ss;
2358 svm->vmcb->save.ds = hsave->save.ds;
2359 svm->vmcb->save.gdtr = hsave->save.gdtr;
2360 svm->vmcb->save.idtr = hsave->save.idtr;
2361 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2362 svm_set_efer(&svm->vcpu, hsave->save.efer);
2363 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2364 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2365 if (npt_enabled) {
2366 svm->vmcb->save.cr3 = hsave->save.cr3;
2367 svm->vcpu.arch.cr3 = hsave->save.cr3;
2368 } else {
2369 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2370 }
2371 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2372 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2373 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2374 svm->vmcb->save.dr7 = 0;
2375 svm->vmcb->save.cpl = 0;
2376 svm->vmcb->control.exit_int_info = 0;
2377
2378 mark_all_dirty(svm->vmcb);
2379
2380 nested_svm_unmap(page);
2381
2382 nested_svm_uninit_mmu_context(&svm->vcpu);
2383 kvm_mmu_reset_context(&svm->vcpu);
2384 kvm_mmu_load(&svm->vcpu);
2385
2386 return 0;
2387 }
2388
2389 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2390 {
2391 /*
2392 * This function merges the msr permission bitmaps of kvm and the
2393 * nested vmcb. It is optimized in that it only merges the parts where
2394 * the kvm msr permission bitmap may contain zero bits
2395 */
2396 int i;
2397
2398 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2399 return true;
2400
2401 for (i = 0; i < MSRPM_OFFSETS; i++) {
2402 u32 value, p;
2403 u64 offset;
2404
2405 if (msrpm_offsets[i] == 0xffffffff)
2406 break;
2407
2408 p = msrpm_offsets[i];
2409 offset = svm->nested.vmcb_msrpm + (p * 4);
2410
2411 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2412 return false;
2413
2414 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2415 }
2416
2417 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2418
2419 return true;
2420 }
2421
2422 static bool nested_vmcb_checks(struct vmcb *vmcb)
2423 {
2424 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2425 return false;
2426
2427 if (vmcb->control.asid == 0)
2428 return false;
2429
2430 if (vmcb->control.nested_ctl && !npt_enabled)
2431 return false;
2432
2433 return true;
2434 }
2435
2436 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2437 {
2438 struct vmcb *nested_vmcb;
2439 struct vmcb *hsave = svm->nested.hsave;
2440 struct vmcb *vmcb = svm->vmcb;
2441 struct page *page;
2442 u64 vmcb_gpa;
2443
2444 vmcb_gpa = svm->vmcb->save.rax;
2445
2446 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2447 if (!nested_vmcb)
2448 return false;
2449
2450 if (!nested_vmcb_checks(nested_vmcb)) {
2451 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2452 nested_vmcb->control.exit_code_hi = 0;
2453 nested_vmcb->control.exit_info_1 = 0;
2454 nested_vmcb->control.exit_info_2 = 0;
2455
2456 nested_svm_unmap(page);
2457
2458 return false;
2459 }
2460
2461 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2462 nested_vmcb->save.rip,
2463 nested_vmcb->control.int_ctl,
2464 nested_vmcb->control.event_inj,
2465 nested_vmcb->control.nested_ctl);
2466
2467 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2468 nested_vmcb->control.intercept_cr >> 16,
2469 nested_vmcb->control.intercept_exceptions,
2470 nested_vmcb->control.intercept);
2471
2472 /* Clear internal status */
2473 kvm_clear_exception_queue(&svm->vcpu);
2474 kvm_clear_interrupt_queue(&svm->vcpu);
2475
2476 /*
2477 * Save the old vmcb, so we don't need to pick what we save, but can
2478 * restore everything when a VMEXIT occurs
2479 */
2480 hsave->save.es = vmcb->save.es;
2481 hsave->save.cs = vmcb->save.cs;
2482 hsave->save.ss = vmcb->save.ss;
2483 hsave->save.ds = vmcb->save.ds;
2484 hsave->save.gdtr = vmcb->save.gdtr;
2485 hsave->save.idtr = vmcb->save.idtr;
2486 hsave->save.efer = svm->vcpu.arch.efer;
2487 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2488 hsave->save.cr4 = svm->vcpu.arch.cr4;
2489 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2490 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2491 hsave->save.rsp = vmcb->save.rsp;
2492 hsave->save.rax = vmcb->save.rax;
2493 if (npt_enabled)
2494 hsave->save.cr3 = vmcb->save.cr3;
2495 else
2496 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2497
2498 copy_vmcb_control_area(hsave, vmcb);
2499
2500 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2501 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2502 else
2503 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2504
2505 if (nested_vmcb->control.nested_ctl) {
2506 kvm_mmu_unload(&svm->vcpu);
2507 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2508 nested_svm_init_mmu_context(&svm->vcpu);
2509 }
2510
2511 /* Load the nested guest state */
2512 svm->vmcb->save.es = nested_vmcb->save.es;
2513 svm->vmcb->save.cs = nested_vmcb->save.cs;
2514 svm->vmcb->save.ss = nested_vmcb->save.ss;
2515 svm->vmcb->save.ds = nested_vmcb->save.ds;
2516 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2517 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2518 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2519 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2520 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2521 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2522 if (npt_enabled) {
2523 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2524 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2525 } else
2526 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2527
2528 /* Guest paging mode is active - reset mmu */
2529 kvm_mmu_reset_context(&svm->vcpu);
2530
2531 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2532 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2533 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2534 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2535
2536 /* In case we don't even reach vcpu_run, the fields are not updated */
2537 svm->vmcb->save.rax = nested_vmcb->save.rax;
2538 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2539 svm->vmcb->save.rip = nested_vmcb->save.rip;
2540 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2541 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2542 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2543
2544 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2545 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2546
2547 /* cache intercepts */
2548 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2549 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2550 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2551 svm->nested.intercept = nested_vmcb->control.intercept;
2552
2553 svm_flush_tlb(&svm->vcpu);
2554 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2555 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2556 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2557 else
2558 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2559
2560 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2561 /* We only want the cr8 intercept bits of the guest */
2562 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2563 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2564 }
2565
2566 /* We don't want to see VMMCALLs from a nested guest */
2567 clr_intercept(svm, INTERCEPT_VMMCALL);
2568
2569 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2570 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2571 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2572 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2573 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2574 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2575
2576 nested_svm_unmap(page);
2577
2578 /* Enter Guest-Mode */
2579 enter_guest_mode(&svm->vcpu);
2580
2581 /*
2582 * Merge guest and host intercepts - must be called with vcpu in
2583 * guest-mode to take affect here
2584 */
2585 recalc_intercepts(svm);
2586
2587 svm->nested.vmcb = vmcb_gpa;
2588
2589 enable_gif(svm);
2590
2591 mark_all_dirty(svm->vmcb);
2592
2593 return true;
2594 }
2595
2596 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2597 {
2598 to_vmcb->save.fs = from_vmcb->save.fs;
2599 to_vmcb->save.gs = from_vmcb->save.gs;
2600 to_vmcb->save.tr = from_vmcb->save.tr;
2601 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2602 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2603 to_vmcb->save.star = from_vmcb->save.star;
2604 to_vmcb->save.lstar = from_vmcb->save.lstar;
2605 to_vmcb->save.cstar = from_vmcb->save.cstar;
2606 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2607 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2608 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2609 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2610 }
2611
2612 static int vmload_interception(struct vcpu_svm *svm)
2613 {
2614 struct vmcb *nested_vmcb;
2615 struct page *page;
2616
2617 if (nested_svm_check_permissions(svm))
2618 return 1;
2619
2620 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2621 if (!nested_vmcb)
2622 return 1;
2623
2624 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2625 skip_emulated_instruction(&svm->vcpu);
2626
2627 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2628 nested_svm_unmap(page);
2629
2630 return 1;
2631 }
2632
2633 static int vmsave_interception(struct vcpu_svm *svm)
2634 {
2635 struct vmcb *nested_vmcb;
2636 struct page *page;
2637
2638 if (nested_svm_check_permissions(svm))
2639 return 1;
2640
2641 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2642 if (!nested_vmcb)
2643 return 1;
2644
2645 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2646 skip_emulated_instruction(&svm->vcpu);
2647
2648 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2649 nested_svm_unmap(page);
2650
2651 return 1;
2652 }
2653
2654 static int vmrun_interception(struct vcpu_svm *svm)
2655 {
2656 if (nested_svm_check_permissions(svm))
2657 return 1;
2658
2659 /* Save rip after vmrun instruction */
2660 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2661
2662 if (!nested_svm_vmrun(svm))
2663 return 1;
2664
2665 if (!nested_svm_vmrun_msrpm(svm))
2666 goto failed;
2667
2668 return 1;
2669
2670 failed:
2671
2672 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2673 svm->vmcb->control.exit_code_hi = 0;
2674 svm->vmcb->control.exit_info_1 = 0;
2675 svm->vmcb->control.exit_info_2 = 0;
2676
2677 nested_svm_vmexit(svm);
2678
2679 return 1;
2680 }
2681
2682 static int stgi_interception(struct vcpu_svm *svm)
2683 {
2684 if (nested_svm_check_permissions(svm))
2685 return 1;
2686
2687 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2688 skip_emulated_instruction(&svm->vcpu);
2689 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2690
2691 enable_gif(svm);
2692
2693 return 1;
2694 }
2695
2696 static int clgi_interception(struct vcpu_svm *svm)
2697 {
2698 if (nested_svm_check_permissions(svm))
2699 return 1;
2700
2701 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2702 skip_emulated_instruction(&svm->vcpu);
2703
2704 disable_gif(svm);
2705
2706 /* After a CLGI no interrupts should come */
2707 svm_clear_vintr(svm);
2708 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2709
2710 mark_dirty(svm->vmcb, VMCB_INTR);
2711
2712 return 1;
2713 }
2714
2715 static int invlpga_interception(struct vcpu_svm *svm)
2716 {
2717 struct kvm_vcpu *vcpu = &svm->vcpu;
2718
2719 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2720 vcpu->arch.regs[VCPU_REGS_RAX]);
2721
2722 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2723 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2724
2725 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2726 skip_emulated_instruction(&svm->vcpu);
2727 return 1;
2728 }
2729
2730 static int skinit_interception(struct vcpu_svm *svm)
2731 {
2732 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2733
2734 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2735 return 1;
2736 }
2737
2738 static int xsetbv_interception(struct vcpu_svm *svm)
2739 {
2740 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2741 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2742
2743 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2744 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2745 skip_emulated_instruction(&svm->vcpu);
2746 }
2747
2748 return 1;
2749 }
2750
2751 static int invalid_op_interception(struct vcpu_svm *svm)
2752 {
2753 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2754 return 1;
2755 }
2756
2757 static int task_switch_interception(struct vcpu_svm *svm)
2758 {
2759 u16 tss_selector;
2760 int reason;
2761 int int_type = svm->vmcb->control.exit_int_info &
2762 SVM_EXITINTINFO_TYPE_MASK;
2763 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2764 uint32_t type =
2765 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2766 uint32_t idt_v =
2767 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2768 bool has_error_code = false;
2769 u32 error_code = 0;
2770
2771 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2772
2773 if (svm->vmcb->control.exit_info_2 &
2774 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2775 reason = TASK_SWITCH_IRET;
2776 else if (svm->vmcb->control.exit_info_2 &
2777 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2778 reason = TASK_SWITCH_JMP;
2779 else if (idt_v)
2780 reason = TASK_SWITCH_GATE;
2781 else
2782 reason = TASK_SWITCH_CALL;
2783
2784 if (reason == TASK_SWITCH_GATE) {
2785 switch (type) {
2786 case SVM_EXITINTINFO_TYPE_NMI:
2787 svm->vcpu.arch.nmi_injected = false;
2788 break;
2789 case SVM_EXITINTINFO_TYPE_EXEPT:
2790 if (svm->vmcb->control.exit_info_2 &
2791 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2792 has_error_code = true;
2793 error_code =
2794 (u32)svm->vmcb->control.exit_info_2;
2795 }
2796 kvm_clear_exception_queue(&svm->vcpu);
2797 break;
2798 case SVM_EXITINTINFO_TYPE_INTR:
2799 kvm_clear_interrupt_queue(&svm->vcpu);
2800 break;
2801 default:
2802 break;
2803 }
2804 }
2805
2806 if (reason != TASK_SWITCH_GATE ||
2807 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2808 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2809 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2810 skip_emulated_instruction(&svm->vcpu);
2811
2812 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2813 int_vec = -1;
2814
2815 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2816 has_error_code, error_code) == EMULATE_FAIL) {
2817 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2818 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2819 svm->vcpu.run->internal.ndata = 0;
2820 return 0;
2821 }
2822 return 1;
2823 }
2824
2825 static int cpuid_interception(struct vcpu_svm *svm)
2826 {
2827 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2828 kvm_emulate_cpuid(&svm->vcpu);
2829 return 1;
2830 }
2831
2832 static int iret_interception(struct vcpu_svm *svm)
2833 {
2834 ++svm->vcpu.stat.nmi_window_exits;
2835 clr_intercept(svm, INTERCEPT_IRET);
2836 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2837 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2838 return 1;
2839 }
2840
2841 static int invlpg_interception(struct vcpu_svm *svm)
2842 {
2843 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2844 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2845
2846 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2847 skip_emulated_instruction(&svm->vcpu);
2848 return 1;
2849 }
2850
2851 static int emulate_on_interception(struct vcpu_svm *svm)
2852 {
2853 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2854 }
2855
2856 static int rdpmc_interception(struct vcpu_svm *svm)
2857 {
2858 int err;
2859
2860 if (!static_cpu_has(X86_FEATURE_NRIPS))
2861 return emulate_on_interception(svm);
2862
2863 err = kvm_rdpmc(&svm->vcpu);
2864 kvm_complete_insn_gp(&svm->vcpu, err);
2865
2866 return 1;
2867 }
2868
2869 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2870 {
2871 unsigned long cr0 = svm->vcpu.arch.cr0;
2872 bool ret = false;
2873 u64 intercept;
2874
2875 intercept = svm->nested.intercept;
2876
2877 if (!is_guest_mode(&svm->vcpu) ||
2878 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2879 return false;
2880
2881 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2882 val &= ~SVM_CR0_SELECTIVE_MASK;
2883
2884 if (cr0 ^ val) {
2885 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2886 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2887 }
2888
2889 return ret;
2890 }
2891
2892 #define CR_VALID (1ULL << 63)
2893
2894 static int cr_interception(struct vcpu_svm *svm)
2895 {
2896 int reg, cr;
2897 unsigned long val;
2898 int err;
2899
2900 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2901 return emulate_on_interception(svm);
2902
2903 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2904 return emulate_on_interception(svm);
2905
2906 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2907 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2908
2909 err = 0;
2910 if (cr >= 16) { /* mov to cr */
2911 cr -= 16;
2912 val = kvm_register_read(&svm->vcpu, reg);
2913 switch (cr) {
2914 case 0:
2915 if (!check_selective_cr0_intercepted(svm, val))
2916 err = kvm_set_cr0(&svm->vcpu, val);
2917 else
2918 return 1;
2919
2920 break;
2921 case 3:
2922 err = kvm_set_cr3(&svm->vcpu, val);
2923 break;
2924 case 4:
2925 err = kvm_set_cr4(&svm->vcpu, val);
2926 break;
2927 case 8:
2928 err = kvm_set_cr8(&svm->vcpu, val);
2929 break;
2930 default:
2931 WARN(1, "unhandled write to CR%d", cr);
2932 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2933 return 1;
2934 }
2935 } else { /* mov from cr */
2936 switch (cr) {
2937 case 0:
2938 val = kvm_read_cr0(&svm->vcpu);
2939 break;
2940 case 2:
2941 val = svm->vcpu.arch.cr2;
2942 break;
2943 case 3:
2944 val = kvm_read_cr3(&svm->vcpu);
2945 break;
2946 case 4:
2947 val = kvm_read_cr4(&svm->vcpu);
2948 break;
2949 case 8:
2950 val = kvm_get_cr8(&svm->vcpu);
2951 break;
2952 default:
2953 WARN(1, "unhandled read from CR%d", cr);
2954 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2955 return 1;
2956 }
2957 kvm_register_write(&svm->vcpu, reg, val);
2958 }
2959 kvm_complete_insn_gp(&svm->vcpu, err);
2960
2961 return 1;
2962 }
2963
2964 static int dr_interception(struct vcpu_svm *svm)
2965 {
2966 int reg, dr;
2967 unsigned long val;
2968 int err;
2969
2970 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2971 return emulate_on_interception(svm);
2972
2973 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2974 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2975
2976 if (dr >= 16) { /* mov to DRn */
2977 val = kvm_register_read(&svm->vcpu, reg);
2978 kvm_set_dr(&svm->vcpu, dr - 16, val);
2979 } else {
2980 err = kvm_get_dr(&svm->vcpu, dr, &val);
2981 if (!err)
2982 kvm_register_write(&svm->vcpu, reg, val);
2983 }
2984
2985 skip_emulated_instruction(&svm->vcpu);
2986
2987 return 1;
2988 }
2989
2990 static int cr8_write_interception(struct vcpu_svm *svm)
2991 {
2992 struct kvm_run *kvm_run = svm->vcpu.run;
2993 int r;
2994
2995 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2996 /* instruction emulation calls kvm_set_cr8() */
2997 r = cr_interception(svm);
2998 if (irqchip_in_kernel(svm->vcpu.kvm))
2999 return r;
3000 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3001 return r;
3002 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3003 return 0;
3004 }
3005
3006 u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3007 {
3008 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3009 return vmcb->control.tsc_offset +
3010 svm_scale_tsc(vcpu, host_tsc);
3011 }
3012
3013 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
3014 {
3015 struct vcpu_svm *svm = to_svm(vcpu);
3016
3017 switch (ecx) {
3018 case MSR_IA32_TSC: {
3019 *data = svm->vmcb->control.tsc_offset +
3020 svm_scale_tsc(vcpu, native_read_tsc());
3021
3022 break;
3023 }
3024 case MSR_STAR:
3025 *data = svm->vmcb->save.star;
3026 break;
3027 #ifdef CONFIG_X86_64
3028 case MSR_LSTAR:
3029 *data = svm->vmcb->save.lstar;
3030 break;
3031 case MSR_CSTAR:
3032 *data = svm->vmcb->save.cstar;
3033 break;
3034 case MSR_KERNEL_GS_BASE:
3035 *data = svm->vmcb->save.kernel_gs_base;
3036 break;
3037 case MSR_SYSCALL_MASK:
3038 *data = svm->vmcb->save.sfmask;
3039 break;
3040 #endif
3041 case MSR_IA32_SYSENTER_CS:
3042 *data = svm->vmcb->save.sysenter_cs;
3043 break;
3044 case MSR_IA32_SYSENTER_EIP:
3045 *data = svm->sysenter_eip;
3046 break;
3047 case MSR_IA32_SYSENTER_ESP:
3048 *data = svm->sysenter_esp;
3049 break;
3050 /*
3051 * Nobody will change the following 5 values in the VMCB so we can
3052 * safely return them on rdmsr. They will always be 0 until LBRV is
3053 * implemented.
3054 */
3055 case MSR_IA32_DEBUGCTLMSR:
3056 *data = svm->vmcb->save.dbgctl;
3057 break;
3058 case MSR_IA32_LASTBRANCHFROMIP:
3059 *data = svm->vmcb->save.br_from;
3060 break;
3061 case MSR_IA32_LASTBRANCHTOIP:
3062 *data = svm->vmcb->save.br_to;
3063 break;
3064 case MSR_IA32_LASTINTFROMIP:
3065 *data = svm->vmcb->save.last_excp_from;
3066 break;
3067 case MSR_IA32_LASTINTTOIP:
3068 *data = svm->vmcb->save.last_excp_to;
3069 break;
3070 case MSR_VM_HSAVE_PA:
3071 *data = svm->nested.hsave_msr;
3072 break;
3073 case MSR_VM_CR:
3074 *data = svm->nested.vm_cr_msr;
3075 break;
3076 case MSR_IA32_UCODE_REV:
3077 *data = 0x01000065;
3078 break;
3079 default:
3080 return kvm_get_msr_common(vcpu, ecx, data);
3081 }
3082 return 0;
3083 }
3084
3085 static int rdmsr_interception(struct vcpu_svm *svm)
3086 {
3087 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3088 u64 data;
3089
3090 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3091 trace_kvm_msr_read_ex(ecx);
3092 kvm_inject_gp(&svm->vcpu, 0);
3093 } else {
3094 trace_kvm_msr_read(ecx, data);
3095
3096 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3097 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3098 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3099 skip_emulated_instruction(&svm->vcpu);
3100 }
3101 return 1;
3102 }
3103
3104 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3105 {
3106 struct vcpu_svm *svm = to_svm(vcpu);
3107 int svm_dis, chg_mask;
3108
3109 if (data & ~SVM_VM_CR_VALID_MASK)
3110 return 1;
3111
3112 chg_mask = SVM_VM_CR_VALID_MASK;
3113
3114 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3115 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3116
3117 svm->nested.vm_cr_msr &= ~chg_mask;
3118 svm->nested.vm_cr_msr |= (data & chg_mask);
3119
3120 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3121
3122 /* check for svm_disable while efer.svme is set */
3123 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3124 return 1;
3125
3126 return 0;
3127 }
3128
3129 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3130 {
3131 struct vcpu_svm *svm = to_svm(vcpu);
3132
3133 u32 ecx = msr->index;
3134 u64 data = msr->data;
3135 switch (ecx) {
3136 case MSR_IA32_TSC:
3137 kvm_write_tsc(vcpu, msr);
3138 break;
3139 case MSR_STAR:
3140 svm->vmcb->save.star = data;
3141 break;
3142 #ifdef CONFIG_X86_64
3143 case MSR_LSTAR:
3144 svm->vmcb->save.lstar = data;
3145 break;
3146 case MSR_CSTAR:
3147 svm->vmcb->save.cstar = data;
3148 break;
3149 case MSR_KERNEL_GS_BASE:
3150 svm->vmcb->save.kernel_gs_base = data;
3151 break;
3152 case MSR_SYSCALL_MASK:
3153 svm->vmcb->save.sfmask = data;
3154 break;
3155 #endif
3156 case MSR_IA32_SYSENTER_CS:
3157 svm->vmcb->save.sysenter_cs = data;
3158 break;
3159 case MSR_IA32_SYSENTER_EIP:
3160 svm->sysenter_eip = data;
3161 svm->vmcb->save.sysenter_eip = data;
3162 break;
3163 case MSR_IA32_SYSENTER_ESP:
3164 svm->sysenter_esp = data;
3165 svm->vmcb->save.sysenter_esp = data;
3166 break;
3167 case MSR_IA32_DEBUGCTLMSR:
3168 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3169 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3170 __func__, data);
3171 break;
3172 }
3173 if (data & DEBUGCTL_RESERVED_BITS)
3174 return 1;
3175
3176 svm->vmcb->save.dbgctl = data;
3177 mark_dirty(svm->vmcb, VMCB_LBR);
3178 if (data & (1ULL<<0))
3179 svm_enable_lbrv(svm);
3180 else
3181 svm_disable_lbrv(svm);
3182 break;
3183 case MSR_VM_HSAVE_PA:
3184 svm->nested.hsave_msr = data;
3185 break;
3186 case MSR_VM_CR:
3187 return svm_set_vm_cr(vcpu, data);
3188 case MSR_VM_IGNNE:
3189 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3190 break;
3191 default:
3192 return kvm_set_msr_common(vcpu, msr);
3193 }
3194 return 0;
3195 }
3196
3197 static int wrmsr_interception(struct vcpu_svm *svm)
3198 {
3199 struct msr_data msr;
3200 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3201 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3202 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3203
3204 msr.data = data;
3205 msr.index = ecx;
3206 msr.host_initiated = false;
3207
3208 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3209 if (kvm_set_msr(&svm->vcpu, &msr)) {
3210 trace_kvm_msr_write_ex(ecx, data);
3211 kvm_inject_gp(&svm->vcpu, 0);
3212 } else {
3213 trace_kvm_msr_write(ecx, data);
3214 skip_emulated_instruction(&svm->vcpu);
3215 }
3216 return 1;
3217 }
3218
3219 static int msr_interception(struct vcpu_svm *svm)
3220 {
3221 if (svm->vmcb->control.exit_info_1)
3222 return wrmsr_interception(svm);
3223 else
3224 return rdmsr_interception(svm);
3225 }
3226
3227 static int interrupt_window_interception(struct vcpu_svm *svm)
3228 {
3229 struct kvm_run *kvm_run = svm->vcpu.run;
3230
3231 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3232 svm_clear_vintr(svm);
3233 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3234 mark_dirty(svm->vmcb, VMCB_INTR);
3235 ++svm->vcpu.stat.irq_window_exits;
3236 /*
3237 * If the user space waits to inject interrupts, exit as soon as
3238 * possible
3239 */
3240 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3241 kvm_run->request_interrupt_window &&
3242 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3243 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3244 return 0;
3245 }
3246
3247 return 1;
3248 }
3249
3250 static int pause_interception(struct vcpu_svm *svm)
3251 {
3252 kvm_vcpu_on_spin(&(svm->vcpu));
3253 return 1;
3254 }
3255
3256 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3257 [SVM_EXIT_READ_CR0] = cr_interception,
3258 [SVM_EXIT_READ_CR3] = cr_interception,
3259 [SVM_EXIT_READ_CR4] = cr_interception,
3260 [SVM_EXIT_READ_CR8] = cr_interception,
3261 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
3262 [SVM_EXIT_WRITE_CR0] = cr_interception,
3263 [SVM_EXIT_WRITE_CR3] = cr_interception,
3264 [SVM_EXIT_WRITE_CR4] = cr_interception,
3265 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3266 [SVM_EXIT_READ_DR0] = dr_interception,
3267 [SVM_EXIT_READ_DR1] = dr_interception,
3268 [SVM_EXIT_READ_DR2] = dr_interception,
3269 [SVM_EXIT_READ_DR3] = dr_interception,
3270 [SVM_EXIT_READ_DR4] = dr_interception,
3271 [SVM_EXIT_READ_DR5] = dr_interception,
3272 [SVM_EXIT_READ_DR6] = dr_interception,
3273 [SVM_EXIT_READ_DR7] = dr_interception,
3274 [SVM_EXIT_WRITE_DR0] = dr_interception,
3275 [SVM_EXIT_WRITE_DR1] = dr_interception,
3276 [SVM_EXIT_WRITE_DR2] = dr_interception,
3277 [SVM_EXIT_WRITE_DR3] = dr_interception,
3278 [SVM_EXIT_WRITE_DR4] = dr_interception,
3279 [SVM_EXIT_WRITE_DR5] = dr_interception,
3280 [SVM_EXIT_WRITE_DR6] = dr_interception,
3281 [SVM_EXIT_WRITE_DR7] = dr_interception,
3282 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3283 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3284 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3285 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3286 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3287 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3288 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
3289 [SVM_EXIT_INTR] = intr_interception,
3290 [SVM_EXIT_NMI] = nmi_interception,
3291 [SVM_EXIT_SMI] = nop_on_interception,
3292 [SVM_EXIT_INIT] = nop_on_interception,
3293 [SVM_EXIT_VINTR] = interrupt_window_interception,
3294 [SVM_EXIT_RDPMC] = rdpmc_interception,
3295 [SVM_EXIT_CPUID] = cpuid_interception,
3296 [SVM_EXIT_IRET] = iret_interception,
3297 [SVM_EXIT_INVD] = emulate_on_interception,
3298 [SVM_EXIT_PAUSE] = pause_interception,
3299 [SVM_EXIT_HLT] = halt_interception,
3300 [SVM_EXIT_INVLPG] = invlpg_interception,
3301 [SVM_EXIT_INVLPGA] = invlpga_interception,
3302 [SVM_EXIT_IOIO] = io_interception,
3303 [SVM_EXIT_MSR] = msr_interception,
3304 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3305 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3306 [SVM_EXIT_VMRUN] = vmrun_interception,
3307 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3308 [SVM_EXIT_VMLOAD] = vmload_interception,
3309 [SVM_EXIT_VMSAVE] = vmsave_interception,
3310 [SVM_EXIT_STGI] = stgi_interception,
3311 [SVM_EXIT_CLGI] = clgi_interception,
3312 [SVM_EXIT_SKINIT] = skinit_interception,
3313 [SVM_EXIT_WBINVD] = emulate_on_interception,
3314 [SVM_EXIT_MONITOR] = invalid_op_interception,
3315 [SVM_EXIT_MWAIT] = invalid_op_interception,
3316 [SVM_EXIT_XSETBV] = xsetbv_interception,
3317 [SVM_EXIT_NPF] = pf_interception,
3318 };
3319
3320 static void dump_vmcb(struct kvm_vcpu *vcpu)
3321 {
3322 struct vcpu_svm *svm = to_svm(vcpu);
3323 struct vmcb_control_area *control = &svm->vmcb->control;
3324 struct vmcb_save_area *save = &svm->vmcb->save;
3325
3326 pr_err("VMCB Control Area:\n");
3327 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3328 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3329 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3330 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3331 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3332 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3333 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3334 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3335 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3336 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3337 pr_err("%-20s%d\n", "asid:", control->asid);
3338 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3339 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3340 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3341 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3342 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3343 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3344 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3345 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3346 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3347 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3348 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3349 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3350 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3351 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3352 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3353 pr_err("VMCB State Save Area:\n");
3354 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3355 "es:",
3356 save->es.selector, save->es.attrib,
3357 save->es.limit, save->es.base);
3358 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3359 "cs:",
3360 save->cs.selector, save->cs.attrib,
3361 save->cs.limit, save->cs.base);
3362 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3363 "ss:",
3364 save->ss.selector, save->ss.attrib,
3365 save->ss.limit, save->ss.base);
3366 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3367 "ds:",
3368 save->ds.selector, save->ds.attrib,
3369 save->ds.limit, save->ds.base);
3370 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3371 "fs:",
3372 save->fs.selector, save->fs.attrib,
3373 save->fs.limit, save->fs.base);
3374 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3375 "gs:",
3376 save->gs.selector, save->gs.attrib,
3377 save->gs.limit, save->gs.base);
3378 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3379 "gdtr:",
3380 save->gdtr.selector, save->gdtr.attrib,
3381 save->gdtr.limit, save->gdtr.base);
3382 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3383 "ldtr:",
3384 save->ldtr.selector, save->ldtr.attrib,
3385 save->ldtr.limit, save->ldtr.base);
3386 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3387 "idtr:",
3388 save->idtr.selector, save->idtr.attrib,
3389 save->idtr.limit, save->idtr.base);
3390 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3391 "tr:",
3392 save->tr.selector, save->tr.attrib,
3393 save->tr.limit, save->tr.base);
3394 pr_err("cpl: %d efer: %016llx\n",
3395 save->cpl, save->efer);
3396 pr_err("%-15s %016llx %-13s %016llx\n",
3397 "cr0:", save->cr0, "cr2:", save->cr2);
3398 pr_err("%-15s %016llx %-13s %016llx\n",
3399 "cr3:", save->cr3, "cr4:", save->cr4);
3400 pr_err("%-15s %016llx %-13s %016llx\n",
3401 "dr6:", save->dr6, "dr7:", save->dr7);
3402 pr_err("%-15s %016llx %-13s %016llx\n",
3403 "rip:", save->rip, "rflags:", save->rflags);
3404 pr_err("%-15s %016llx %-13s %016llx\n",
3405 "rsp:", save->rsp, "rax:", save->rax);
3406 pr_err("%-15s %016llx %-13s %016llx\n",
3407 "star:", save->star, "lstar:", save->lstar);
3408 pr_err("%-15s %016llx %-13s %016llx\n",
3409 "cstar:", save->cstar, "sfmask:", save->sfmask);
3410 pr_err("%-15s %016llx %-13s %016llx\n",
3411 "kernel_gs_base:", save->kernel_gs_base,
3412 "sysenter_cs:", save->sysenter_cs);
3413 pr_err("%-15s %016llx %-13s %016llx\n",
3414 "sysenter_esp:", save->sysenter_esp,
3415 "sysenter_eip:", save->sysenter_eip);
3416 pr_err("%-15s %016llx %-13s %016llx\n",
3417 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3418 pr_err("%-15s %016llx %-13s %016llx\n",
3419 "br_from:", save->br_from, "br_to:", save->br_to);
3420 pr_err("%-15s %016llx %-13s %016llx\n",
3421 "excp_from:", save->last_excp_from,
3422 "excp_to:", save->last_excp_to);
3423 }
3424
3425 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3426 {
3427 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3428
3429 *info1 = control->exit_info_1;
3430 *info2 = control->exit_info_2;
3431 }
3432
3433 static int handle_exit(struct kvm_vcpu *vcpu)
3434 {
3435 struct vcpu_svm *svm = to_svm(vcpu);
3436 struct kvm_run *kvm_run = vcpu->run;
3437 u32 exit_code = svm->vmcb->control.exit_code;
3438
3439 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3440 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3441 if (npt_enabled)
3442 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3443
3444 if (unlikely(svm->nested.exit_required)) {
3445 nested_svm_vmexit(svm);
3446 svm->nested.exit_required = false;
3447
3448 return 1;
3449 }
3450
3451 if (is_guest_mode(vcpu)) {
3452 int vmexit;
3453
3454 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3455 svm->vmcb->control.exit_info_1,
3456 svm->vmcb->control.exit_info_2,
3457 svm->vmcb->control.exit_int_info,
3458 svm->vmcb->control.exit_int_info_err,
3459 KVM_ISA_SVM);
3460
3461 vmexit = nested_svm_exit_special(svm);
3462
3463 if (vmexit == NESTED_EXIT_CONTINUE)
3464 vmexit = nested_svm_exit_handled(svm);
3465
3466 if (vmexit == NESTED_EXIT_DONE)
3467 return 1;
3468 }
3469
3470 svm_complete_interrupts(svm);
3471
3472 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3473 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3474 kvm_run->fail_entry.hardware_entry_failure_reason
3475 = svm->vmcb->control.exit_code;
3476 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3477 dump_vmcb(vcpu);
3478 return 0;
3479 }
3480
3481 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3482 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3483 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3484 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3485 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3486 "exit_code 0x%x\n",
3487 __func__, svm->vmcb->control.exit_int_info,
3488 exit_code);
3489
3490 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3491 || !svm_exit_handlers[exit_code]) {
3492 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_code);
3493 kvm_queue_exception(vcpu, UD_VECTOR);
3494 return 1;
3495 }
3496
3497 return svm_exit_handlers[exit_code](svm);
3498 }
3499
3500 static void reload_tss(struct kvm_vcpu *vcpu)
3501 {
3502 int cpu = raw_smp_processor_id();
3503
3504 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3505 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3506 load_TR_desc();
3507 }
3508
3509 static void pre_svm_run(struct vcpu_svm *svm)
3510 {
3511 int cpu = raw_smp_processor_id();
3512
3513 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3514
3515 /* FIXME: handle wraparound of asid_generation */
3516 if (svm->asid_generation != sd->asid_generation)
3517 new_asid(svm, sd);
3518 }
3519
3520 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3521 {
3522 struct vcpu_svm *svm = to_svm(vcpu);
3523
3524 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3525 vcpu->arch.hflags |= HF_NMI_MASK;
3526 set_intercept(svm, INTERCEPT_IRET);
3527 ++vcpu->stat.nmi_injections;
3528 }
3529
3530 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3531 {
3532 struct vmcb_control_area *control;
3533
3534 control = &svm->vmcb->control;
3535 control->int_vector = irq;
3536 control->int_ctl &= ~V_INTR_PRIO_MASK;
3537 control->int_ctl |= V_IRQ_MASK |
3538 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3539 mark_dirty(svm->vmcb, VMCB_INTR);
3540 }
3541
3542 static void svm_set_irq(struct kvm_vcpu *vcpu)
3543 {
3544 struct vcpu_svm *svm = to_svm(vcpu);
3545
3546 BUG_ON(!(gif_set(svm)));
3547
3548 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3549 ++vcpu->stat.irq_injections;
3550
3551 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3552 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3553 }
3554
3555 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3556 {
3557 struct vcpu_svm *svm = to_svm(vcpu);
3558
3559 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3560 return;
3561
3562 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3563
3564 if (irr == -1)
3565 return;
3566
3567 if (tpr >= irr)
3568 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3569 }
3570
3571 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3572 {
3573 return;
3574 }
3575
3576 static int svm_vm_has_apicv(struct kvm *kvm)
3577 {
3578 return 0;
3579 }
3580
3581 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3582 {
3583 return;
3584 }
3585
3586 static void svm_hwapic_isr_update(struct kvm *kvm, int isr)
3587 {
3588 return;
3589 }
3590
3591 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3592 {
3593 return;
3594 }
3595
3596 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3597 {
3598 struct vcpu_svm *svm = to_svm(vcpu);
3599 struct vmcb *vmcb = svm->vmcb;
3600 int ret;
3601 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3602 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3603 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3604
3605 return ret;
3606 }
3607
3608 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3609 {
3610 struct vcpu_svm *svm = to_svm(vcpu);
3611
3612 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3613 }
3614
3615 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3616 {
3617 struct vcpu_svm *svm = to_svm(vcpu);
3618
3619 if (masked) {
3620 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3621 set_intercept(svm, INTERCEPT_IRET);
3622 } else {
3623 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3624 clr_intercept(svm, INTERCEPT_IRET);
3625 }
3626 }
3627
3628 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3629 {
3630 struct vcpu_svm *svm = to_svm(vcpu);
3631 struct vmcb *vmcb = svm->vmcb;
3632 int ret;
3633
3634 if (!gif_set(svm) ||
3635 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3636 return 0;
3637
3638 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3639
3640 if (is_guest_mode(vcpu))
3641 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3642
3643 return ret;
3644 }
3645
3646 static int enable_irq_window(struct kvm_vcpu *vcpu)
3647 {
3648 struct vcpu_svm *svm = to_svm(vcpu);
3649
3650 /*
3651 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3652 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3653 * get that intercept, this function will be called again though and
3654 * we'll get the vintr intercept.
3655 */
3656 if (gif_set(svm) && nested_svm_intr(svm)) {
3657 svm_set_vintr(svm);
3658 svm_inject_irq(svm, 0x0);
3659 }
3660 return 0;
3661 }
3662
3663 static int enable_nmi_window(struct kvm_vcpu *vcpu)
3664 {
3665 struct vcpu_svm *svm = to_svm(vcpu);
3666
3667 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3668 == HF_NMI_MASK)
3669 return 0; /* IRET will cause a vm exit */
3670
3671 /*
3672 * Something prevents NMI from been injected. Single step over possible
3673 * problem (IRET or exception injection or interrupt shadow)
3674 */
3675 svm->nmi_singlestep = true;
3676 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3677 return 0;
3678 }
3679
3680 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3681 {
3682 return 0;
3683 }
3684
3685 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3686 {
3687 struct vcpu_svm *svm = to_svm(vcpu);
3688
3689 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3690 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3691 else
3692 svm->asid_generation--;
3693 }
3694
3695 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3696 {
3697 }
3698
3699 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3700 {
3701 struct vcpu_svm *svm = to_svm(vcpu);
3702
3703 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3704 return;
3705
3706 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3707 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3708 kvm_set_cr8(vcpu, cr8);
3709 }
3710 }
3711
3712 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3713 {
3714 struct vcpu_svm *svm = to_svm(vcpu);
3715 u64 cr8;
3716
3717 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3718 return;
3719
3720 cr8 = kvm_get_cr8(vcpu);
3721 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3722 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3723 }
3724
3725 static void svm_complete_interrupts(struct vcpu_svm *svm)
3726 {
3727 u8 vector;
3728 int type;
3729 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3730 unsigned int3_injected = svm->int3_injected;
3731
3732 svm->int3_injected = 0;
3733
3734 /*
3735 * If we've made progress since setting HF_IRET_MASK, we've
3736 * executed an IRET and can allow NMI injection.
3737 */
3738 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3739 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3740 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3741 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3742 }
3743
3744 svm->vcpu.arch.nmi_injected = false;
3745 kvm_clear_exception_queue(&svm->vcpu);
3746 kvm_clear_interrupt_queue(&svm->vcpu);
3747
3748 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3749 return;
3750
3751 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3752
3753 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3754 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3755
3756 switch (type) {
3757 case SVM_EXITINTINFO_TYPE_NMI:
3758 svm->vcpu.arch.nmi_injected = true;
3759 break;
3760 case SVM_EXITINTINFO_TYPE_EXEPT:
3761 /*
3762 * In case of software exceptions, do not reinject the vector,
3763 * but re-execute the instruction instead. Rewind RIP first
3764 * if we emulated INT3 before.
3765 */
3766 if (kvm_exception_is_soft(vector)) {
3767 if (vector == BP_VECTOR && int3_injected &&
3768 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3769 kvm_rip_write(&svm->vcpu,
3770 kvm_rip_read(&svm->vcpu) -
3771 int3_injected);
3772 break;
3773 }
3774 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3775 u32 err = svm->vmcb->control.exit_int_info_err;
3776 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3777
3778 } else
3779 kvm_requeue_exception(&svm->vcpu, vector);
3780 break;
3781 case SVM_EXITINTINFO_TYPE_INTR:
3782 kvm_queue_interrupt(&svm->vcpu, vector, false);
3783 break;
3784 default:
3785 break;
3786 }
3787 }
3788
3789 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3790 {
3791 struct vcpu_svm *svm = to_svm(vcpu);
3792 struct vmcb_control_area *control = &svm->vmcb->control;
3793
3794 control->exit_int_info = control->event_inj;
3795 control->exit_int_info_err = control->event_inj_err;
3796 control->event_inj = 0;
3797 svm_complete_interrupts(svm);
3798 }
3799
3800 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3801 {
3802 struct vcpu_svm *svm = to_svm(vcpu);
3803
3804 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3805 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3806 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3807
3808 /*
3809 * A vmexit emulation is required before the vcpu can be executed
3810 * again.
3811 */
3812 if (unlikely(svm->nested.exit_required))
3813 return;
3814
3815 pre_svm_run(svm);
3816
3817 sync_lapic_to_cr8(vcpu);
3818
3819 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3820
3821 clgi();
3822
3823 local_irq_enable();
3824
3825 asm volatile (
3826 "push %%" _ASM_BP "; \n\t"
3827 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3828 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3829 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3830 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3831 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3832 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3833 #ifdef CONFIG_X86_64
3834 "mov %c[r8](%[svm]), %%r8 \n\t"
3835 "mov %c[r9](%[svm]), %%r9 \n\t"
3836 "mov %c[r10](%[svm]), %%r10 \n\t"
3837 "mov %c[r11](%[svm]), %%r11 \n\t"
3838 "mov %c[r12](%[svm]), %%r12 \n\t"
3839 "mov %c[r13](%[svm]), %%r13 \n\t"
3840 "mov %c[r14](%[svm]), %%r14 \n\t"
3841 "mov %c[r15](%[svm]), %%r15 \n\t"
3842 #endif
3843
3844 /* Enter guest mode */
3845 "push %%" _ASM_AX " \n\t"
3846 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3847 __ex(SVM_VMLOAD) "\n\t"
3848 __ex(SVM_VMRUN) "\n\t"
3849 __ex(SVM_VMSAVE) "\n\t"
3850 "pop %%" _ASM_AX " \n\t"
3851
3852 /* Save guest registers, load host registers */
3853 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3854 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3855 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3856 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3857 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3858 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3859 #ifdef CONFIG_X86_64
3860 "mov %%r8, %c[r8](%[svm]) \n\t"
3861 "mov %%r9, %c[r9](%[svm]) \n\t"
3862 "mov %%r10, %c[r10](%[svm]) \n\t"
3863 "mov %%r11, %c[r11](%[svm]) \n\t"
3864 "mov %%r12, %c[r12](%[svm]) \n\t"
3865 "mov %%r13, %c[r13](%[svm]) \n\t"
3866 "mov %%r14, %c[r14](%[svm]) \n\t"
3867 "mov %%r15, %c[r15](%[svm]) \n\t"
3868 #endif
3869 "pop %%" _ASM_BP
3870 :
3871 : [svm]"a"(svm),
3872 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3873 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3874 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3875 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3876 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3877 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3878 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3879 #ifdef CONFIG_X86_64
3880 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3881 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3882 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3883 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3884 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3885 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3886 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3887 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3888 #endif
3889 : "cc", "memory"
3890 #ifdef CONFIG_X86_64
3891 , "rbx", "rcx", "rdx", "rsi", "rdi"
3892 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3893 #else
3894 , "ebx", "ecx", "edx", "esi", "edi"
3895 #endif
3896 );
3897
3898 #ifdef CONFIG_X86_64
3899 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3900 #else
3901 loadsegment(fs, svm->host.fs);
3902 #ifndef CONFIG_X86_32_LAZY_GS
3903 loadsegment(gs, svm->host.gs);
3904 #endif
3905 #endif
3906
3907 reload_tss(vcpu);
3908
3909 local_irq_disable();
3910
3911 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3912 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3913 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3914 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3915
3916 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3917
3918 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3919 kvm_before_handle_nmi(&svm->vcpu);
3920
3921 stgi();
3922
3923 /* Any pending NMI will happen here */
3924
3925 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3926 kvm_after_handle_nmi(&svm->vcpu);
3927
3928 sync_cr8_to_lapic(vcpu);
3929
3930 svm->next_rip = 0;
3931
3932 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3933
3934 /* if exit due to PF check for async PF */
3935 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3936 svm->apf_reason = kvm_read_and_reset_pf_reason();
3937
3938 if (npt_enabled) {
3939 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3940 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3941 }
3942
3943 /*
3944 * We need to handle MC intercepts here before the vcpu has a chance to
3945 * change the physical cpu
3946 */
3947 if (unlikely(svm->vmcb->control.exit_code ==
3948 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3949 svm_handle_mce(svm);
3950
3951 mark_all_clean(svm->vmcb);
3952 }
3953
3954 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3955 {
3956 struct vcpu_svm *svm = to_svm(vcpu);
3957
3958 svm->vmcb->save.cr3 = root;
3959 mark_dirty(svm->vmcb, VMCB_CR);
3960 svm_flush_tlb(vcpu);
3961 }
3962
3963 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3964 {
3965 struct vcpu_svm *svm = to_svm(vcpu);
3966
3967 svm->vmcb->control.nested_cr3 = root;
3968 mark_dirty(svm->vmcb, VMCB_NPT);
3969
3970 /* Also sync guest cr3 here in case we live migrate */
3971 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3972 mark_dirty(svm->vmcb, VMCB_CR);
3973
3974 svm_flush_tlb(vcpu);
3975 }
3976
3977 static int is_disabled(void)
3978 {
3979 u64 vm_cr;
3980
3981 rdmsrl(MSR_VM_CR, vm_cr);
3982 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3983 return 1;
3984
3985 return 0;
3986 }
3987
3988 static void
3989 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3990 {
3991 /*
3992 * Patch in the VMMCALL instruction:
3993 */
3994 hypercall[0] = 0x0f;
3995 hypercall[1] = 0x01;
3996 hypercall[2] = 0xd9;
3997 }
3998
3999 static void svm_check_processor_compat(void *rtn)
4000 {
4001 *(int *)rtn = 0;
4002 }
4003
4004 static bool svm_cpu_has_accelerated_tpr(void)
4005 {
4006 return false;
4007 }
4008
4009 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4010 {
4011 return 0;
4012 }
4013
4014 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4015 {
4016 }
4017
4018 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4019 {
4020 switch (func) {
4021 case 0x80000001:
4022 if (nested)
4023 entry->ecx |= (1 << 2); /* Set SVM bit */
4024 break;
4025 case 0x8000000A:
4026 entry->eax = 1; /* SVM revision 1 */
4027 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4028 ASID emulation to nested SVM */
4029 entry->ecx = 0; /* Reserved */
4030 entry->edx = 0; /* Per default do not support any
4031 additional features */
4032
4033 /* Support next_rip if host supports it */
4034 if (boot_cpu_has(X86_FEATURE_NRIPS))
4035 entry->edx |= SVM_FEATURE_NRIP;
4036
4037 /* Support NPT for the guest if enabled */
4038 if (npt_enabled)
4039 entry->edx |= SVM_FEATURE_NPT;
4040
4041 break;
4042 }
4043 }
4044
4045 static int svm_get_lpage_level(void)
4046 {
4047 return PT_PDPE_LEVEL;
4048 }
4049
4050 static bool svm_rdtscp_supported(void)
4051 {
4052 return false;
4053 }
4054
4055 static bool svm_invpcid_supported(void)
4056 {
4057 return false;
4058 }
4059
4060 static bool svm_has_wbinvd_exit(void)
4061 {
4062 return true;
4063 }
4064
4065 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4066 {
4067 struct vcpu_svm *svm = to_svm(vcpu);
4068
4069 set_exception_intercept(svm, NM_VECTOR);
4070 update_cr0_intercept(svm);
4071 }
4072
4073 #define PRE_EX(exit) { .exit_code = (exit), \
4074 .stage = X86_ICPT_PRE_EXCEPT, }
4075 #define POST_EX(exit) { .exit_code = (exit), \
4076 .stage = X86_ICPT_POST_EXCEPT, }
4077 #define POST_MEM(exit) { .exit_code = (exit), \
4078 .stage = X86_ICPT_POST_MEMACCESS, }
4079
4080 static const struct __x86_intercept {
4081 u32 exit_code;
4082 enum x86_intercept_stage stage;
4083 } x86_intercept_map[] = {
4084 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4085 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4086 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4087 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4088 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4089 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4090 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4091 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4092 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4093 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4094 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4095 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4096 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4097 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4098 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4099 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4100 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4101 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4102 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4103 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4104 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4105 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4106 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4107 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4108 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4109 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4110 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4111 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4112 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4113 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4114 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4115 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4116 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4117 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4118 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4119 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4120 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4121 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4122 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4123 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4124 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4125 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4126 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4127 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4128 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4129 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4130 };
4131
4132 #undef PRE_EX
4133 #undef POST_EX
4134 #undef POST_MEM
4135
4136 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4137 struct x86_instruction_info *info,
4138 enum x86_intercept_stage stage)
4139 {
4140 struct vcpu_svm *svm = to_svm(vcpu);
4141 int vmexit, ret = X86EMUL_CONTINUE;
4142 struct __x86_intercept icpt_info;
4143 struct vmcb *vmcb = svm->vmcb;
4144
4145 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4146 goto out;
4147
4148 icpt_info = x86_intercept_map[info->intercept];
4149
4150 if (stage != icpt_info.stage)
4151 goto out;
4152
4153 switch (icpt_info.exit_code) {
4154 case SVM_EXIT_READ_CR0:
4155 if (info->intercept == x86_intercept_cr_read)
4156 icpt_info.exit_code += info->modrm_reg;
4157 break;
4158 case SVM_EXIT_WRITE_CR0: {
4159 unsigned long cr0, val;
4160 u64 intercept;
4161
4162 if (info->intercept == x86_intercept_cr_write)
4163 icpt_info.exit_code += info->modrm_reg;
4164
4165 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4166 break;
4167
4168 intercept = svm->nested.intercept;
4169
4170 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4171 break;
4172
4173 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4174 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4175
4176 if (info->intercept == x86_intercept_lmsw) {
4177 cr0 &= 0xfUL;
4178 val &= 0xfUL;
4179 /* lmsw can't clear PE - catch this here */
4180 if (cr0 & X86_CR0_PE)
4181 val |= X86_CR0_PE;
4182 }
4183
4184 if (cr0 ^ val)
4185 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4186
4187 break;
4188 }
4189 case SVM_EXIT_READ_DR0:
4190 case SVM_EXIT_WRITE_DR0:
4191 icpt_info.exit_code += info->modrm_reg;
4192 break;
4193 case SVM_EXIT_MSR:
4194 if (info->intercept == x86_intercept_wrmsr)
4195 vmcb->control.exit_info_1 = 1;
4196 else
4197 vmcb->control.exit_info_1 = 0;
4198 break;
4199 case SVM_EXIT_PAUSE:
4200 /*
4201 * We get this for NOP only, but pause
4202 * is rep not, check this here
4203 */
4204 if (info->rep_prefix != REPE_PREFIX)
4205 goto out;
4206 case SVM_EXIT_IOIO: {
4207 u64 exit_info;
4208 u32 bytes;
4209
4210 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4211
4212 if (info->intercept == x86_intercept_in ||
4213 info->intercept == x86_intercept_ins) {
4214 exit_info |= SVM_IOIO_TYPE_MASK;
4215 bytes = info->src_bytes;
4216 } else {
4217 bytes = info->dst_bytes;
4218 }
4219
4220 if (info->intercept == x86_intercept_outs ||
4221 info->intercept == x86_intercept_ins)
4222 exit_info |= SVM_IOIO_STR_MASK;
4223
4224 if (info->rep_prefix)
4225 exit_info |= SVM_IOIO_REP_MASK;
4226
4227 bytes = min(bytes, 4u);
4228
4229 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4230
4231 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4232
4233 vmcb->control.exit_info_1 = exit_info;
4234 vmcb->control.exit_info_2 = info->next_rip;
4235
4236 break;
4237 }
4238 default:
4239 break;
4240 }
4241
4242 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4243 if (static_cpu_has(X86_FEATURE_NRIPS))
4244 vmcb->control.next_rip = info->next_rip;
4245 vmcb->control.exit_code = icpt_info.exit_code;
4246 vmexit = nested_svm_exit_handled(svm);
4247
4248 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4249 : X86EMUL_CONTINUE;
4250
4251 out:
4252 return ret;
4253 }
4254
4255 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4256 {
4257 local_irq_enable();
4258 }
4259
4260 static struct kvm_x86_ops svm_x86_ops = {
4261 .cpu_has_kvm_support = has_svm,
4262 .disabled_by_bios = is_disabled,
4263 .hardware_setup = svm_hardware_setup,
4264 .hardware_unsetup = svm_hardware_unsetup,
4265 .check_processor_compatibility = svm_check_processor_compat,
4266 .hardware_enable = svm_hardware_enable,
4267 .hardware_disable = svm_hardware_disable,
4268 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4269
4270 .vcpu_create = svm_create_vcpu,
4271 .vcpu_free = svm_free_vcpu,
4272 .vcpu_reset = svm_vcpu_reset,
4273
4274 .prepare_guest_switch = svm_prepare_guest_switch,
4275 .vcpu_load = svm_vcpu_load,
4276 .vcpu_put = svm_vcpu_put,
4277
4278 .update_db_bp_intercept = update_bp_intercept,
4279 .get_msr = svm_get_msr,
4280 .set_msr = svm_set_msr,
4281 .get_segment_base = svm_get_segment_base,
4282 .get_segment = svm_get_segment,
4283 .set_segment = svm_set_segment,
4284 .get_cpl = svm_get_cpl,
4285 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4286 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4287 .decache_cr3 = svm_decache_cr3,
4288 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4289 .set_cr0 = svm_set_cr0,
4290 .set_cr3 = svm_set_cr3,
4291 .set_cr4 = svm_set_cr4,
4292 .set_efer = svm_set_efer,
4293 .get_idt = svm_get_idt,
4294 .set_idt = svm_set_idt,
4295 .get_gdt = svm_get_gdt,
4296 .set_gdt = svm_set_gdt,
4297 .set_dr7 = svm_set_dr7,
4298 .cache_reg = svm_cache_reg,
4299 .get_rflags = svm_get_rflags,
4300 .set_rflags = svm_set_rflags,
4301 .fpu_activate = svm_fpu_activate,
4302 .fpu_deactivate = svm_fpu_deactivate,
4303
4304 .tlb_flush = svm_flush_tlb,
4305
4306 .run = svm_vcpu_run,
4307 .handle_exit = handle_exit,
4308 .skip_emulated_instruction = skip_emulated_instruction,
4309 .set_interrupt_shadow = svm_set_interrupt_shadow,
4310 .get_interrupt_shadow = svm_get_interrupt_shadow,
4311 .patch_hypercall = svm_patch_hypercall,
4312 .set_irq = svm_set_irq,
4313 .set_nmi = svm_inject_nmi,
4314 .queue_exception = svm_queue_exception,
4315 .cancel_injection = svm_cancel_injection,
4316 .interrupt_allowed = svm_interrupt_allowed,
4317 .nmi_allowed = svm_nmi_allowed,
4318 .get_nmi_mask = svm_get_nmi_mask,
4319 .set_nmi_mask = svm_set_nmi_mask,
4320 .enable_nmi_window = enable_nmi_window,
4321 .enable_irq_window = enable_irq_window,
4322 .update_cr8_intercept = update_cr8_intercept,
4323 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4324 .vm_has_apicv = svm_vm_has_apicv,
4325 .load_eoi_exitmap = svm_load_eoi_exitmap,
4326 .hwapic_isr_update = svm_hwapic_isr_update,
4327 .sync_pir_to_irr = svm_sync_pir_to_irr,
4328
4329 .set_tss_addr = svm_set_tss_addr,
4330 .get_tdp_level = get_npt_level,
4331 .get_mt_mask = svm_get_mt_mask,
4332
4333 .get_exit_info = svm_get_exit_info,
4334
4335 .get_lpage_level = svm_get_lpage_level,
4336
4337 .cpuid_update = svm_cpuid_update,
4338
4339 .rdtscp_supported = svm_rdtscp_supported,
4340 .invpcid_supported = svm_invpcid_supported,
4341
4342 .set_supported_cpuid = svm_set_supported_cpuid,
4343
4344 .has_wbinvd_exit = svm_has_wbinvd_exit,
4345
4346 .set_tsc_khz = svm_set_tsc_khz,
4347 .read_tsc_offset = svm_read_tsc_offset,
4348 .write_tsc_offset = svm_write_tsc_offset,
4349 .adjust_tsc_offset = svm_adjust_tsc_offset,
4350 .compute_tsc_offset = svm_compute_tsc_offset,
4351 .read_l1_tsc = svm_read_l1_tsc,
4352
4353 .set_tdp_cr3 = set_tdp_cr3,
4354
4355 .check_intercept = svm_check_intercept,
4356 .handle_external_intr = svm_handle_external_intr,
4357 };
4358
4359 static int __init svm_init(void)
4360 {
4361 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4362 __alignof__(struct vcpu_svm), THIS_MODULE);
4363 }
4364
4365 static void __exit svm_exit(void)
4366 {
4367 kvm_exit();
4368 }
4369
4370 module_init(svm_init)
4371 module_exit(svm_exit)
Linux with added FPC-III support