?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / dma / imx-sdma.c
blobfc43603cf0bbeca883aa260d880c86898b49e793
1 /*
2 * drivers/dma/imx-sdma.c
3 *
4 * This file contains a driver for the Freescale Smart DMA engine
5 *
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 *
8 * Based on code from Freescale:
9 *
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
11 *
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
15 *
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
18 */
19
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/types.h>
23 #include <linux/bitops.h>
24 #include <linux/mm.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/semaphore.h>
30 #include <linux/spinlock.h>
31 #include <linux/device.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/firmware.h>
34 #include <linux/slab.h>
35 #include <linux/platform_device.h>
36 #include <linux/dmaengine.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39 #include <linux/of_dma.h>
40
41 #include <asm/irq.h>
42 #include <linux/platform_data/dma-imx-sdma.h>
43 #include <linux/platform_data/dma-imx.h>
44
45 #include "dmaengine.h"
46
47 /* SDMA registers */
48 #define SDMA_H_C0PTR 0x000
49 #define SDMA_H_INTR 0x004
50 #define SDMA_H_STATSTOP 0x008
51 #define SDMA_H_START 0x00c
52 #define SDMA_H_EVTOVR 0x010
53 #define SDMA_H_DSPOVR 0x014
54 #define SDMA_H_HOSTOVR 0x018
55 #define SDMA_H_EVTPEND 0x01c
56 #define SDMA_H_DSPENBL 0x020
57 #define SDMA_H_RESET 0x024
58 #define SDMA_H_EVTERR 0x028
59 #define SDMA_H_INTRMSK 0x02c
60 #define SDMA_H_PSW 0x030
61 #define SDMA_H_EVTERRDBG 0x034
62 #define SDMA_H_CONFIG 0x038
63 #define SDMA_ONCE_ENB 0x040
64 #define SDMA_ONCE_DATA 0x044
65 #define SDMA_ONCE_INSTR 0x048
66 #define SDMA_ONCE_STAT 0x04c
67 #define SDMA_ONCE_CMD 0x050
68 #define SDMA_EVT_MIRROR 0x054
69 #define SDMA_ILLINSTADDR 0x058
70 #define SDMA_CHN0ADDR 0x05c
71 #define SDMA_ONCE_RTB 0x060
72 #define SDMA_XTRIG_CONF1 0x070
73 #define SDMA_XTRIG_CONF2 0x074
74 #define SDMA_CHNENBL0_IMX35 0x200
75 #define SDMA_CHNENBL0_IMX31 0x080
76 #define SDMA_CHNPRI_0 0x100
77
78 /*
79 * Buffer descriptor status values.
80 */
81 #define BD_DONE 0x01
82 #define BD_WRAP 0x02
83 #define BD_CONT 0x04
84 #define BD_INTR 0x08
85 #define BD_RROR 0x10
86 #define BD_LAST 0x20
87 #define BD_EXTD 0x80
88
89 /*
90 * Data Node descriptor status values.
91 */
92 #define DND_END_OF_FRAME 0x80
93 #define DND_END_OF_XFER 0x40
94 #define DND_DONE 0x20
95 #define DND_UNUSED 0x01
96
97 /*
98 * IPCV2 descriptor status values.
99 */
100 #define BD_IPCV2_END_OF_FRAME 0x40
101
102 #define IPCV2_MAX_NODES 50
103 /*
104 * Error bit set in the CCB status field by the SDMA,
105 * in setbd routine, in case of a transfer error
106 */
107 #define DATA_ERROR 0x10000000
108
109 /*
110 * Buffer descriptor commands.
111 */
112 #define C0_ADDR 0x01
113 #define C0_LOAD 0x02
114 #define C0_DUMP 0x03
115 #define C0_SETCTX 0x07
116 #define C0_GETCTX 0x03
117 #define C0_SETDM 0x01
118 #define C0_SETPM 0x04
119 #define C0_GETDM 0x02
120 #define C0_GETPM 0x08
121 /*
122 * Change endianness indicator in the BD command field
123 */
124 #define CHANGE_ENDIANNESS 0x80
125
126 /*
127 * Mode/Count of data node descriptors - IPCv2
128 */
129 struct sdma_mode_count {
130 u32 count : 16; /* size of the buffer pointed by this BD */
131 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
132 u32 command : 8; /* command mostlky used for channel 0 */
133 };
134
135 /*
136 * Buffer descriptor
137 */
138 struct sdma_buffer_descriptor {
139 struct sdma_mode_count mode;
140 u32 buffer_addr; /* address of the buffer described */
141 u32 ext_buffer_addr; /* extended buffer address */
142 } __attribute__ ((packed));
143
144 /**
145 * struct sdma_channel_control - Channel control Block
146 *
147 * @current_bd_ptr current buffer descriptor processed
148 * @base_bd_ptr first element of buffer descriptor array
149 * @unused padding. The SDMA engine expects an array of 128 byte
150 * control blocks
151 */
152 struct sdma_channel_control {
153 u32 current_bd_ptr;
154 u32 base_bd_ptr;
155 u32 unused[2];
156 } __attribute__ ((packed));
157
158 /**
159 * struct sdma_state_registers - SDMA context for a channel
160 *
161 * @pc: program counter
162 * @t: test bit: status of arithmetic & test instruction
163 * @rpc: return program counter
164 * @sf: source fault while loading data
165 * @spc: loop start program counter
166 * @df: destination fault while storing data
167 * @epc: loop end program counter
168 * @lm: loop mode
169 */
170 struct sdma_state_registers {
171 u32 pc :14;
172 u32 unused1: 1;
173 u32 t : 1;
174 u32 rpc :14;
175 u32 unused0: 1;
176 u32 sf : 1;
177 u32 spc :14;
178 u32 unused2: 1;
179 u32 df : 1;
180 u32 epc :14;
181 u32 lm : 2;
182 } __attribute__ ((packed));
183
184 /**
185 * struct sdma_context_data - sdma context specific to a channel
186 *
187 * @channel_state: channel state bits
188 * @gReg: general registers
189 * @mda: burst dma destination address register
190 * @msa: burst dma source address register
191 * @ms: burst dma status register
192 * @md: burst dma data register
193 * @pda: peripheral dma destination address register
194 * @psa: peripheral dma source address register
195 * @ps: peripheral dma status register
196 * @pd: peripheral dma data register
197 * @ca: CRC polynomial register
198 * @cs: CRC accumulator register
199 * @dda: dedicated core destination address register
200 * @dsa: dedicated core source address register
201 * @ds: dedicated core status register
202 * @dd: dedicated core data register
203 */
204 struct sdma_context_data {
205 struct sdma_state_registers channel_state;
206 u32 gReg[8];
207 u32 mda;
208 u32 msa;
209 u32 ms;
210 u32 md;
211 u32 pda;
212 u32 psa;
213 u32 ps;
214 u32 pd;
215 u32 ca;
216 u32 cs;
217 u32 dda;
218 u32 dsa;
219 u32 ds;
220 u32 dd;
221 u32 scratch0;
222 u32 scratch1;
223 u32 scratch2;
224 u32 scratch3;
225 u32 scratch4;
226 u32 scratch5;
227 u32 scratch6;
228 u32 scratch7;
229 } __attribute__ ((packed));
230
231 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
232
233 struct sdma_engine;
234
235 /**
236 * struct sdma_channel - housekeeping for a SDMA channel
237 *
238 * @sdma pointer to the SDMA engine for this channel
239 * @channel the channel number, matches dmaengine chan_id + 1
240 * @direction transfer type. Needed for setting SDMA script
241 * @peripheral_type Peripheral type. Needed for setting SDMA script
242 * @event_id0 aka dma request line
243 * @event_id1 for channels that use 2 events
244 * @word_size peripheral access size
245 * @buf_tail ID of the buffer that was processed
246 * @num_bd max NUM_BD. number of descriptors currently handling
247 */
248 struct sdma_channel {
249 struct sdma_engine *sdma;
250 unsigned int channel;
251 enum dma_transfer_direction direction;
252 enum sdma_peripheral_type peripheral_type;
253 unsigned int event_id0;
254 unsigned int event_id1;
255 enum dma_slave_buswidth word_size;
256 unsigned int buf_tail;
257 unsigned int num_bd;
258 struct sdma_buffer_descriptor *bd;
259 dma_addr_t bd_phys;
260 unsigned int pc_from_device, pc_to_device;
261 unsigned long flags;
262 dma_addr_t per_address;
263 unsigned long event_mask[2];
264 unsigned long watermark_level;
265 u32 shp_addr, per_addr;
266 struct dma_chan chan;
267 spinlock_t lock;
268 struct dma_async_tx_descriptor desc;
269 enum dma_status status;
270 unsigned int chn_count;
271 unsigned int chn_real_count;
272 struct tasklet_struct tasklet;
273 };
274
275 #define IMX_DMA_SG_LOOP BIT(0)
276
277 #define MAX_DMA_CHANNELS 32
278 #define MXC_SDMA_DEFAULT_PRIORITY 1
279 #define MXC_SDMA_MIN_PRIORITY 1
280 #define MXC_SDMA_MAX_PRIORITY 7
281
282 #define SDMA_FIRMWARE_MAGIC 0x414d4453
283
284 /**
285 * struct sdma_firmware_header - Layout of the firmware image
286 *
287 * @magic "SDMA"
288 * @version_major increased whenever layout of struct sdma_script_start_addrs
289 * changes.
290 * @version_minor firmware minor version (for binary compatible changes)
291 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
292 * @num_script_addrs Number of script addresses in this image
293 * @ram_code_start offset of SDMA ram image in this firmware image
294 * @ram_code_size size of SDMA ram image
295 * @script_addrs Stores the start address of the SDMA scripts
296 * (in SDMA memory space)
297 */
298 struct sdma_firmware_header {
299 u32 magic;
300 u32 version_major;
301 u32 version_minor;
302 u32 script_addrs_start;
303 u32 num_script_addrs;
304 u32 ram_code_start;
305 u32 ram_code_size;
306 };
307
308 struct sdma_driver_data {
309 int chnenbl0;
310 int num_events;
311 struct sdma_script_start_addrs *script_addrs;
312 };
313
314 struct sdma_engine {
315 struct device *dev;
316 struct device_dma_parameters dma_parms;
317 struct sdma_channel channel[MAX_DMA_CHANNELS];
318 struct sdma_channel_control *channel_control;
319 void __iomem *regs;
320 struct sdma_context_data *context;
321 dma_addr_t context_phys;
322 struct dma_device dma_device;
323 struct clk *clk_ipg;
324 struct clk *clk_ahb;
325 spinlock_t channel_0_lock;
326 struct sdma_script_start_addrs *script_addrs;
327 const struct sdma_driver_data *drvdata;
328 };
329
330 static struct sdma_driver_data sdma_imx31 = {
331 .chnenbl0 = SDMA_CHNENBL0_IMX31,
332 .num_events = 32,
333 };
334
335 static struct sdma_script_start_addrs sdma_script_imx25 = {
336 .ap_2_ap_addr = 729,
337 .uart_2_mcu_addr = 904,
338 .per_2_app_addr = 1255,
339 .mcu_2_app_addr = 834,
340 .uartsh_2_mcu_addr = 1120,
341 .per_2_shp_addr = 1329,
342 .mcu_2_shp_addr = 1048,
343 .ata_2_mcu_addr = 1560,
344 .mcu_2_ata_addr = 1479,
345 .app_2_per_addr = 1189,
346 .app_2_mcu_addr = 770,
347 .shp_2_per_addr = 1407,
348 .shp_2_mcu_addr = 979,
349 };
350
351 static struct sdma_driver_data sdma_imx25 = {
352 .chnenbl0 = SDMA_CHNENBL0_IMX35,
353 .num_events = 48,
354 .script_addrs = &sdma_script_imx25,
355 };
356
357 static struct sdma_driver_data sdma_imx35 = {
358 .chnenbl0 = SDMA_CHNENBL0_IMX35,
359 .num_events = 48,
360 };
361
362 static struct sdma_script_start_addrs sdma_script_imx51 = {
363 .ap_2_ap_addr = 642,
364 .uart_2_mcu_addr = 817,
365 .mcu_2_app_addr = 747,
366 .mcu_2_shp_addr = 961,
367 .ata_2_mcu_addr = 1473,
368 .mcu_2_ata_addr = 1392,
369 .app_2_per_addr = 1033,
370 .app_2_mcu_addr = 683,
371 .shp_2_per_addr = 1251,
372 .shp_2_mcu_addr = 892,
373 };
374
375 static struct sdma_driver_data sdma_imx51 = {
376 .chnenbl0 = SDMA_CHNENBL0_IMX35,
377 .num_events = 48,
378 .script_addrs = &sdma_script_imx51,
379 };
380
381 static struct sdma_script_start_addrs sdma_script_imx53 = {
382 .ap_2_ap_addr = 642,
383 .app_2_mcu_addr = 683,
384 .mcu_2_app_addr = 747,
385 .uart_2_mcu_addr = 817,
386 .shp_2_mcu_addr = 891,
387 .mcu_2_shp_addr = 960,
388 .uartsh_2_mcu_addr = 1032,
389 .spdif_2_mcu_addr = 1100,
390 .mcu_2_spdif_addr = 1134,
391 .firi_2_mcu_addr = 1193,
392 .mcu_2_firi_addr = 1290,
393 };
394
395 static struct sdma_driver_data sdma_imx53 = {
396 .chnenbl0 = SDMA_CHNENBL0_IMX35,
397 .num_events = 48,
398 .script_addrs = &sdma_script_imx53,
399 };
400
401 static struct sdma_script_start_addrs sdma_script_imx6q = {
402 .ap_2_ap_addr = 642,
403 .uart_2_mcu_addr = 817,
404 .mcu_2_app_addr = 747,
405 .per_2_per_addr = 6331,
406 .uartsh_2_mcu_addr = 1032,
407 .mcu_2_shp_addr = 960,
408 .app_2_mcu_addr = 683,
409 .shp_2_mcu_addr = 891,
410 .spdif_2_mcu_addr = 1100,
411 .mcu_2_spdif_addr = 1134,
412 };
413
414 static struct sdma_driver_data sdma_imx6q = {
415 .chnenbl0 = SDMA_CHNENBL0_IMX35,
416 .num_events = 48,
417 .script_addrs = &sdma_script_imx6q,
418 };
419
420 static struct platform_device_id sdma_devtypes[] = {
421 {
422 .name = "imx25-sdma",
423 .driver_data = (unsigned long)&sdma_imx25,
424 }, {
425 .name = "imx31-sdma",
426 .driver_data = (unsigned long)&sdma_imx31,
427 }, {
428 .name = "imx35-sdma",
429 .driver_data = (unsigned long)&sdma_imx35,
430 }, {
431 .name = "imx51-sdma",
432 .driver_data = (unsigned long)&sdma_imx51,
433 }, {
434 .name = "imx53-sdma",
435 .driver_data = (unsigned long)&sdma_imx53,
436 }, {
437 .name = "imx6q-sdma",
438 .driver_data = (unsigned long)&sdma_imx6q,
439 }, {
440 /* sentinel */
441 }
442 };
443 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
444
445 static const struct of_device_id sdma_dt_ids[] = {
446 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
447 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
448 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
449 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
450 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
451 { /* sentinel */ }
452 };
453 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
454
455 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
456 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
457 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
458 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
459
460 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
461 {
462 u32 chnenbl0 = sdma->drvdata->chnenbl0;
463 return chnenbl0 + event * 4;
464 }
465
466 static int sdma_config_ownership(struct sdma_channel *sdmac,
467 bool event_override, bool mcu_override, bool dsp_override)
468 {
469 struct sdma_engine *sdma = sdmac->sdma;
470 int channel = sdmac->channel;
471 unsigned long evt, mcu, dsp;
472
473 if (event_override && mcu_override && dsp_override)
474 return -EINVAL;
475
476 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
477 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
478 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
479
480 if (dsp_override)
481 __clear_bit(channel, &dsp);
482 else
483 __set_bit(channel, &dsp);
484
485 if (event_override)
486 __clear_bit(channel, &evt);
487 else
488 __set_bit(channel, &evt);
489
490 if (mcu_override)
491 __clear_bit(channel, &mcu);
492 else
493 __set_bit(channel, &mcu);
494
495 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
496 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
497 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
498
499 return 0;
500 }
501
502 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
503 {
504 writel(BIT(channel), sdma->regs + SDMA_H_START);
505 }
506
507 /*
508 * sdma_run_channel0 - run a channel and wait till it's done
509 */
510 static int sdma_run_channel0(struct sdma_engine *sdma)
511 {
512 int ret;
513 unsigned long timeout = 500;
514
515 sdma_enable_channel(sdma, 0);
516
517 while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) {
518 if (timeout-- <= 0)
519 break;
520 udelay(1);
521 }
522
523 if (ret) {
524 /* Clear the interrupt status */
525 writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
526 } else {
527 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
528 }
529
530 return ret ? 0 : -ETIMEDOUT;
531 }
532
533 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
534 u32 address)
535 {
536 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
537 void *buf_virt;
538 dma_addr_t buf_phys;
539 int ret;
540 unsigned long flags;
541
542 buf_virt = dma_alloc_coherent(NULL,
543 size,
544 &buf_phys, GFP_KERNEL);
545 if (!buf_virt) {
546 return -ENOMEM;
547 }
548
549 spin_lock_irqsave(&sdma->channel_0_lock, flags);
550
551 bd0->mode.command = C0_SETPM;
552 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
553 bd0->mode.count = size / 2;
554 bd0->buffer_addr = buf_phys;
555 bd0->ext_buffer_addr = address;
556
557 memcpy(buf_virt, buf, size);
558
559 ret = sdma_run_channel0(sdma);
560
561 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
562
563 dma_free_coherent(NULL, size, buf_virt, buf_phys);
564
565 return ret;
566 }
567
568 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
569 {
570 struct sdma_engine *sdma = sdmac->sdma;
571 int channel = sdmac->channel;
572 unsigned long val;
573 u32 chnenbl = chnenbl_ofs(sdma, event);
574
575 val = readl_relaxed(sdma->regs + chnenbl);
576 __set_bit(channel, &val);
577 writel_relaxed(val, sdma->regs + chnenbl);
578 }
579
580 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
581 {
582 struct sdma_engine *sdma = sdmac->sdma;
583 int channel = sdmac->channel;
584 u32 chnenbl = chnenbl_ofs(sdma, event);
585 unsigned long val;
586
587 val = readl_relaxed(sdma->regs + chnenbl);
588 __clear_bit(channel, &val);
589 writel_relaxed(val, sdma->regs + chnenbl);
590 }
591
592 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
593 {
594 struct sdma_buffer_descriptor *bd;
595
596 /*
597 * loop mode. Iterate over descriptors, re-setup them and
598 * call callback function.
599 */
600 while (1) {
601 bd = &sdmac->bd[sdmac->buf_tail];
602
603 if (bd->mode.status & BD_DONE)
604 break;
605
606 if (bd->mode.status & BD_RROR)
607 sdmac->status = DMA_ERROR;
608 else
609 sdmac->status = DMA_IN_PROGRESS;
610
611 bd->mode.status |= BD_DONE;
612 sdmac->buf_tail++;
613 sdmac->buf_tail %= sdmac->num_bd;
614
615 if (sdmac->desc.callback)
616 sdmac->desc.callback(sdmac->desc.callback_param);
617 }
618 }
619
620 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
621 {
622 struct sdma_buffer_descriptor *bd;
623 int i, error = 0;
624
625 sdmac->chn_real_count = 0;
626 /*
627 * non loop mode. Iterate over all descriptors, collect
628 * errors and call callback function
629 */
630 for (i = 0; i < sdmac->num_bd; i++) {
631 bd = &sdmac->bd[i];
632
633 if (bd->mode.status & (BD_DONE | BD_RROR))
634 error = -EIO;
635 sdmac->chn_real_count += bd->mode.count;
636 }
637
638 if (error)
639 sdmac->status = DMA_ERROR;
640 else
641 sdmac->status = DMA_SUCCESS;
642
643 dma_cookie_complete(&sdmac->desc);
644 if (sdmac->desc.callback)
645 sdmac->desc.callback(sdmac->desc.callback_param);
646 }
647
648 static void sdma_tasklet(unsigned long data)
649 {
650 struct sdma_channel *sdmac = (struct sdma_channel *) data;
651
652 if (sdmac->flags & IMX_DMA_SG_LOOP)
653 sdma_handle_channel_loop(sdmac);
654 else
655 mxc_sdma_handle_channel_normal(sdmac);
656 }
657
658 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
659 {
660 struct sdma_engine *sdma = dev_id;
661 unsigned long stat;
662
663 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
664 /* not interested in channel 0 interrupts */
665 stat &= ~1;
666 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
667
668 while (stat) {
669 int channel = fls(stat) - 1;
670 struct sdma_channel *sdmac = &sdma->channel[channel];
671
672 tasklet_schedule(&sdmac->tasklet);
673
674 __clear_bit(channel, &stat);
675 }
676
677 return IRQ_HANDLED;
678 }
679
680 /*
681 * sets the pc of SDMA script according to the peripheral type
682 */
683 static void sdma_get_pc(struct sdma_channel *sdmac,
684 enum sdma_peripheral_type peripheral_type)
685 {
686 struct sdma_engine *sdma = sdmac->sdma;
687 int per_2_emi = 0, emi_2_per = 0;
688 /*
689 * These are needed once we start to support transfers between
690 * two peripherals or memory-to-memory transfers
691 */
692 int per_2_per = 0, emi_2_emi = 0;
693
694 sdmac->pc_from_device = 0;
695 sdmac->pc_to_device = 0;
696
697 switch (peripheral_type) {
698 case IMX_DMATYPE_MEMORY:
699 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
700 break;
701 case IMX_DMATYPE_DSP:
702 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
703 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
704 break;
705 case IMX_DMATYPE_FIRI:
706 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
707 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
708 break;
709 case IMX_DMATYPE_UART:
710 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
711 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
712 break;
713 case IMX_DMATYPE_UART_SP:
714 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
715 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
716 break;
717 case IMX_DMATYPE_ATA:
718 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
719 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
720 break;
721 case IMX_DMATYPE_CSPI:
722 case IMX_DMATYPE_EXT:
723 case IMX_DMATYPE_SSI:
724 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
725 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
726 break;
727 case IMX_DMATYPE_SSI_SP:
728 case IMX_DMATYPE_MMC:
729 case IMX_DMATYPE_SDHC:
730 case IMX_DMATYPE_CSPI_SP:
731 case IMX_DMATYPE_ESAI:
732 case IMX_DMATYPE_MSHC_SP:
733 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
734 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
735 break;
736 case IMX_DMATYPE_ASRC:
737 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
738 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
739 per_2_per = sdma->script_addrs->per_2_per_addr;
740 break;
741 case IMX_DMATYPE_MSHC:
742 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
743 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
744 break;
745 case IMX_DMATYPE_CCM:
746 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
747 break;
748 case IMX_DMATYPE_SPDIF:
749 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
750 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
751 break;
752 case IMX_DMATYPE_IPU_MEMORY:
753 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
754 break;
755 default:
756 break;
757 }
758
759 sdmac->pc_from_device = per_2_emi;
760 sdmac->pc_to_device = emi_2_per;
761 }
762
763 static int sdma_load_context(struct sdma_channel *sdmac)
764 {
765 struct sdma_engine *sdma = sdmac->sdma;
766 int channel = sdmac->channel;
767 int load_address;
768 struct sdma_context_data *context = sdma->context;
769 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
770 int ret;
771 unsigned long flags;
772
773 if (sdmac->direction == DMA_DEV_TO_MEM) {
774 load_address = sdmac->pc_from_device;
775 } else {
776 load_address = sdmac->pc_to_device;
777 }
778
779 if (load_address < 0)
780 return load_address;
781
782 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
783 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
784 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
785 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
786 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
787 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
788
789 spin_lock_irqsave(&sdma->channel_0_lock, flags);
790
791 memset(context, 0, sizeof(*context));
792 context->channel_state.pc = load_address;
793
794 /* Send by context the event mask,base address for peripheral
795 * and watermark level
796 */
797 context->gReg[0] = sdmac->event_mask[1];
798 context->gReg[1] = sdmac->event_mask[0];
799 context->gReg[2] = sdmac->per_addr;
800 context->gReg[6] = sdmac->shp_addr;
801 context->gReg[7] = sdmac->watermark_level;
802
803 bd0->mode.command = C0_SETDM;
804 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
805 bd0->mode.count = sizeof(*context) / 4;
806 bd0->buffer_addr = sdma->context_phys;
807 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
808 ret = sdma_run_channel0(sdma);
809
810 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
811
812 return ret;
813 }
814
815 static void sdma_disable_channel(struct sdma_channel *sdmac)
816 {
817 struct sdma_engine *sdma = sdmac->sdma;
818 int channel = sdmac->channel;
819
820 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
821 sdmac->status = DMA_ERROR;
822 }
823
824 static int sdma_config_channel(struct sdma_channel *sdmac)
825 {
826 int ret;
827
828 sdma_disable_channel(sdmac);
829
830 sdmac->event_mask[0] = 0;
831 sdmac->event_mask[1] = 0;
832 sdmac->shp_addr = 0;
833 sdmac->per_addr = 0;
834
835 if (sdmac->event_id0) {
836 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
837 return -EINVAL;
838 sdma_event_enable(sdmac, sdmac->event_id0);
839 }
840
841 switch (sdmac->peripheral_type) {
842 case IMX_DMATYPE_DSP:
843 sdma_config_ownership(sdmac, false, true, true);
844 break;
845 case IMX_DMATYPE_MEMORY:
846 sdma_config_ownership(sdmac, false, true, false);
847 break;
848 default:
849 sdma_config_ownership(sdmac, true, true, false);
850 break;
851 }
852
853 sdma_get_pc(sdmac, sdmac->peripheral_type);
854
855 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
856 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
857 /* Handle multiple event channels differently */
858 if (sdmac->event_id1) {
859 sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32);
860 if (sdmac->event_id1 > 31)
861 __set_bit(31, &sdmac->watermark_level);
862 sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32);
863 if (sdmac->event_id0 > 31)
864 __set_bit(30, &sdmac->watermark_level);
865 } else {
866 __set_bit(sdmac->event_id0, sdmac->event_mask);
867 }
868 /* Watermark Level */
869 sdmac->watermark_level |= sdmac->watermark_level;
870 /* Address */
871 sdmac->shp_addr = sdmac->per_address;
872 } else {
873 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
874 }
875
876 ret = sdma_load_context(sdmac);
877
878 return ret;
879 }
880
881 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
882 unsigned int priority)
883 {
884 struct sdma_engine *sdma = sdmac->sdma;
885 int channel = sdmac->channel;
886
887 if (priority < MXC_SDMA_MIN_PRIORITY
888 || priority > MXC_SDMA_MAX_PRIORITY) {
889 return -EINVAL;
890 }
891
892 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
893
894 return 0;
895 }
896
897 static int sdma_request_channel(struct sdma_channel *sdmac)
898 {
899 struct sdma_engine *sdma = sdmac->sdma;
900 int channel = sdmac->channel;
901 int ret = -EBUSY;
902
903 sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
904 if (!sdmac->bd) {
905 ret = -ENOMEM;
906 goto out;
907 }
908
909 memset(sdmac->bd, 0, PAGE_SIZE);
910
911 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
912 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
913
914 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
915 return 0;
916 out:
917
918 return ret;
919 }
920
921 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
922 {
923 return container_of(chan, struct sdma_channel, chan);
924 }
925
926 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
927 {
928 unsigned long flags;
929 struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
930 dma_cookie_t cookie;
931
932 spin_lock_irqsave(&sdmac->lock, flags);
933
934 cookie = dma_cookie_assign(tx);
935
936 spin_unlock_irqrestore(&sdmac->lock, flags);
937
938 return cookie;
939 }
940
941 static int sdma_alloc_chan_resources(struct dma_chan *chan)
942 {
943 struct sdma_channel *sdmac = to_sdma_chan(chan);
944 struct imx_dma_data *data = chan->private;
945 int prio, ret;
946
947 if (!data)
948 return -EINVAL;
949
950 switch (data->priority) {
951 case DMA_PRIO_HIGH:
952 prio = 3;
953 break;
954 case DMA_PRIO_MEDIUM:
955 prio = 2;
956 break;
957 case DMA_PRIO_LOW:
958 default:
959 prio = 1;
960 break;
961 }
962
963 sdmac->peripheral_type = data->peripheral_type;
964 sdmac->event_id0 = data->dma_request;
965
966 clk_enable(sdmac->sdma->clk_ipg);
967 clk_enable(sdmac->sdma->clk_ahb);
968
969 ret = sdma_request_channel(sdmac);
970 if (ret)
971 return ret;
972
973 ret = sdma_set_channel_priority(sdmac, prio);
974 if (ret)
975 return ret;
976
977 dma_async_tx_descriptor_init(&sdmac->desc, chan);
978 sdmac->desc.tx_submit = sdma_tx_submit;
979 /* txd.flags will be overwritten in prep funcs */
980 sdmac->desc.flags = DMA_CTRL_ACK;
981
982 return 0;
983 }
984
985 static void sdma_free_chan_resources(struct dma_chan *chan)
986 {
987 struct sdma_channel *sdmac = to_sdma_chan(chan);
988 struct sdma_engine *sdma = sdmac->sdma;
989
990 sdma_disable_channel(sdmac);
991
992 if (sdmac->event_id0)
993 sdma_event_disable(sdmac, sdmac->event_id0);
994 if (sdmac->event_id1)
995 sdma_event_disable(sdmac, sdmac->event_id1);
996
997 sdmac->event_id0 = 0;
998 sdmac->event_id1 = 0;
999
1000 sdma_set_channel_priority(sdmac, 0);
1001
1002 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
1003
1004 clk_disable(sdma->clk_ipg);
1005 clk_disable(sdma->clk_ahb);
1006 }
1007
1008 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1009 struct dma_chan *chan, struct scatterlist *sgl,
1010 unsigned int sg_len, enum dma_transfer_direction direction,
1011 unsigned long flags, void *context)
1012 {
1013 struct sdma_channel *sdmac = to_sdma_chan(chan);
1014 struct sdma_engine *sdma = sdmac->sdma;
1015 int ret, i, count;
1016 int channel = sdmac->channel;
1017 struct scatterlist *sg;
1018
1019 if (sdmac->status == DMA_IN_PROGRESS)
1020 return NULL;
1021 sdmac->status = DMA_IN_PROGRESS;
1022
1023 sdmac->flags = 0;
1024
1025 sdmac->buf_tail = 0;
1026
1027 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1028 sg_len, channel);
1029
1030 sdmac->direction = direction;
1031 ret = sdma_load_context(sdmac);
1032 if (ret)
1033 goto err_out;
1034
1035 if (sg_len > NUM_BD) {
1036 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1037 channel, sg_len, NUM_BD);
1038 ret = -EINVAL;
1039 goto err_out;
1040 }
1041
1042 sdmac->chn_count = 0;
1043 for_each_sg(sgl, sg, sg_len, i) {
1044 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1045 int param;
1046
1047 bd->buffer_addr = sg->dma_address;
1048
1049 count = sg_dma_len(sg);
1050
1051 if (count > 0xffff) {
1052 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1053 channel, count, 0xffff);
1054 ret = -EINVAL;
1055 goto err_out;
1056 }
1057
1058 bd->mode.count = count;
1059 sdmac->chn_count += count;
1060
1061 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1062 ret = -EINVAL;
1063 goto err_out;
1064 }
1065
1066 switch (sdmac->word_size) {
1067 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1068 bd->mode.command = 0;
1069 if (count & 3 || sg->dma_address & 3)
1070 return NULL;
1071 break;
1072 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1073 bd->mode.command = 2;
1074 if (count & 1 || sg->dma_address & 1)
1075 return NULL;
1076 break;
1077 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1078 bd->mode.command = 1;
1079 break;
1080 default:
1081 return NULL;
1082 }
1083
1084 param = BD_DONE | BD_EXTD | BD_CONT;
1085
1086 if (i + 1 == sg_len) {
1087 param |= BD_INTR;
1088 param |= BD_LAST;
1089 param &= ~BD_CONT;
1090 }
1091
1092 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1093 i, count, sg->dma_address,
1094 param & BD_WRAP ? "wrap" : "",
1095 param & BD_INTR ? " intr" : "");
1096
1097 bd->mode.status = param;
1098 }
1099
1100 sdmac->num_bd = sg_len;
1101 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1102
1103 return &sdmac->desc;
1104 err_out:
1105 sdmac->status = DMA_ERROR;
1106 return NULL;
1107 }
1108
1109 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1110 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1111 size_t period_len, enum dma_transfer_direction direction,
1112 unsigned long flags, void *context)
1113 {
1114 struct sdma_channel *sdmac = to_sdma_chan(chan);
1115 struct sdma_engine *sdma = sdmac->sdma;
1116 int num_periods = buf_len / period_len;
1117 int channel = sdmac->channel;
1118 int ret, i = 0, buf = 0;
1119
1120 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1121
1122 if (sdmac->status == DMA_IN_PROGRESS)
1123 return NULL;
1124
1125 sdmac->status = DMA_IN_PROGRESS;
1126
1127 sdmac->buf_tail = 0;
1128
1129 sdmac->flags |= IMX_DMA_SG_LOOP;
1130 sdmac->direction = direction;
1131 ret = sdma_load_context(sdmac);
1132 if (ret)
1133 goto err_out;
1134
1135 if (num_periods > NUM_BD) {
1136 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1137 channel, num_periods, NUM_BD);
1138 goto err_out;
1139 }
1140
1141 if (period_len > 0xffff) {
1142 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1143 channel, period_len, 0xffff);
1144 goto err_out;
1145 }
1146
1147 while (buf < buf_len) {
1148 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1149 int param;
1150
1151 bd->buffer_addr = dma_addr;
1152
1153 bd->mode.count = period_len;
1154
1155 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1156 goto err_out;
1157 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1158 bd->mode.command = 0;
1159 else
1160 bd->mode.command = sdmac->word_size;
1161
1162 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1163 if (i + 1 == num_periods)
1164 param |= BD_WRAP;
1165
1166 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1167 i, period_len, dma_addr,
1168 param & BD_WRAP ? "wrap" : "",
1169 param & BD_INTR ? " intr" : "");
1170
1171 bd->mode.status = param;
1172
1173 dma_addr += period_len;
1174 buf += period_len;
1175
1176 i++;
1177 }
1178
1179 sdmac->num_bd = num_periods;
1180 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1181
1182 return &sdmac->desc;
1183 err_out:
1184 sdmac->status = DMA_ERROR;
1185 return NULL;
1186 }
1187
1188 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1189 unsigned long arg)
1190 {
1191 struct sdma_channel *sdmac = to_sdma_chan(chan);
1192 struct dma_slave_config *dmaengine_cfg = (void *)arg;
1193
1194 switch (cmd) {
1195 case DMA_TERMINATE_ALL:
1196 sdma_disable_channel(sdmac);
1197 return 0;
1198 case DMA_SLAVE_CONFIG:
1199 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1200 sdmac->per_address = dmaengine_cfg->src_addr;
1201 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1202 dmaengine_cfg->src_addr_width;
1203 sdmac->word_size = dmaengine_cfg->src_addr_width;
1204 } else {
1205 sdmac->per_address = dmaengine_cfg->dst_addr;
1206 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1207 dmaengine_cfg->dst_addr_width;
1208 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1209 }
1210 sdmac->direction = dmaengine_cfg->direction;
1211 return sdma_config_channel(sdmac);
1212 default:
1213 return -ENOSYS;
1214 }
1215
1216 return -EINVAL;
1217 }
1218
1219 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1220 dma_cookie_t cookie,
1221 struct dma_tx_state *txstate)
1222 {
1223 struct sdma_channel *sdmac = to_sdma_chan(chan);
1224
1225 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1226 sdmac->chn_count - sdmac->chn_real_count);
1227
1228 return sdmac->status;
1229 }
1230
1231 static void sdma_issue_pending(struct dma_chan *chan)
1232 {
1233 struct sdma_channel *sdmac = to_sdma_chan(chan);
1234 struct sdma_engine *sdma = sdmac->sdma;
1235
1236 if (sdmac->status == DMA_IN_PROGRESS)
1237 sdma_enable_channel(sdma, sdmac->channel);
1238 }
1239
1240 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1241
1242 static void sdma_add_scripts(struct sdma_engine *sdma,
1243 const struct sdma_script_start_addrs *addr)
1244 {
1245 s32 *addr_arr = (u32 *)addr;
1246 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1247 int i;
1248
1249 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1250 if (addr_arr[i] > 0)
1251 saddr_arr[i] = addr_arr[i];
1252 }
1253
1254 static void sdma_load_firmware(const struct firmware *fw, void *context)
1255 {
1256 struct sdma_engine *sdma = context;
1257 const struct sdma_firmware_header *header;
1258 const struct sdma_script_start_addrs *addr;
1259 unsigned short *ram_code;
1260
1261 if (!fw) {
1262 dev_err(sdma->dev, "firmware not found\n");
1263 return;
1264 }
1265
1266 if (fw->size < sizeof(*header))
1267 goto err_firmware;
1268
1269 header = (struct sdma_firmware_header *)fw->data;
1270
1271 if (header->magic != SDMA_FIRMWARE_MAGIC)
1272 goto err_firmware;
1273 if (header->ram_code_start + header->ram_code_size > fw->size)
1274 goto err_firmware;
1275
1276 addr = (void *)header + header->script_addrs_start;
1277 ram_code = (void *)header + header->ram_code_start;
1278
1279 clk_enable(sdma->clk_ipg);
1280 clk_enable(sdma->clk_ahb);
1281 /* download the RAM image for SDMA */
1282 sdma_load_script(sdma, ram_code,
1283 header->ram_code_size,
1284 addr->ram_code_start_addr);
1285 clk_disable(sdma->clk_ipg);
1286 clk_disable(sdma->clk_ahb);
1287
1288 sdma_add_scripts(sdma, addr);
1289
1290 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1291 header->version_major,
1292 header->version_minor);
1293
1294 err_firmware:
1295 release_firmware(fw);
1296 }
1297
1298 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1299 const char *fw_name)
1300 {
1301 int ret;
1302
1303 ret = request_firmware_nowait(THIS_MODULE,
1304 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1305 GFP_KERNEL, sdma, sdma_load_firmware);
1306
1307 return ret;
1308 }
1309
1310 static int __init sdma_init(struct sdma_engine *sdma)
1311 {
1312 int i, ret;
1313 dma_addr_t ccb_phys;
1314
1315 clk_enable(sdma->clk_ipg);
1316 clk_enable(sdma->clk_ahb);
1317
1318 /* Be sure SDMA has not started yet */
1319 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1320
1321 sdma->channel_control = dma_alloc_coherent(NULL,
1322 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1323 sizeof(struct sdma_context_data),
1324 &ccb_phys, GFP_KERNEL);
1325
1326 if (!sdma->channel_control) {
1327 ret = -ENOMEM;
1328 goto err_dma_alloc;
1329 }
1330
1331 sdma->context = (void *)sdma->channel_control +
1332 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1333 sdma->context_phys = ccb_phys +
1334 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1335
1336 /* Zero-out the CCB structures array just allocated */
1337 memset(sdma->channel_control, 0,
1338 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1339
1340 /* disable all channels */
1341 for (i = 0; i < sdma->drvdata->num_events; i++)
1342 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1343
1344 /* All channels have priority 0 */
1345 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1346 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1347
1348 ret = sdma_request_channel(&sdma->channel[0]);
1349 if (ret)
1350 goto err_dma_alloc;
1351
1352 sdma_config_ownership(&sdma->channel[0], false, true, false);
1353
1354 /* Set Command Channel (Channel Zero) */
1355 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1356
1357 /* Set bits of CONFIG register but with static context switching */
1358 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1359 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1360
1361 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1362
1363 /* Set bits of CONFIG register with given context switching mode */
1364 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1365
1366 /* Initializes channel's priorities */
1367 sdma_set_channel_priority(&sdma->channel[0], 7);
1368
1369 clk_disable(sdma->clk_ipg);
1370 clk_disable(sdma->clk_ahb);
1371
1372 return 0;
1373
1374 err_dma_alloc:
1375 clk_disable(sdma->clk_ipg);
1376 clk_disable(sdma->clk_ahb);
1377 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1378 return ret;
1379 }
1380
1381 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1382 {
1383 struct imx_dma_data *data = fn_param;
1384
1385 if (!imx_dma_is_general_purpose(chan))
1386 return false;
1387
1388 chan->private = data;
1389
1390 return true;
1391 }
1392
1393 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1394 struct of_dma *ofdma)
1395 {
1396 struct sdma_engine *sdma = ofdma->of_dma_data;
1397 dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1398 struct imx_dma_data data;
1399
1400 if (dma_spec->args_count != 3)
1401 return NULL;
1402
1403 data.dma_request = dma_spec->args[0];
1404 data.peripheral_type = dma_spec->args[1];
1405 data.priority = dma_spec->args[2];
1406
1407 return dma_request_channel(mask, sdma_filter_fn, &data);
1408 }
1409
1410 static int __init sdma_probe(struct platform_device *pdev)
1411 {
1412 const struct of_device_id *of_id =
1413 of_match_device(sdma_dt_ids, &pdev->dev);
1414 struct device_node *np = pdev->dev.of_node;
1415 const char *fw_name;
1416 int ret;
1417 int irq;
1418 struct resource *iores;
1419 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1420 int i;
1421 struct sdma_engine *sdma;
1422 s32 *saddr_arr;
1423 const struct sdma_driver_data *drvdata = NULL;
1424
1425 if (of_id)
1426 drvdata = of_id->data;
1427 else if (pdev->id_entry)
1428 drvdata = (void *)pdev->id_entry->driver_data;
1429
1430 if (!drvdata) {
1431 dev_err(&pdev->dev, "unable to find driver data\n");
1432 return -EINVAL;
1433 }
1434
1435 sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1436 if (!sdma)
1437 return -ENOMEM;
1438
1439 spin_lock_init(&sdma->channel_0_lock);
1440
1441 sdma->dev = &pdev->dev;
1442 sdma->drvdata = drvdata;
1443
1444 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1445 irq = platform_get_irq(pdev, 0);
1446 if (!iores || irq < 0) {
1447 ret = -EINVAL;
1448 goto err_irq;
1449 }
1450
1451 if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1452 ret = -EBUSY;
1453 goto err_request_region;
1454 }
1455
1456 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1457 if (IS_ERR(sdma->clk_ipg)) {
1458 ret = PTR_ERR(sdma->clk_ipg);
1459 goto err_clk;
1460 }
1461
1462 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1463 if (IS_ERR(sdma->clk_ahb)) {
1464 ret = PTR_ERR(sdma->clk_ahb);
1465 goto err_clk;
1466 }
1467
1468 clk_prepare(sdma->clk_ipg);
1469 clk_prepare(sdma->clk_ahb);
1470
1471 sdma->regs = ioremap(iores->start, resource_size(iores));
1472 if (!sdma->regs) {
1473 ret = -ENOMEM;
1474 goto err_ioremap;
1475 }
1476
1477 ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1478 if (ret)
1479 goto err_request_irq;
1480
1481 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1482 if (!sdma->script_addrs) {
1483 ret = -ENOMEM;
1484 goto err_alloc;
1485 }
1486
1487 /* initially no scripts available */
1488 saddr_arr = (s32 *)sdma->script_addrs;
1489 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1490 saddr_arr[i] = -EINVAL;
1491
1492 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1493 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1494
1495 INIT_LIST_HEAD(&sdma->dma_device.channels);
1496 /* Initialize channel parameters */
1497 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1498 struct sdma_channel *sdmac = &sdma->channel[i];
1499
1500 sdmac->sdma = sdma;
1501 spin_lock_init(&sdmac->lock);
1502
1503 sdmac->chan.device = &sdma->dma_device;
1504 dma_cookie_init(&sdmac->chan);
1505 sdmac->channel = i;
1506
1507 tasklet_init(&sdmac->tasklet, sdma_tasklet,
1508 (unsigned long) sdmac);
1509 /*
1510 * Add the channel to the DMAC list. Do not add channel 0 though
1511 * because we need it internally in the SDMA driver. This also means
1512 * that channel 0 in dmaengine counting matches sdma channel 1.
1513 */
1514 if (i)
1515 list_add_tail(&sdmac->chan.device_node,
1516 &sdma->dma_device.channels);
1517 }
1518
1519 ret = sdma_init(sdma);
1520 if (ret)
1521 goto err_init;
1522
1523 if (sdma->drvdata->script_addrs)
1524 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1525 if (pdata && pdata->script_addrs)
1526 sdma_add_scripts(sdma, pdata->script_addrs);
1527
1528 if (pdata) {
1529 ret = sdma_get_firmware(sdma, pdata->fw_name);
1530 if (ret)
1531 dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1532 } else {
1533 /*
1534 * Because that device tree does not encode ROM script address,
1535 * the RAM script in firmware is mandatory for device tree
1536 * probe, otherwise it fails.
1537 */
1538 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1539 &fw_name);
1540 if (ret)
1541 dev_warn(&pdev->dev, "failed to get firmware name\n");
1542 else {
1543 ret = sdma_get_firmware(sdma, fw_name);
1544 if (ret)
1545 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1546 }
1547 }
1548
1549 sdma->dma_device.dev = &pdev->dev;
1550
1551 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1552 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1553 sdma->dma_device.device_tx_status = sdma_tx_status;
1554 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1555 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1556 sdma->dma_device.device_control = sdma_control;
1557 sdma->dma_device.device_issue_pending = sdma_issue_pending;
1558 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1559 dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1560
1561 ret = dma_async_device_register(&sdma->dma_device);
1562 if (ret) {
1563 dev_err(&pdev->dev, "unable to register\n");
1564 goto err_init;
1565 }
1566
1567 if (np) {
1568 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1569 if (ret) {
1570 dev_err(&pdev->dev, "failed to register controller\n");
1571 goto err_register;
1572 }
1573 }
1574
1575 dev_info(sdma->dev, "initialized\n");
1576
1577 return 0;
1578
1579 err_register:
1580 dma_async_device_unregister(&sdma->dma_device);
1581 err_init:
1582 kfree(sdma->script_addrs);
1583 err_alloc:
1584 free_irq(irq, sdma);
1585 err_request_irq:
1586 iounmap(sdma->regs);
1587 err_ioremap:
1588 err_clk:
1589 release_mem_region(iores->start, resource_size(iores));
1590 err_request_region:
1591 err_irq:
1592 kfree(sdma);
1593 return ret;
1594 }
1595
1596 static int sdma_remove(struct platform_device *pdev)
1597 {
1598 return -EBUSY;
1599 }
1600
1601 static struct platform_driver sdma_driver = {
1602 .driver = {
1603 .name = "imx-sdma",
1604 .of_match_table = sdma_dt_ids,
1605 },
1606 .id_table = sdma_devtypes,
1607 .remove = sdma_remove,
1608 };
1609
1610 static int __init sdma_module_init(void)
1611 {
1612 return platform_driver_probe(&sdma_driver, sdma_probe);
1613 }
1614 module_init(sdma_module_init);
1615
1616 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1617 MODULE_DESCRIPTION("i.MX SDMA driver");
1618 MODULE_LICENSE("GPL");
Linux with added FPC-III support