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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / dma / ioat / dma_v3.c
blob476017f7ea023a5fc33ade0d699edc285865a582
1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 *
22 * The full GNU General Public License is included in this distribution in
23 * the file called "COPYING".
24 *
25 * BSD LICENSE
26 *
27 * Copyright(c) 2004-2009 Intel Corporation. All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions are met:
31 *
32 * * Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * * Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in
36 * the documentation and/or other materials provided with the
37 * distribution.
38 * * Neither the name of Intel Corporation nor the names of its
39 * contributors may be used to endorse or promote products derived
40 * from this software without specific prior written permission.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
46 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
47 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
48 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
49 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
50 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
51 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
52 * POSSIBILITY OF SUCH DAMAGE.
53 */
54
55 /*
56 * Support routines for v3+ hardware
57 */
58 #include <linux/module.h>
59 #include <linux/pci.h>
60 #include <linux/gfp.h>
61 #include <linux/dmaengine.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/prefetch.h>
64 #include "../dmaengine.h"
65 #include "registers.h"
66 #include "hw.h"
67 #include "dma.h"
68 #include "dma_v2.h"
69
70 /* ioat hardware assumes at least two sources for raid operations */
71 #define src_cnt_to_sw(x) ((x) + 2)
72 #define src_cnt_to_hw(x) ((x) - 2)
73 #define ndest_to_sw(x) ((x) + 1)
74 #define ndest_to_hw(x) ((x) - 1)
75 #define src16_cnt_to_sw(x) ((x) + 9)
76 #define src16_cnt_to_hw(x) ((x) - 9)
77
78 /* provide a lookup table for setting the source address in the base or
79 * extended descriptor of an xor or pq descriptor
80 */
81 static const u8 xor_idx_to_desc = 0xe0;
82 static const u8 xor_idx_to_field[] = { 1, 4, 5, 6, 7, 0, 1, 2 };
83 static const u8 pq_idx_to_desc = 0xf8;
84 static const u8 pq16_idx_to_desc[] = { 0, 0, 1, 1, 1, 1, 1, 1, 1,
85 2, 2, 2, 2, 2, 2, 2 };
86 static const u8 pq_idx_to_field[] = { 1, 4, 5, 0, 1, 2, 4, 5 };
87 static const u8 pq16_idx_to_field[] = { 1, 4, 1, 2, 3, 4, 5, 6, 7,
88 0, 1, 2, 3, 4, 5, 6 };
89
90 static void ioat3_eh(struct ioat2_dma_chan *ioat);
91
92 static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx)
93 {
94 struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1];
95
96 return raw->field[xor_idx_to_field[idx]];
97 }
98
99 static void xor_set_src(struct ioat_raw_descriptor *descs[2],
100 dma_addr_t addr, u32 offset, int idx)
101 {
102 struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1];
103
104 raw->field[xor_idx_to_field[idx]] = addr + offset;
105 }
106
107 static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx)
108 {
109 struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1];
110
111 return raw->field[pq_idx_to_field[idx]];
112 }
113
114 static dma_addr_t pq16_get_src(struct ioat_raw_descriptor *desc[3], int idx)
115 {
116 struct ioat_raw_descriptor *raw = desc[pq16_idx_to_desc[idx]];
117
118 return raw->field[pq16_idx_to_field[idx]];
119 }
120
121 static void pq_set_src(struct ioat_raw_descriptor *descs[2],
122 dma_addr_t addr, u32 offset, u8 coef, int idx)
123 {
124 struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0];
125 struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1];
126
127 raw->field[pq_idx_to_field[idx]] = addr + offset;
128 pq->coef[idx] = coef;
129 }
130
131 static bool is_jf_ioat(struct pci_dev *pdev)
132 {
133 switch (pdev->device) {
134 case PCI_DEVICE_ID_INTEL_IOAT_JSF0:
135 case PCI_DEVICE_ID_INTEL_IOAT_JSF1:
136 case PCI_DEVICE_ID_INTEL_IOAT_JSF2:
137 case PCI_DEVICE_ID_INTEL_IOAT_JSF3:
138 case PCI_DEVICE_ID_INTEL_IOAT_JSF4:
139 case PCI_DEVICE_ID_INTEL_IOAT_JSF5:
140 case PCI_DEVICE_ID_INTEL_IOAT_JSF6:
141 case PCI_DEVICE_ID_INTEL_IOAT_JSF7:
142 case PCI_DEVICE_ID_INTEL_IOAT_JSF8:
143 case PCI_DEVICE_ID_INTEL_IOAT_JSF9:
144 return true;
145 default:
146 return false;
147 }
148 }
149
150 static bool is_snb_ioat(struct pci_dev *pdev)
151 {
152 switch (pdev->device) {
153 case PCI_DEVICE_ID_INTEL_IOAT_SNB0:
154 case PCI_DEVICE_ID_INTEL_IOAT_SNB1:
155 case PCI_DEVICE_ID_INTEL_IOAT_SNB2:
156 case PCI_DEVICE_ID_INTEL_IOAT_SNB3:
157 case PCI_DEVICE_ID_INTEL_IOAT_SNB4:
158 case PCI_DEVICE_ID_INTEL_IOAT_SNB5:
159 case PCI_DEVICE_ID_INTEL_IOAT_SNB6:
160 case PCI_DEVICE_ID_INTEL_IOAT_SNB7:
161 case PCI_DEVICE_ID_INTEL_IOAT_SNB8:
162 case PCI_DEVICE_ID_INTEL_IOAT_SNB9:
163 return true;
164 default:
165 return false;
166 }
167 }
168
169 static bool is_ivb_ioat(struct pci_dev *pdev)
170 {
171 switch (pdev->device) {
172 case PCI_DEVICE_ID_INTEL_IOAT_IVB0:
173 case PCI_DEVICE_ID_INTEL_IOAT_IVB1:
174 case PCI_DEVICE_ID_INTEL_IOAT_IVB2:
175 case PCI_DEVICE_ID_INTEL_IOAT_IVB3:
176 case PCI_DEVICE_ID_INTEL_IOAT_IVB4:
177 case PCI_DEVICE_ID_INTEL_IOAT_IVB5:
178 case PCI_DEVICE_ID_INTEL_IOAT_IVB6:
179 case PCI_DEVICE_ID_INTEL_IOAT_IVB7:
180 case PCI_DEVICE_ID_INTEL_IOAT_IVB8:
181 case PCI_DEVICE_ID_INTEL_IOAT_IVB9:
182 return true;
183 default:
184 return false;
185 }
186
187 }
188
189 static bool is_hsw_ioat(struct pci_dev *pdev)
190 {
191 switch (pdev->device) {
192 case PCI_DEVICE_ID_INTEL_IOAT_HSW0:
193 case PCI_DEVICE_ID_INTEL_IOAT_HSW1:
194 case PCI_DEVICE_ID_INTEL_IOAT_HSW2:
195 case PCI_DEVICE_ID_INTEL_IOAT_HSW3:
196 case PCI_DEVICE_ID_INTEL_IOAT_HSW4:
197 case PCI_DEVICE_ID_INTEL_IOAT_HSW5:
198 case PCI_DEVICE_ID_INTEL_IOAT_HSW6:
199 case PCI_DEVICE_ID_INTEL_IOAT_HSW7:
200 case PCI_DEVICE_ID_INTEL_IOAT_HSW8:
201 case PCI_DEVICE_ID_INTEL_IOAT_HSW9:
202 return true;
203 default:
204 return false;
205 }
206
207 }
208
209 static bool is_xeon_cb32(struct pci_dev *pdev)
210 {
211 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) ||
212 is_hsw_ioat(pdev);
213 }
214
215 static bool is_bwd_ioat(struct pci_dev *pdev)
216 {
217 switch (pdev->device) {
218 case PCI_DEVICE_ID_INTEL_IOAT_BWD0:
219 case PCI_DEVICE_ID_INTEL_IOAT_BWD1:
220 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
221 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
222 return true;
223 default:
224 return false;
225 }
226 }
227
228 static bool is_bwd_noraid(struct pci_dev *pdev)
229 {
230 switch (pdev->device) {
231 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
232 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
233 return true;
234 default:
235 return false;
236 }
237
238 }
239
240 static void pq16_set_src(struct ioat_raw_descriptor *desc[3],
241 dma_addr_t addr, u32 offset, u8 coef, unsigned idx)
242 {
243 struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *)desc[0];
244 struct ioat_pq16a_descriptor *pq16 =
245 (struct ioat_pq16a_descriptor *)desc[1];
246 struct ioat_raw_descriptor *raw = desc[pq16_idx_to_desc[idx]];
247
248 raw->field[pq16_idx_to_field[idx]] = addr + offset;
249
250 if (idx < 8)
251 pq->coef[idx] = coef;
252 else
253 pq16->coef[idx - 8] = coef;
254 }
255
256 static struct ioat_sed_ent *
257 ioat3_alloc_sed(struct ioatdma_device *device, unsigned int hw_pool)
258 {
259 struct ioat_sed_ent *sed;
260 gfp_t flags = __GFP_ZERO | GFP_ATOMIC;
261
262 sed = kmem_cache_alloc(device->sed_pool, flags);
263 if (!sed)
264 return NULL;
265
266 sed->hw_pool = hw_pool;
267 sed->hw = dma_pool_alloc(device->sed_hw_pool[hw_pool],
268 flags, &sed->dma);
269 if (!sed->hw) {
270 kmem_cache_free(device->sed_pool, sed);
271 return NULL;
272 }
273
274 return sed;
275 }
276
277 static void ioat3_free_sed(struct ioatdma_device *device, struct ioat_sed_ent *sed)
278 {
279 if (!sed)
280 return;
281
282 dma_pool_free(device->sed_hw_pool[sed->hw_pool], sed->hw, sed->dma);
283 kmem_cache_free(device->sed_pool, sed);
284 }
285
286 static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat,
287 struct ioat_ring_ent *desc, int idx)
288 {
289 struct ioat_chan_common *chan = &ioat->base;
290 struct pci_dev *pdev = chan->device->pdev;
291 size_t len = desc->len;
292 size_t offset = len - desc->hw->size;
293 struct dma_async_tx_descriptor *tx = &desc->txd;
294 enum dma_ctrl_flags flags = tx->flags;
295
296 switch (desc->hw->ctl_f.op) {
297 case IOAT_OP_COPY:
298 if (!desc->hw->ctl_f.null) /* skip 'interrupt' ops */
299 ioat_dma_unmap(chan, flags, len, desc->hw);
300 break;
301 case IOAT_OP_XOR_VAL:
302 case IOAT_OP_XOR: {
303 struct ioat_xor_descriptor *xor = desc->xor;
304 struct ioat_ring_ent *ext;
305 struct ioat_xor_ext_descriptor *xor_ex = NULL;
306 int src_cnt = src_cnt_to_sw(xor->ctl_f.src_cnt);
307 struct ioat_raw_descriptor *descs[2];
308 int i;
309
310 if (src_cnt > 5) {
311 ext = ioat2_get_ring_ent(ioat, idx + 1);
312 xor_ex = ext->xor_ex;
313 }
314
315 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
316 descs[0] = (struct ioat_raw_descriptor *) xor;
317 descs[1] = (struct ioat_raw_descriptor *) xor_ex;
318 for (i = 0; i < src_cnt; i++) {
319 dma_addr_t src = xor_get_src(descs, i);
320
321 ioat_unmap(pdev, src - offset, len,
322 PCI_DMA_TODEVICE, flags, 0);
323 }
324
325 /* dest is a source in xor validate operations */
326 if (xor->ctl_f.op == IOAT_OP_XOR_VAL) {
327 ioat_unmap(pdev, xor->dst_addr - offset, len,
328 PCI_DMA_TODEVICE, flags, 1);
329 break;
330 }
331 }
332
333 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
334 ioat_unmap(pdev, xor->dst_addr - offset, len,
335 PCI_DMA_FROMDEVICE, flags, 1);
336 break;
337 }
338 case IOAT_OP_PQ_VAL:
339 case IOAT_OP_PQ: {
340 struct ioat_pq_descriptor *pq = desc->pq;
341 struct ioat_ring_ent *ext;
342 struct ioat_pq_ext_descriptor *pq_ex = NULL;
343 int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt);
344 struct ioat_raw_descriptor *descs[2];
345 int i;
346
347 if (src_cnt > 3) {
348 ext = ioat2_get_ring_ent(ioat, idx + 1);
349 pq_ex = ext->pq_ex;
350 }
351
352 /* in the 'continue' case don't unmap the dests as sources */
353 if (dmaf_p_disabled_continue(flags))
354 src_cnt--;
355 else if (dmaf_continue(flags))
356 src_cnt -= 3;
357
358 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
359 descs[0] = (struct ioat_raw_descriptor *) pq;
360 descs[1] = (struct ioat_raw_descriptor *) pq_ex;
361 for (i = 0; i < src_cnt; i++) {
362 dma_addr_t src = pq_get_src(descs, i);
363
364 ioat_unmap(pdev, src - offset, len,
365 PCI_DMA_TODEVICE, flags, 0);
366 }
367
368 /* the dests are sources in pq validate operations */
369 if (pq->ctl_f.op == IOAT_OP_XOR_VAL) {
370 if (!(flags & DMA_PREP_PQ_DISABLE_P))
371 ioat_unmap(pdev, pq->p_addr - offset,
372 len, PCI_DMA_TODEVICE, flags, 0);
373 if (!(flags & DMA_PREP_PQ_DISABLE_Q))
374 ioat_unmap(pdev, pq->q_addr - offset,
375 len, PCI_DMA_TODEVICE, flags, 0);
376 break;
377 }
378 }
379
380 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
381 if (!(flags & DMA_PREP_PQ_DISABLE_P))
382 ioat_unmap(pdev, pq->p_addr - offset, len,
383 PCI_DMA_BIDIRECTIONAL, flags, 1);
384 if (!(flags & DMA_PREP_PQ_DISABLE_Q))
385 ioat_unmap(pdev, pq->q_addr - offset, len,
386 PCI_DMA_BIDIRECTIONAL, flags, 1);
387 }
388 break;
389 }
390 case IOAT_OP_PQ_16S:
391 case IOAT_OP_PQ_VAL_16S: {
392 struct ioat_pq_descriptor *pq = desc->pq;
393 int src_cnt = src16_cnt_to_sw(pq->ctl_f.src_cnt);
394 struct ioat_raw_descriptor *descs[4];
395 int i;
396
397 /* in the 'continue' case don't unmap the dests as sources */
398 if (dmaf_p_disabled_continue(flags))
399 src_cnt--;
400 else if (dmaf_continue(flags))
401 src_cnt -= 3;
402
403 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
404 descs[0] = (struct ioat_raw_descriptor *)pq;
405 descs[1] = (struct ioat_raw_descriptor *)(desc->sed->hw);
406 descs[2] = (struct ioat_raw_descriptor *)(&desc->sed->hw->b[0]);
407 for (i = 0; i < src_cnt; i++) {
408 dma_addr_t src = pq16_get_src(descs, i);
409
410 ioat_unmap(pdev, src - offset, len,
411 PCI_DMA_TODEVICE, flags, 0);
412 }
413
414 /* the dests are sources in pq validate operations */
415 if (pq->ctl_f.op == IOAT_OP_XOR_VAL) {
416 if (!(flags & DMA_PREP_PQ_DISABLE_P))
417 ioat_unmap(pdev, pq->p_addr - offset,
418 len, PCI_DMA_TODEVICE,
419 flags, 0);
420 if (!(flags & DMA_PREP_PQ_DISABLE_Q))
421 ioat_unmap(pdev, pq->q_addr - offset,
422 len, PCI_DMA_TODEVICE,
423 flags, 0);
424 break;
425 }
426 }
427
428 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
429 if (!(flags & DMA_PREP_PQ_DISABLE_P))
430 ioat_unmap(pdev, pq->p_addr - offset, len,
431 PCI_DMA_BIDIRECTIONAL, flags, 1);
432 if (!(flags & DMA_PREP_PQ_DISABLE_Q))
433 ioat_unmap(pdev, pq->q_addr - offset, len,
434 PCI_DMA_BIDIRECTIONAL, flags, 1);
435 }
436 break;
437 }
438 default:
439 dev_err(&pdev->dev, "%s: unknown op type: %#x\n",
440 __func__, desc->hw->ctl_f.op);
441 }
442 }
443
444 static bool desc_has_ext(struct ioat_ring_ent *desc)
445 {
446 struct ioat_dma_descriptor *hw = desc->hw;
447
448 if (hw->ctl_f.op == IOAT_OP_XOR ||
449 hw->ctl_f.op == IOAT_OP_XOR_VAL) {
450 struct ioat_xor_descriptor *xor = desc->xor;
451
452 if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5)
453 return true;
454 } else if (hw->ctl_f.op == IOAT_OP_PQ ||
455 hw->ctl_f.op == IOAT_OP_PQ_VAL) {
456 struct ioat_pq_descriptor *pq = desc->pq;
457
458 if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3)
459 return true;
460 }
461
462 return false;
463 }
464
465 static u64 ioat3_get_current_completion(struct ioat_chan_common *chan)
466 {
467 u64 phys_complete;
468 u64 completion;
469
470 completion = *chan->completion;
471 phys_complete = ioat_chansts_to_addr(completion);
472
473 dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__,
474 (unsigned long long) phys_complete);
475
476 return phys_complete;
477 }
478
479 static bool ioat3_cleanup_preamble(struct ioat_chan_common *chan,
480 u64 *phys_complete)
481 {
482 *phys_complete = ioat3_get_current_completion(chan);
483 if (*phys_complete == chan->last_completion)
484 return false;
485
486 clear_bit(IOAT_COMPLETION_ACK, &chan->state);
487 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
488
489 return true;
490 }
491
492 static void
493 desc_get_errstat(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc)
494 {
495 struct ioat_dma_descriptor *hw = desc->hw;
496
497 switch (hw->ctl_f.op) {
498 case IOAT_OP_PQ_VAL:
499 case IOAT_OP_PQ_VAL_16S:
500 {
501 struct ioat_pq_descriptor *pq = desc->pq;
502
503 /* check if there's error written */
504 if (!pq->dwbes_f.wbes)
505 return;
506
507 /* need to set a chanerr var for checking to clear later */
508
509 if (pq->dwbes_f.p_val_err)
510 *desc->result |= SUM_CHECK_P_RESULT;
511
512 if (pq->dwbes_f.q_val_err)
513 *desc->result |= SUM_CHECK_Q_RESULT;
514
515 return;
516 }
517 default:
518 return;
519 }
520 }
521
522 /**
523 * __cleanup - reclaim used descriptors
524 * @ioat: channel (ring) to clean
525 *
526 * The difference from the dma_v2.c __cleanup() is that this routine
527 * handles extended descriptors and dma-unmapping raid operations.
528 */
529 static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete)
530 {
531 struct ioat_chan_common *chan = &ioat->base;
532 struct ioatdma_device *device = chan->device;
533 struct ioat_ring_ent *desc;
534 bool seen_current = false;
535 int idx = ioat->tail, i;
536 u16 active;
537
538 dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
539 __func__, ioat->head, ioat->tail, ioat->issued);
540
541 /*
542 * At restart of the channel, the completion address and the
543 * channel status will be 0 due to starting a new chain. Since
544 * it's new chain and the first descriptor "fails", there is
545 * nothing to clean up. We do not want to reap the entire submitted
546 * chain due to this 0 address value and then BUG.
547 */
548 if (!phys_complete)
549 return;
550
551 active = ioat2_ring_active(ioat);
552 for (i = 0; i < active && !seen_current; i++) {
553 struct dma_async_tx_descriptor *tx;
554
555 smp_read_barrier_depends();
556 prefetch(ioat2_get_ring_ent(ioat, idx + i + 1));
557 desc = ioat2_get_ring_ent(ioat, idx + i);
558 dump_desc_dbg(ioat, desc);
559
560 /* set err stat if we are using dwbes */
561 if (device->cap & IOAT_CAP_DWBES)
562 desc_get_errstat(ioat, desc);
563
564 tx = &desc->txd;
565 if (tx->cookie) {
566 dma_cookie_complete(tx);
567 ioat3_dma_unmap(ioat, desc, idx + i);
568 if (tx->callback) {
569 tx->callback(tx->callback_param);
570 tx->callback = NULL;
571 }
572 }
573
574 if (tx->phys == phys_complete)
575 seen_current = true;
576
577 /* skip extended descriptors */
578 if (desc_has_ext(desc)) {
579 BUG_ON(i + 1 >= active);
580 i++;
581 }
582
583 /* cleanup super extended descriptors */
584 if (desc->sed) {
585 ioat3_free_sed(device, desc->sed);
586 desc->sed = NULL;
587 }
588 }
589 smp_mb(); /* finish all descriptor reads before incrementing tail */
590 ioat->tail = idx + i;
591 BUG_ON(active && !seen_current); /* no active descs have written a completion? */
592 chan->last_completion = phys_complete;
593
594 if (active - i == 0) {
595 dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
596 __func__);
597 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
598 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
599 }
600 /* 5 microsecond delay per pending descriptor */
601 writew(min((5 * (active - i)), IOAT_INTRDELAY_MASK),
602 chan->device->reg_base + IOAT_INTRDELAY_OFFSET);
603 }
604
605 static void ioat3_cleanup(struct ioat2_dma_chan *ioat)
606 {
607 struct ioat_chan_common *chan = &ioat->base;
608 u64 phys_complete;
609
610 spin_lock_bh(&chan->cleanup_lock);
611
612 if (ioat3_cleanup_preamble(chan, &phys_complete))
613 __cleanup(ioat, phys_complete);
614
615 if (is_ioat_halted(*chan->completion)) {
616 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
617
618 if (chanerr & IOAT_CHANERR_HANDLE_MASK) {
619 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
620 ioat3_eh(ioat);
621 }
622 }
623
624 spin_unlock_bh(&chan->cleanup_lock);
625 }
626
627 static void ioat3_cleanup_event(unsigned long data)
628 {
629 struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
630 struct ioat_chan_common *chan = &ioat->base;
631
632 ioat3_cleanup(ioat);
633 if (!test_bit(IOAT_RUN, &chan->state))
634 return;
635 writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
636 }
637
638 static void ioat3_restart_channel(struct ioat2_dma_chan *ioat)
639 {
640 struct ioat_chan_common *chan = &ioat->base;
641 u64 phys_complete;
642
643 ioat2_quiesce(chan, 0);
644 if (ioat3_cleanup_preamble(chan, &phys_complete))
645 __cleanup(ioat, phys_complete);
646
647 __ioat2_restart_chan(ioat);
648 }
649
650 static void ioat3_eh(struct ioat2_dma_chan *ioat)
651 {
652 struct ioat_chan_common *chan = &ioat->base;
653 struct pci_dev *pdev = to_pdev(chan);
654 struct ioat_dma_descriptor *hw;
655 u64 phys_complete;
656 struct ioat_ring_ent *desc;
657 u32 err_handled = 0;
658 u32 chanerr_int;
659 u32 chanerr;
660
661 /* cleanup so tail points to descriptor that caused the error */
662 if (ioat3_cleanup_preamble(chan, &phys_complete))
663 __cleanup(ioat, phys_complete);
664
665 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
666 pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr_int);
667
668 dev_dbg(to_dev(chan), "%s: error = %x:%x\n",
669 __func__, chanerr, chanerr_int);
670
671 desc = ioat2_get_ring_ent(ioat, ioat->tail);
672 hw = desc->hw;
673 dump_desc_dbg(ioat, desc);
674
675 switch (hw->ctl_f.op) {
676 case IOAT_OP_XOR_VAL:
677 if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) {
678 *desc->result |= SUM_CHECK_P_RESULT;
679 err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR;
680 }
681 break;
682 case IOAT_OP_PQ_VAL:
683 case IOAT_OP_PQ_VAL_16S:
684 if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) {
685 *desc->result |= SUM_CHECK_P_RESULT;
686 err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR;
687 }
688 if (chanerr & IOAT_CHANERR_XOR_Q_ERR) {
689 *desc->result |= SUM_CHECK_Q_RESULT;
690 err_handled |= IOAT_CHANERR_XOR_Q_ERR;
691 }
692 break;
693 }
694
695 /* fault on unhandled error or spurious halt */
696 if (chanerr ^ err_handled || chanerr == 0) {
697 dev_err(to_dev(chan), "%s: fatal error (%x:%x)\n",
698 __func__, chanerr, err_handled);
699 BUG();
700 }
701
702 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
703 pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr_int);
704
705 /* mark faulting descriptor as complete */
706 *chan->completion = desc->txd.phys;
707
708 spin_lock_bh(&ioat->prep_lock);
709 ioat3_restart_channel(ioat);
710 spin_unlock_bh(&ioat->prep_lock);
711 }
712
713 static void check_active(struct ioat2_dma_chan *ioat)
714 {
715 struct ioat_chan_common *chan = &ioat->base;
716
717 if (ioat2_ring_active(ioat)) {
718 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
719 return;
720 }
721
722 if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &chan->state))
723 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
724 else if (ioat->alloc_order > ioat_get_alloc_order()) {
725 /* if the ring is idle, empty, and oversized try to step
726 * down the size
727 */
728 reshape_ring(ioat, ioat->alloc_order - 1);
729
730 /* keep shrinking until we get back to our minimum
731 * default size
732 */
733 if (ioat->alloc_order > ioat_get_alloc_order())
734 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
735 }
736
737 }
738
739 static void ioat3_timer_event(unsigned long data)
740 {
741 struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
742 struct ioat_chan_common *chan = &ioat->base;
743 dma_addr_t phys_complete;
744 u64 status;
745
746 status = ioat_chansts(chan);
747
748 /* when halted due to errors check for channel
749 * programming errors before advancing the completion state
750 */
751 if (is_ioat_halted(status)) {
752 u32 chanerr;
753
754 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
755 dev_err(to_dev(chan), "%s: Channel halted (%x)\n",
756 __func__, chanerr);
757 if (test_bit(IOAT_RUN, &chan->state))
758 BUG_ON(is_ioat_bug(chanerr));
759 else /* we never got off the ground */
760 return;
761 }
762
763 /* if we haven't made progress and we have already
764 * acknowledged a pending completion once, then be more
765 * forceful with a restart
766 */
767 spin_lock_bh(&chan->cleanup_lock);
768 if (ioat_cleanup_preamble(chan, &phys_complete))
769 __cleanup(ioat, phys_complete);
770 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) {
771 spin_lock_bh(&ioat->prep_lock);
772 ioat3_restart_channel(ioat);
773 spin_unlock_bh(&ioat->prep_lock);
774 spin_unlock_bh(&chan->cleanup_lock);
775 return;
776 } else {
777 set_bit(IOAT_COMPLETION_ACK, &chan->state);
778 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
779 }
780
781
782 if (ioat2_ring_active(ioat))
783 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
784 else {
785 spin_lock_bh(&ioat->prep_lock);
786 check_active(ioat);
787 spin_unlock_bh(&ioat->prep_lock);
788 }
789 spin_unlock_bh(&chan->cleanup_lock);
790 }
791
792 static enum dma_status
793 ioat3_tx_status(struct dma_chan *c, dma_cookie_t cookie,
794 struct dma_tx_state *txstate)
795 {
796 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
797 enum dma_status ret;
798
799 ret = dma_cookie_status(c, cookie, txstate);
800 if (ret == DMA_SUCCESS)
801 return ret;
802
803 ioat3_cleanup(ioat);
804
805 return dma_cookie_status(c, cookie, txstate);
806 }
807
808 static struct dma_async_tx_descriptor *
809 __ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result,
810 dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt,
811 size_t len, unsigned long flags)
812 {
813 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
814 struct ioat_ring_ent *compl_desc;
815 struct ioat_ring_ent *desc;
816 struct ioat_ring_ent *ext;
817 size_t total_len = len;
818 struct ioat_xor_descriptor *xor;
819 struct ioat_xor_ext_descriptor *xor_ex = NULL;
820 struct ioat_dma_descriptor *hw;
821 int num_descs, with_ext, idx, i;
822 u32 offset = 0;
823 u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR;
824
825 BUG_ON(src_cnt < 2);
826
827 num_descs = ioat2_xferlen_to_descs(ioat, len);
828 /* we need 2x the number of descriptors to cover greater than 5
829 * sources
830 */
831 if (src_cnt > 5) {
832 with_ext = 1;
833 num_descs *= 2;
834 } else
835 with_ext = 0;
836
837 /* completion writes from the raid engine may pass completion
838 * writes from the legacy engine, so we need one extra null
839 * (legacy) descriptor to ensure all completion writes arrive in
840 * order.
841 */
842 if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs+1) == 0)
843 idx = ioat->head;
844 else
845 return NULL;
846 i = 0;
847 do {
848 struct ioat_raw_descriptor *descs[2];
849 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
850 int s;
851
852 desc = ioat2_get_ring_ent(ioat, idx + i);
853 xor = desc->xor;
854
855 /* save a branch by unconditionally retrieving the
856 * extended descriptor xor_set_src() knows to not write
857 * to it in the single descriptor case
858 */
859 ext = ioat2_get_ring_ent(ioat, idx + i + 1);
860 xor_ex = ext->xor_ex;
861
862 descs[0] = (struct ioat_raw_descriptor *) xor;
863 descs[1] = (struct ioat_raw_descriptor *) xor_ex;
864 for (s = 0; s < src_cnt; s++)
865 xor_set_src(descs, src[s], offset, s);
866 xor->size = xfer_size;
867 xor->dst_addr = dest + offset;
868 xor->ctl = 0;
869 xor->ctl_f.op = op;
870 xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt);
871
872 len -= xfer_size;
873 offset += xfer_size;
874 dump_desc_dbg(ioat, desc);
875 } while ((i += 1 + with_ext) < num_descs);
876
877 /* last xor descriptor carries the unmap parameters and fence bit */
878 desc->txd.flags = flags;
879 desc->len = total_len;
880 if (result)
881 desc->result = result;
882 xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
883
884 /* completion descriptor carries interrupt bit */
885 compl_desc = ioat2_get_ring_ent(ioat, idx + i);
886 compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT;
887 hw = compl_desc->hw;
888 hw->ctl = 0;
889 hw->ctl_f.null = 1;
890 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
891 hw->ctl_f.compl_write = 1;
892 hw->size = NULL_DESC_BUFFER_SIZE;
893 dump_desc_dbg(ioat, compl_desc);
894
895 /* we leave the channel locked to ensure in order submission */
896 return &compl_desc->txd;
897 }
898
899 static struct dma_async_tx_descriptor *
900 ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
901 unsigned int src_cnt, size_t len, unsigned long flags)
902 {
903 return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags);
904 }
905
906 struct dma_async_tx_descriptor *
907 ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
908 unsigned int src_cnt, size_t len,
909 enum sum_check_flags *result, unsigned long flags)
910 {
911 /* the cleanup routine only sets bits on validate failure, it
912 * does not clear bits on validate success... so clear it here
913 */
914 *result = 0;
915
916 return __ioat3_prep_xor_lock(chan, result, src[0], &src[1],
917 src_cnt - 1, len, flags);
918 }
919
920 static void
921 dump_pq_desc_dbg(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, struct ioat_ring_ent *ext)
922 {
923 struct device *dev = to_dev(&ioat->base);
924 struct ioat_pq_descriptor *pq = desc->pq;
925 struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL;
926 struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex };
927 int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt);
928 int i;
929
930 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x"
931 " sz: %#10.8x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s'"
932 " src_cnt: %d)\n",
933 desc_id(desc), (unsigned long long) desc->txd.phys,
934 (unsigned long long) (pq_ex ? pq_ex->next : pq->next),
935 desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, pq->ctl_f.int_en,
936 pq->ctl_f.compl_write,
937 pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q",
938 pq->ctl_f.src_cnt);
939 for (i = 0; i < src_cnt; i++)
940 dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i,
941 (unsigned long long) pq_get_src(descs, i), pq->coef[i]);
942 dev_dbg(dev, "\tP: %#llx\n", pq->p_addr);
943 dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr);
944 dev_dbg(dev, "\tNEXT: %#llx\n", pq->next);
945 }
946
947 static void dump_pq16_desc_dbg(struct ioat2_dma_chan *ioat,
948 struct ioat_ring_ent *desc)
949 {
950 struct device *dev = to_dev(&ioat->base);
951 struct ioat_pq_descriptor *pq = desc->pq;
952 struct ioat_raw_descriptor *descs[] = { (void *)pq,
953 (void *)pq,
954 (void *)pq };
955 int src_cnt = src16_cnt_to_sw(pq->ctl_f.src_cnt);
956 int i;
957
958 if (desc->sed) {
959 descs[1] = (void *)desc->sed->hw;
960 descs[2] = (void *)desc->sed->hw + 64;
961 }
962
963 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x"
964 " sz: %#x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s'"
965 " src_cnt: %d)\n",
966 desc_id(desc), (unsigned long long) desc->txd.phys,
967 (unsigned long long) pq->next,
968 desc->txd.flags, pq->size, pq->ctl,
969 pq->ctl_f.op, pq->ctl_f.int_en,
970 pq->ctl_f.compl_write,
971 pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q",
972 pq->ctl_f.src_cnt);
973 for (i = 0; i < src_cnt; i++) {
974 dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i,
975 (unsigned long long) pq16_get_src(descs, i),
976 pq->coef[i]);
977 }
978 dev_dbg(dev, "\tP: %#llx\n", pq->p_addr);
979 dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr);
980 }
981
982 static struct dma_async_tx_descriptor *
983 __ioat3_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result,
984 const dma_addr_t *dst, const dma_addr_t *src,
985 unsigned int src_cnt, const unsigned char *scf,
986 size_t len, unsigned long flags)
987 {
988 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
989 struct ioat_chan_common *chan = &ioat->base;
990 struct ioatdma_device *device = chan->device;
991 struct ioat_ring_ent *compl_desc;
992 struct ioat_ring_ent *desc;
993 struct ioat_ring_ent *ext;
994 size_t total_len = len;
995 struct ioat_pq_descriptor *pq;
996 struct ioat_pq_ext_descriptor *pq_ex = NULL;
997 struct ioat_dma_descriptor *hw;
998 u32 offset = 0;
999 u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ;
1000 int i, s, idx, with_ext, num_descs;
1001 int cb32 = (device->version < IOAT_VER_3_3) ? 1 : 0;
1002
1003 dev_dbg(to_dev(chan), "%s\n", __func__);
1004 /* the engine requires at least two sources (we provide
1005 * at least 1 implied source in the DMA_PREP_CONTINUE case)
1006 */
1007 BUG_ON(src_cnt + dmaf_continue(flags) < 2);
1008
1009 num_descs = ioat2_xferlen_to_descs(ioat, len);
1010 /* we need 2x the number of descriptors to cover greater than 3
1011 * sources (we need 1 extra source in the q-only continuation
1012 * case and 3 extra sources in the p+q continuation case.
1013 */
1014 if (src_cnt + dmaf_p_disabled_continue(flags) > 3 ||
1015 (dmaf_continue(flags) && !dmaf_p_disabled_continue(flags))) {
1016 with_ext = 1;
1017 num_descs *= 2;
1018 } else
1019 with_ext = 0;
1020
1021 /* completion writes from the raid engine may pass completion
1022 * writes from the legacy engine, so we need one extra null
1023 * (legacy) descriptor to ensure all completion writes arrive in
1024 * order.
1025 */
1026 if (likely(num_descs) &&
1027 ioat2_check_space_lock(ioat, num_descs + cb32) == 0)
1028 idx = ioat->head;
1029 else
1030 return NULL;
1031 i = 0;
1032 do {
1033 struct ioat_raw_descriptor *descs[2];
1034 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
1035
1036 desc = ioat2_get_ring_ent(ioat, idx + i);
1037 pq = desc->pq;
1038
1039 /* save a branch by unconditionally retrieving the
1040 * extended descriptor pq_set_src() knows to not write
1041 * to it in the single descriptor case
1042 */
1043 ext = ioat2_get_ring_ent(ioat, idx + i + with_ext);
1044 pq_ex = ext->pq_ex;
1045
1046 descs[0] = (struct ioat_raw_descriptor *) pq;
1047 descs[1] = (struct ioat_raw_descriptor *) pq_ex;
1048
1049 for (s = 0; s < src_cnt; s++)
1050 pq_set_src(descs, src[s], offset, scf[s], s);
1051
1052 /* see the comment for dma_maxpq in include/linux/dmaengine.h */
1053 if (dmaf_p_disabled_continue(flags))
1054 pq_set_src(descs, dst[1], offset, 1, s++);
1055 else if (dmaf_continue(flags)) {
1056 pq_set_src(descs, dst[0], offset, 0, s++);
1057 pq_set_src(descs, dst[1], offset, 1, s++);
1058 pq_set_src(descs, dst[1], offset, 0, s++);
1059 }
1060 pq->size = xfer_size;
1061 pq->p_addr = dst[0] + offset;
1062 pq->q_addr = dst[1] + offset;
1063 pq->ctl = 0;
1064 pq->ctl_f.op = op;
1065 /* we turn on descriptor write back error status */
1066 if (device->cap & IOAT_CAP_DWBES)
1067 pq->ctl_f.wb_en = result ? 1 : 0;
1068 pq->ctl_f.src_cnt = src_cnt_to_hw(s);
1069 pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P);
1070 pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q);
1071
1072 len -= xfer_size;
1073 offset += xfer_size;
1074 } while ((i += 1 + with_ext) < num_descs);
1075
1076 /* last pq descriptor carries the unmap parameters and fence bit */
1077 desc->txd.flags = flags;
1078 desc->len = total_len;
1079 if (result)
1080 desc->result = result;
1081 pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
1082 dump_pq_desc_dbg(ioat, desc, ext);
1083
1084 if (!cb32) {
1085 pq->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
1086 pq->ctl_f.compl_write = 1;
1087 compl_desc = desc;
1088 } else {
1089 /* completion descriptor carries interrupt bit */
1090 compl_desc = ioat2_get_ring_ent(ioat, idx + i);
1091 compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT;
1092 hw = compl_desc->hw;
1093 hw->ctl = 0;
1094 hw->ctl_f.null = 1;
1095 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
1096 hw->ctl_f.compl_write = 1;
1097 hw->size = NULL_DESC_BUFFER_SIZE;
1098 dump_desc_dbg(ioat, compl_desc);
1099 }
1100
1101
1102 /* we leave the channel locked to ensure in order submission */
1103 return &compl_desc->txd;
1104 }
1105
1106 static struct dma_async_tx_descriptor *
1107 __ioat3_prep_pq16_lock(struct dma_chan *c, enum sum_check_flags *result,
1108 const dma_addr_t *dst, const dma_addr_t *src,
1109 unsigned int src_cnt, const unsigned char *scf,
1110 size_t len, unsigned long flags)
1111 {
1112 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
1113 struct ioat_chan_common *chan = &ioat->base;
1114 struct ioatdma_device *device = chan->device;
1115 struct ioat_ring_ent *desc;
1116 size_t total_len = len;
1117 struct ioat_pq_descriptor *pq;
1118 u32 offset = 0;
1119 u8 op;
1120 int i, s, idx, num_descs;
1121
1122 /* this function is only called with 9-16 sources */
1123 op = result ? IOAT_OP_PQ_VAL_16S : IOAT_OP_PQ_16S;
1124
1125 dev_dbg(to_dev(chan), "%s\n", __func__);
1126
1127 num_descs = ioat2_xferlen_to_descs(ioat, len);
1128
1129 /*
1130 * 16 source pq is only available on cb3.3 and has no completion
1131 * write hw bug.
1132 */
1133 if (num_descs && ioat2_check_space_lock(ioat, num_descs) == 0)
1134 idx = ioat->head;
1135 else
1136 return NULL;
1137
1138 i = 0;
1139
1140 do {
1141 struct ioat_raw_descriptor *descs[4];
1142 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
1143
1144 desc = ioat2_get_ring_ent(ioat, idx + i);
1145 pq = desc->pq;
1146
1147 descs[0] = (struct ioat_raw_descriptor *) pq;
1148
1149 desc->sed = ioat3_alloc_sed(device, (src_cnt-2) >> 3);
1150 if (!desc->sed) {
1151 dev_err(to_dev(chan),
1152 "%s: no free sed entries\n", __func__);
1153 return NULL;
1154 }
1155
1156 pq->sed_addr = desc->sed->dma;
1157 desc->sed->parent = desc;
1158
1159 descs[1] = (struct ioat_raw_descriptor *)desc->sed->hw;
1160 descs[2] = (void *)descs[1] + 64;
1161
1162 for (s = 0; s < src_cnt; s++)
1163 pq16_set_src(descs, src[s], offset, scf[s], s);
1164
1165 /* see the comment for dma_maxpq in include/linux/dmaengine.h */
1166 if (dmaf_p_disabled_continue(flags))
1167 pq16_set_src(descs, dst[1], offset, 1, s++);
1168 else if (dmaf_continue(flags)) {
1169 pq16_set_src(descs, dst[0], offset, 0, s++);
1170 pq16_set_src(descs, dst[1], offset, 1, s++);
1171 pq16_set_src(descs, dst[1], offset, 0, s++);
1172 }
1173
1174 pq->size = xfer_size;
1175 pq->p_addr = dst[0] + offset;
1176 pq->q_addr = dst[1] + offset;
1177 pq->ctl = 0;
1178 pq->ctl_f.op = op;
1179 pq->ctl_f.src_cnt = src16_cnt_to_hw(s);
1180 /* we turn on descriptor write back error status */
1181 if (device->cap & IOAT_CAP_DWBES)
1182 pq->ctl_f.wb_en = result ? 1 : 0;
1183 pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P);
1184 pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q);
1185
1186 len -= xfer_size;
1187 offset += xfer_size;
1188 } while (++i < num_descs);
1189
1190 /* last pq descriptor carries the unmap parameters and fence bit */
1191 desc->txd.flags = flags;
1192 desc->len = total_len;
1193 if (result)
1194 desc->result = result;
1195 pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
1196
1197 /* with cb3.3 we should be able to do completion w/o a null desc */
1198 pq->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
1199 pq->ctl_f.compl_write = 1;
1200
1201 dump_pq16_desc_dbg(ioat, desc);
1202
1203 /* we leave the channel locked to ensure in order submission */
1204 return &desc->txd;
1205 }
1206
1207 static int src_cnt_flags(unsigned int src_cnt, unsigned long flags)
1208 {
1209 if (dmaf_p_disabled_continue(flags))
1210 return src_cnt + 1;
1211 else if (dmaf_continue(flags))
1212 return src_cnt + 3;
1213 else
1214 return src_cnt;
1215 }
1216
1217 static struct dma_async_tx_descriptor *
1218 ioat3_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
1219 unsigned int src_cnt, const unsigned char *scf, size_t len,
1220 unsigned long flags)
1221 {
1222 /* specify valid address for disabled result */
1223 if (flags & DMA_PREP_PQ_DISABLE_P)
1224 dst[0] = dst[1];
1225 if (flags & DMA_PREP_PQ_DISABLE_Q)
1226 dst[1] = dst[0];
1227
1228 /* handle the single source multiply case from the raid6
1229 * recovery path
1230 */
1231 if ((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1) {
1232 dma_addr_t single_source[2];
1233 unsigned char single_source_coef[2];
1234
1235 BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q);
1236 single_source[0] = src[0];
1237 single_source[1] = src[0];
1238 single_source_coef[0] = scf[0];
1239 single_source_coef[1] = 0;
1240
1241 return src_cnt_flags(src_cnt, flags) > 8 ?
1242 __ioat3_prep_pq16_lock(chan, NULL, dst, single_source,
1243 2, single_source_coef, len,
1244 flags) :
1245 __ioat3_prep_pq_lock(chan, NULL, dst, single_source, 2,
1246 single_source_coef, len, flags);
1247
1248 } else {
1249 return src_cnt_flags(src_cnt, flags) > 8 ?
1250 __ioat3_prep_pq16_lock(chan, NULL, dst, src, src_cnt,
1251 scf, len, flags) :
1252 __ioat3_prep_pq_lock(chan, NULL, dst, src, src_cnt,
1253 scf, len, flags);
1254 }
1255 }
1256
1257 struct dma_async_tx_descriptor *
1258 ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
1259 unsigned int src_cnt, const unsigned char *scf, size_t len,
1260 enum sum_check_flags *pqres, unsigned long flags)
1261 {
1262 /* specify valid address for disabled result */
1263 if (flags & DMA_PREP_PQ_DISABLE_P)
1264 pq[0] = pq[1];
1265 if (flags & DMA_PREP_PQ_DISABLE_Q)
1266 pq[1] = pq[0];
1267
1268 /* the cleanup routine only sets bits on validate failure, it
1269 * does not clear bits on validate success... so clear it here
1270 */
1271 *pqres = 0;
1272
1273 return src_cnt_flags(src_cnt, flags) > 8 ?
1274 __ioat3_prep_pq16_lock(chan, pqres, pq, src, src_cnt, scf, len,
1275 flags) :
1276 __ioat3_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len,
1277 flags);
1278 }
1279
1280 static struct dma_async_tx_descriptor *
1281 ioat3_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
1282 unsigned int src_cnt, size_t len, unsigned long flags)
1283 {
1284 unsigned char scf[src_cnt];
1285 dma_addr_t pq[2];
1286
1287 memset(scf, 0, src_cnt);
1288 pq[0] = dst;
1289 flags |= DMA_PREP_PQ_DISABLE_Q;
1290 pq[1] = dst; /* specify valid address for disabled result */
1291
1292 return src_cnt_flags(src_cnt, flags) > 8 ?
1293 __ioat3_prep_pq16_lock(chan, NULL, pq, src, src_cnt, scf, len,
1294 flags) :
1295 __ioat3_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len,
1296 flags);
1297 }
1298
1299 struct dma_async_tx_descriptor *
1300 ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src,
1301 unsigned int src_cnt, size_t len,
1302 enum sum_check_flags *result, unsigned long flags)
1303 {
1304 unsigned char scf[src_cnt];
1305 dma_addr_t pq[2];
1306
1307 /* the cleanup routine only sets bits on validate failure, it
1308 * does not clear bits on validate success... so clear it here
1309 */
1310 *result = 0;
1311
1312 memset(scf, 0, src_cnt);
1313 pq[0] = src[0];
1314 flags |= DMA_PREP_PQ_DISABLE_Q;
1315 pq[1] = pq[0]; /* specify valid address for disabled result */
1316
1317 return src_cnt_flags(src_cnt, flags) > 8 ?
1318 __ioat3_prep_pq16_lock(chan, result, pq, &src[1], src_cnt - 1,
1319 scf, len, flags) :
1320 __ioat3_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1,
1321 scf, len, flags);
1322 }
1323
1324 static struct dma_async_tx_descriptor *
1325 ioat3_prep_interrupt_lock(struct dma_chan *c, unsigned long flags)
1326 {
1327 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
1328 struct ioat_ring_ent *desc;
1329 struct ioat_dma_descriptor *hw;
1330
1331 if (ioat2_check_space_lock(ioat, 1) == 0)
1332 desc = ioat2_get_ring_ent(ioat, ioat->head);
1333 else
1334 return NULL;
1335
1336 hw = desc->hw;
1337 hw->ctl = 0;
1338 hw->ctl_f.null = 1;
1339 hw->ctl_f.int_en = 1;
1340 hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
1341 hw->ctl_f.compl_write = 1;
1342 hw->size = NULL_DESC_BUFFER_SIZE;
1343 hw->src_addr = 0;
1344 hw->dst_addr = 0;
1345
1346 desc->txd.flags = flags;
1347 desc->len = 1;
1348
1349 dump_desc_dbg(ioat, desc);
1350
1351 /* we leave the channel locked to ensure in order submission */
1352 return &desc->txd;
1353 }
1354
1355 static void ioat3_dma_test_callback(void *dma_async_param)
1356 {
1357 struct completion *cmp = dma_async_param;
1358
1359 complete(cmp);
1360 }
1361
1362 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
1363 static int ioat_xor_val_self_test(struct ioatdma_device *device)
1364 {
1365 int i, src_idx;
1366 struct page *dest;
1367 struct page *xor_srcs[IOAT_NUM_SRC_TEST];
1368 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1];
1369 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1];
1370 dma_addr_t dest_dma;
1371 struct dma_async_tx_descriptor *tx;
1372 struct dma_chan *dma_chan;
1373 dma_cookie_t cookie;
1374 u8 cmp_byte = 0;
1375 u32 cmp_word;
1376 u32 xor_val_result;
1377 int err = 0;
1378 struct completion cmp;
1379 unsigned long tmo;
1380 struct device *dev = &device->pdev->dev;
1381 struct dma_device *dma = &device->common;
1382 u8 op = 0;
1383
1384 dev_dbg(dev, "%s\n", __func__);
1385
1386 if (!dma_has_cap(DMA_XOR, dma->cap_mask))
1387 return 0;
1388
1389 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
1390 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
1391 if (!xor_srcs[src_idx]) {
1392 while (src_idx--)
1393 __free_page(xor_srcs[src_idx]);
1394 return -ENOMEM;
1395 }
1396 }
1397
1398 dest = alloc_page(GFP_KERNEL);
1399 if (!dest) {
1400 while (src_idx--)
1401 __free_page(xor_srcs[src_idx]);
1402 return -ENOMEM;
1403 }
1404
1405 /* Fill in src buffers */
1406 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
1407 u8 *ptr = page_address(xor_srcs[src_idx]);
1408 for (i = 0; i < PAGE_SIZE; i++)
1409 ptr[i] = (1 << src_idx);
1410 }
1411
1412 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++)
1413 cmp_byte ^= (u8) (1 << src_idx);
1414
1415 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
1416 (cmp_byte << 8) | cmp_byte;
1417
1418 memset(page_address(dest), 0, PAGE_SIZE);
1419
1420 dma_chan = container_of(dma->channels.next, struct dma_chan,
1421 device_node);
1422 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
1423 err = -ENODEV;
1424 goto out;
1425 }
1426
1427 /* test xor */
1428 op = IOAT_OP_XOR;
1429
1430 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE);
1431 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
1432 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE,
1433 DMA_TO_DEVICE);
1434 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
1435 IOAT_NUM_SRC_TEST, PAGE_SIZE,
1436 DMA_PREP_INTERRUPT |
1437 DMA_COMPL_SKIP_SRC_UNMAP |
1438 DMA_COMPL_SKIP_DEST_UNMAP);
1439
1440 if (!tx) {
1441 dev_err(dev, "Self-test xor prep failed\n");
1442 err = -ENODEV;
1443 goto dma_unmap;
1444 }
1445
1446 async_tx_ack(tx);
1447 init_completion(&cmp);
1448 tx->callback = ioat3_dma_test_callback;
1449 tx->callback_param = &cmp;
1450 cookie = tx->tx_submit(tx);
1451 if (cookie < 0) {
1452 dev_err(dev, "Self-test xor setup failed\n");
1453 err = -ENODEV;
1454 goto dma_unmap;
1455 }
1456 dma->device_issue_pending(dma_chan);
1457
1458 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1459
1460 if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
1461 dev_err(dev, "Self-test xor timed out\n");
1462 err = -ENODEV;
1463 goto dma_unmap;
1464 }
1465
1466 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
1467 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
1468 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
1469
1470 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
1471 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
1472 u32 *ptr = page_address(dest);
1473 if (ptr[i] != cmp_word) {
1474 dev_err(dev, "Self-test xor failed compare\n");
1475 err = -ENODEV;
1476 goto free_resources;
1477 }
1478 }
1479 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
1480
1481 /* skip validate if the capability is not present */
1482 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
1483 goto free_resources;
1484
1485 op = IOAT_OP_XOR_VAL;
1486
1487 /* validate the sources with the destintation page */
1488 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
1489 xor_val_srcs[i] = xor_srcs[i];
1490 xor_val_srcs[i] = dest;
1491
1492 xor_val_result = 1;
1493
1494 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1495 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
1496 DMA_TO_DEVICE);
1497 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
1498 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
1499 &xor_val_result, DMA_PREP_INTERRUPT |
1500 DMA_COMPL_SKIP_SRC_UNMAP |
1501 DMA_COMPL_SKIP_DEST_UNMAP);
1502 if (!tx) {
1503 dev_err(dev, "Self-test zero prep failed\n");
1504 err = -ENODEV;
1505 goto dma_unmap;
1506 }
1507
1508 async_tx_ack(tx);
1509 init_completion(&cmp);
1510 tx->callback = ioat3_dma_test_callback;
1511 tx->callback_param = &cmp;
1512 cookie = tx->tx_submit(tx);
1513 if (cookie < 0) {
1514 dev_err(dev, "Self-test zero setup failed\n");
1515 err = -ENODEV;
1516 goto dma_unmap;
1517 }
1518 dma->device_issue_pending(dma_chan);
1519
1520 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1521
1522 if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
1523 dev_err(dev, "Self-test validate timed out\n");
1524 err = -ENODEV;
1525 goto dma_unmap;
1526 }
1527
1528 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1529 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
1530
1531 if (xor_val_result != 0) {
1532 dev_err(dev, "Self-test validate failed compare\n");
1533 err = -ENODEV;
1534 goto free_resources;
1535 }
1536
1537 memset(page_address(dest), 0, PAGE_SIZE);
1538
1539 /* test for non-zero parity sum */
1540 op = IOAT_OP_XOR_VAL;
1541
1542 xor_val_result = 0;
1543 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1544 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
1545 DMA_TO_DEVICE);
1546 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
1547 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
1548 &xor_val_result, DMA_PREP_INTERRUPT |
1549 DMA_COMPL_SKIP_SRC_UNMAP |
1550 DMA_COMPL_SKIP_DEST_UNMAP);
1551 if (!tx) {
1552 dev_err(dev, "Self-test 2nd zero prep failed\n");
1553 err = -ENODEV;
1554 goto dma_unmap;
1555 }
1556
1557 async_tx_ack(tx);
1558 init_completion(&cmp);
1559 tx->callback = ioat3_dma_test_callback;
1560 tx->callback_param = &cmp;
1561 cookie = tx->tx_submit(tx);
1562 if (cookie < 0) {
1563 dev_err(dev, "Self-test 2nd zero setup failed\n");
1564 err = -ENODEV;
1565 goto dma_unmap;
1566 }
1567 dma->device_issue_pending(dma_chan);
1568
1569 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1570
1571 if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
1572 dev_err(dev, "Self-test 2nd validate timed out\n");
1573 err = -ENODEV;
1574 goto dma_unmap;
1575 }
1576
1577 if (xor_val_result != SUM_CHECK_P_RESULT) {
1578 dev_err(dev, "Self-test validate failed compare\n");
1579 err = -ENODEV;
1580 goto dma_unmap;
1581 }
1582
1583 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1584 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
1585
1586 goto free_resources;
1587 dma_unmap:
1588 if (op == IOAT_OP_XOR) {
1589 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
1590 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
1591 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1592 DMA_TO_DEVICE);
1593 } else if (op == IOAT_OP_XOR_VAL) {
1594 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1595 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1596 DMA_TO_DEVICE);
1597 }
1598 free_resources:
1599 dma->device_free_chan_resources(dma_chan);
1600 out:
1601 src_idx = IOAT_NUM_SRC_TEST;
1602 while (src_idx--)
1603 __free_page(xor_srcs[src_idx]);
1604 __free_page(dest);
1605 return err;
1606 }
1607
1608 static int ioat3_dma_self_test(struct ioatdma_device *device)
1609 {
1610 int rc = ioat_dma_self_test(device);
1611
1612 if (rc)
1613 return rc;
1614
1615 rc = ioat_xor_val_self_test(device);
1616 if (rc)
1617 return rc;
1618
1619 return 0;
1620 }
1621
1622 static int ioat3_irq_reinit(struct ioatdma_device *device)
1623 {
1624 int msixcnt = device->common.chancnt;
1625 struct pci_dev *pdev = device->pdev;
1626 int i;
1627 struct msix_entry *msix;
1628 struct ioat_chan_common *chan;
1629 int err = 0;
1630
1631 switch (device->irq_mode) {
1632 case IOAT_MSIX:
1633
1634 for (i = 0; i < msixcnt; i++) {
1635 msix = &device->msix_entries[i];
1636 chan = ioat_chan_by_index(device, i);
1637 devm_free_irq(&pdev->dev, msix->vector, chan);
1638 }
1639
1640 pci_disable_msix(pdev);
1641 break;
1642
1643 case IOAT_MSIX_SINGLE:
1644 msix = &device->msix_entries[0];
1645 chan = ioat_chan_by_index(device, 0);
1646 devm_free_irq(&pdev->dev, msix->vector, chan);
1647 pci_disable_msix(pdev);
1648 break;
1649
1650 case IOAT_MSI:
1651 chan = ioat_chan_by_index(device, 0);
1652 devm_free_irq(&pdev->dev, pdev->irq, chan);
1653 pci_disable_msi(pdev);
1654 break;
1655
1656 case IOAT_INTX:
1657 chan = ioat_chan_by_index(device, 0);
1658 devm_free_irq(&pdev->dev, pdev->irq, chan);
1659 break;
1660
1661 default:
1662 return 0;
1663 }
1664
1665 device->irq_mode = IOAT_NOIRQ;
1666
1667 err = ioat_dma_setup_interrupts(device);
1668
1669 return err;
1670 }
1671
1672 static int ioat3_reset_hw(struct ioat_chan_common *chan)
1673 {
1674 /* throw away whatever the channel was doing and get it
1675 * initialized, with ioat3 specific workarounds
1676 */
1677 struct ioatdma_device *device = chan->device;
1678 struct pci_dev *pdev = device->pdev;
1679 u32 chanerr;
1680 u16 dev_id;
1681 int err;
1682
1683 ioat2_quiesce(chan, msecs_to_jiffies(100));
1684
1685 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
1686 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
1687
1688 if (device->version < IOAT_VER_3_3) {
1689 /* clear any pending errors */
1690 err = pci_read_config_dword(pdev,
1691 IOAT_PCI_CHANERR_INT_OFFSET, &chanerr);
1692 if (err) {
1693 dev_err(&pdev->dev,
1694 "channel error register unreachable\n");
1695 return err;
1696 }
1697 pci_write_config_dword(pdev,
1698 IOAT_PCI_CHANERR_INT_OFFSET, chanerr);
1699
1700 /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
1701 * (workaround for spurious config parity error after restart)
1702 */
1703 pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id);
1704 if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) {
1705 pci_write_config_dword(pdev,
1706 IOAT_PCI_DMAUNCERRSTS_OFFSET,
1707 0x10);
1708 }
1709 }
1710
1711 err = ioat2_reset_sync(chan, msecs_to_jiffies(200));
1712 if (err) {
1713 dev_err(&pdev->dev, "Failed to reset!\n");
1714 return err;
1715 }
1716
1717 if (device->irq_mode != IOAT_NOIRQ && is_bwd_ioat(pdev))
1718 err = ioat3_irq_reinit(device);
1719
1720 return err;
1721 }
1722
1723 static void ioat3_intr_quirk(struct ioatdma_device *device)
1724 {
1725 struct dma_device *dma;
1726 struct dma_chan *c;
1727 struct ioat_chan_common *chan;
1728 u32 errmask;
1729
1730 dma = &device->common;
1731
1732 /*
1733 * if we have descriptor write back error status, we mask the
1734 * error interrupts
1735 */
1736 if (device->cap & IOAT_CAP_DWBES) {
1737 list_for_each_entry(c, &dma->channels, device_node) {
1738 chan = to_chan_common(c);
1739 errmask = readl(chan->reg_base +
1740 IOAT_CHANERR_MASK_OFFSET);
1741 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR |
1742 IOAT_CHANERR_XOR_Q_ERR;
1743 writel(errmask, chan->reg_base +
1744 IOAT_CHANERR_MASK_OFFSET);
1745 }
1746 }
1747 }
1748
1749 int ioat3_dma_probe(struct ioatdma_device *device, int dca)
1750 {
1751 struct pci_dev *pdev = device->pdev;
1752 int dca_en = system_has_dca_enabled(pdev);
1753 struct dma_device *dma;
1754 struct dma_chan *c;
1755 struct ioat_chan_common *chan;
1756 bool is_raid_device = false;
1757 int err;
1758
1759 device->enumerate_channels = ioat2_enumerate_channels;
1760 device->reset_hw = ioat3_reset_hw;
1761 device->self_test = ioat3_dma_self_test;
1762 device->intr_quirk = ioat3_intr_quirk;
1763 dma = &device->common;
1764 dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
1765 dma->device_issue_pending = ioat2_issue_pending;
1766 dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
1767 dma->device_free_chan_resources = ioat2_free_chan_resources;
1768
1769 dma_cap_set(DMA_INTERRUPT, dma->cap_mask);
1770 dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock;
1771
1772 device->cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET);
1773
1774 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev))
1775 device->cap &= ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS);
1776
1777 /* dca is incompatible with raid operations */
1778 if (dca_en && (device->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ)))
1779 device->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ);
1780
1781 if (device->cap & IOAT_CAP_XOR) {
1782 is_raid_device = true;
1783 dma->max_xor = 8;
1784
1785 dma_cap_set(DMA_XOR, dma->cap_mask);
1786 dma->device_prep_dma_xor = ioat3_prep_xor;
1787
1788 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1789 dma->device_prep_dma_xor_val = ioat3_prep_xor_val;
1790 }
1791
1792 if (device->cap & IOAT_CAP_PQ) {
1793 is_raid_device = true;
1794
1795 dma->device_prep_dma_pq = ioat3_prep_pq;
1796 dma->device_prep_dma_pq_val = ioat3_prep_pq_val;
1797 dma_cap_set(DMA_PQ, dma->cap_mask);
1798 dma_cap_set(DMA_PQ_VAL, dma->cap_mask);
1799
1800 if (device->cap & IOAT_CAP_RAID16SS) {
1801 dma_set_maxpq(dma, 16, 0);
1802 } else {
1803 dma_set_maxpq(dma, 8, 0);
1804 }
1805
1806 if (!(device->cap & IOAT_CAP_XOR)) {
1807 dma->device_prep_dma_xor = ioat3_prep_pqxor;
1808 dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val;
1809 dma_cap_set(DMA_XOR, dma->cap_mask);
1810 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1811
1812 if (device->cap & IOAT_CAP_RAID16SS) {
1813 dma->max_xor = 16;
1814 } else {
1815 dma->max_xor = 8;
1816 }
1817 }
1818 }
1819
1820 dma->device_tx_status = ioat3_tx_status;
1821 device->cleanup_fn = ioat3_cleanup_event;
1822 device->timer_fn = ioat3_timer_event;
1823
1824 /* starting with CB3.3 super extended descriptors are supported */
1825 if (device->cap & IOAT_CAP_RAID16SS) {
1826 char pool_name[14];
1827 int i;
1828
1829 /* allocate sw descriptor pool for SED */
1830 device->sed_pool = kmem_cache_create("ioat_sed",
1831 sizeof(struct ioat_sed_ent), 0, 0, NULL);
1832 if (!device->sed_pool)
1833 return -ENOMEM;
1834
1835 for (i = 0; i < MAX_SED_POOLS; i++) {
1836 snprintf(pool_name, 14, "ioat_hw%d_sed", i);
1837
1838 /* allocate SED DMA pool */
1839 device->sed_hw_pool[i] = dma_pool_create(pool_name,
1840 &pdev->dev,
1841 SED_SIZE * (i + 1), 64, 0);
1842 if (!device->sed_hw_pool[i])
1843 goto sed_pool_cleanup;
1844
1845 }
1846 }
1847
1848 err = ioat_probe(device);
1849 if (err)
1850 return err;
1851 ioat_set_tcp_copy_break(262144);
1852
1853 list_for_each_entry(c, &dma->channels, device_node) {
1854 chan = to_chan_common(c);
1855 writel(IOAT_DMA_DCA_ANY_CPU,
1856 chan->reg_base + IOAT_DCACTRL_OFFSET);
1857 }
1858
1859 err = ioat_register(device);
1860 if (err)
1861 return err;
1862
1863 ioat_kobject_add(device, &ioat2_ktype);
1864
1865 if (dca)
1866 device->dca = ioat3_dca_init(pdev, device->reg_base);
1867
1868 return 0;
1869
1870 sed_pool_cleanup:
1871 if (device->sed_pool) {
1872 int i;
1873 kmem_cache_destroy(device->sed_pool);
1874
1875 for (i = 0; i < MAX_SED_POOLS; i++)
1876 if (device->sed_hw_pool[i])
1877 dma_pool_destroy(device->sed_hw_pool[i]);
1878 }
1879
1880 return -ENOMEM;
1881 }
1882
1883 void ioat3_dma_remove(struct ioatdma_device *device)
1884 {
1885 if (device->sed_pool) {
1886 int i;
1887 kmem_cache_destroy(device->sed_pool);
1888
1889 for (i = 0; i < MAX_SED_POOLS; i++)
1890 if (device->sed_hw_pool[i])
1891 dma_pool_destroy(device->sed_hw_pool[i]);
1892 }
1893 }
Linux with added FPC-III support