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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / dma / mv_xor.c
blob777732d0c2c0f06dd410c04383ff42aeee593932
1 /*
2 * offload engine driver for the Marvell XOR engine
3 * Copyright (C) 2007, 2008, Marvell International Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/platform_device.h>
27 #include <linux/memory.h>
28 #include <linux/clk.h>
29 #include <linux/of.h>
30 #include <linux/of_irq.h>
31 #include <linux/irqdomain.h>
32 #include <linux/platform_data/dma-mv_xor.h>
33
34 #include "dmaengine.h"
35 #include "mv_xor.h"
36
37 static void mv_xor_issue_pending(struct dma_chan *chan);
38
39 #define to_mv_xor_chan(chan) \
40 container_of(chan, struct mv_xor_chan, dmachan)
41
42 #define to_mv_xor_slot(tx) \
43 container_of(tx, struct mv_xor_desc_slot, async_tx)
44
45 #define mv_chan_to_devp(chan) \
46 ((chan)->dmadev.dev)
47
48 static void mv_desc_init(struct mv_xor_desc_slot *desc, unsigned long flags)
49 {
50 struct mv_xor_desc *hw_desc = desc->hw_desc;
51
52 hw_desc->status = (1 << 31);
53 hw_desc->phy_next_desc = 0;
54 hw_desc->desc_command = (1 << 31);
55 }
56
57 static u32 mv_desc_get_dest_addr(struct mv_xor_desc_slot *desc)
58 {
59 struct mv_xor_desc *hw_desc = desc->hw_desc;
60 return hw_desc->phy_dest_addr;
61 }
62
63 static u32 mv_desc_get_src_addr(struct mv_xor_desc_slot *desc,
64 int src_idx)
65 {
66 struct mv_xor_desc *hw_desc = desc->hw_desc;
67 return hw_desc->phy_src_addr[mv_phy_src_idx(src_idx)];
68 }
69
70
71 static void mv_desc_set_byte_count(struct mv_xor_desc_slot *desc,
72 u32 byte_count)
73 {
74 struct mv_xor_desc *hw_desc = desc->hw_desc;
75 hw_desc->byte_count = byte_count;
76 }
77
78 static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc,
79 u32 next_desc_addr)
80 {
81 struct mv_xor_desc *hw_desc = desc->hw_desc;
82 BUG_ON(hw_desc->phy_next_desc);
83 hw_desc->phy_next_desc = next_desc_addr;
84 }
85
86 static void mv_desc_clear_next_desc(struct mv_xor_desc_slot *desc)
87 {
88 struct mv_xor_desc *hw_desc = desc->hw_desc;
89 hw_desc->phy_next_desc = 0;
90 }
91
92 static void mv_desc_set_dest_addr(struct mv_xor_desc_slot *desc,
93 dma_addr_t addr)
94 {
95 struct mv_xor_desc *hw_desc = desc->hw_desc;
96 hw_desc->phy_dest_addr = addr;
97 }
98
99 static int mv_chan_memset_slot_count(size_t len)
100 {
101 return 1;
102 }
103
104 #define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c)
105
106 static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
107 int index, dma_addr_t addr)
108 {
109 struct mv_xor_desc *hw_desc = desc->hw_desc;
110 hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr;
111 if (desc->type == DMA_XOR)
112 hw_desc->desc_command |= (1 << index);
113 }
114
115 static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
116 {
117 return readl_relaxed(XOR_CURR_DESC(chan));
118 }
119
120 static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
121 u32 next_desc_addr)
122 {
123 writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan));
124 }
125
126 static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
127 {
128 u32 val = readl_relaxed(XOR_INTR_MASK(chan));
129 val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
130 writel_relaxed(val, XOR_INTR_MASK(chan));
131 }
132
133 static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
134 {
135 u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan));
136 intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
137 return intr_cause;
138 }
139
140 static int mv_is_err_intr(u32 intr_cause)
141 {
142 if (intr_cause & ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)))
143 return 1;
144
145 return 0;
146 }
147
148 static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
149 {
150 u32 val = ~(1 << (chan->idx * 16));
151 dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val);
152 writel_relaxed(val, XOR_INTR_CAUSE(chan));
153 }
154
155 static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan)
156 {
157 u32 val = 0xFFFF0000 >> (chan->idx * 16);
158 writel_relaxed(val, XOR_INTR_CAUSE(chan));
159 }
160
161 static int mv_can_chain(struct mv_xor_desc_slot *desc)
162 {
163 struct mv_xor_desc_slot *chain_old_tail = list_entry(
164 desc->chain_node.prev, struct mv_xor_desc_slot, chain_node);
165
166 if (chain_old_tail->type != desc->type)
167 return 0;
168
169 return 1;
170 }
171
172 static void mv_set_mode(struct mv_xor_chan *chan,
173 enum dma_transaction_type type)
174 {
175 u32 op_mode;
176 u32 config = readl_relaxed(XOR_CONFIG(chan));
177
178 switch (type) {
179 case DMA_XOR:
180 op_mode = XOR_OPERATION_MODE_XOR;
181 break;
182 case DMA_MEMCPY:
183 op_mode = XOR_OPERATION_MODE_MEMCPY;
184 break;
185 default:
186 dev_err(mv_chan_to_devp(chan),
187 "error: unsupported operation %d\n",
188 type);
189 BUG();
190 return;
191 }
192
193 config &= ~0x7;
194 config |= op_mode;
195
196 #if defined(__BIG_ENDIAN)
197 config |= XOR_DESCRIPTOR_SWAP;
198 #else
199 config &= ~XOR_DESCRIPTOR_SWAP;
200 #endif
201
202 writel_relaxed(config, XOR_CONFIG(chan));
203 chan->current_type = type;
204 }
205
206 static void mv_chan_activate(struct mv_xor_chan *chan)
207 {
208 dev_dbg(mv_chan_to_devp(chan), " activate chan.\n");
209
210 /* writel ensures all descriptors are flushed before activation */
211 writel(BIT(0), XOR_ACTIVATION(chan));
212 }
213
214 static char mv_chan_is_busy(struct mv_xor_chan *chan)
215 {
216 u32 state = readl_relaxed(XOR_ACTIVATION(chan));
217
218 state = (state >> 4) & 0x3;
219
220 return (state == 1) ? 1 : 0;
221 }
222
223 static int mv_chan_xor_slot_count(size_t len, int src_cnt)
224 {
225 return 1;
226 }
227
228 /**
229 * mv_xor_free_slots - flags descriptor slots for reuse
230 * @slot: Slot to free
231 * Caller must hold &mv_chan->lock while calling this function
232 */
233 static void mv_xor_free_slots(struct mv_xor_chan *mv_chan,
234 struct mv_xor_desc_slot *slot)
235 {
236 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d slot %p\n",
237 __func__, __LINE__, slot);
238
239 slot->slots_per_op = 0;
240
241 }
242
243 /*
244 * mv_xor_start_new_chain - program the engine to operate on new chain headed by
245 * sw_desc
246 * Caller must hold &mv_chan->lock while calling this function
247 */
248 static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan,
249 struct mv_xor_desc_slot *sw_desc)
250 {
251 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n",
252 __func__, __LINE__, sw_desc);
253 if (sw_desc->type != mv_chan->current_type)
254 mv_set_mode(mv_chan, sw_desc->type);
255
256 /* set the hardware chain */
257 mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
258
259 mv_chan->pending += sw_desc->slot_cnt;
260 mv_xor_issue_pending(&mv_chan->dmachan);
261 }
262
263 static dma_cookie_t
264 mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
265 struct mv_xor_chan *mv_chan, dma_cookie_t cookie)
266 {
267 BUG_ON(desc->async_tx.cookie < 0);
268
269 if (desc->async_tx.cookie > 0) {
270 cookie = desc->async_tx.cookie;
271
272 /* call the callback (must not sleep or submit new
273 * operations to this channel)
274 */
275 if (desc->async_tx.callback)
276 desc->async_tx.callback(
277 desc->async_tx.callback_param);
278
279 /* unmap dma addresses
280 * (unmap_single vs unmap_page?)
281 */
282 if (desc->group_head && desc->unmap_len) {
283 struct mv_xor_desc_slot *unmap = desc->group_head;
284 struct device *dev = mv_chan_to_devp(mv_chan);
285 u32 len = unmap->unmap_len;
286 enum dma_ctrl_flags flags = desc->async_tx.flags;
287 u32 src_cnt;
288 dma_addr_t addr;
289 dma_addr_t dest;
290
291 src_cnt = unmap->unmap_src_cnt;
292 dest = mv_desc_get_dest_addr(unmap);
293 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
294 enum dma_data_direction dir;
295
296 if (src_cnt > 1) /* is xor ? */
297 dir = DMA_BIDIRECTIONAL;
298 else
299 dir = DMA_FROM_DEVICE;
300 dma_unmap_page(dev, dest, len, dir);
301 }
302
303 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
304 while (src_cnt--) {
305 addr = mv_desc_get_src_addr(unmap,
306 src_cnt);
307 if (addr == dest)
308 continue;
309 dma_unmap_page(dev, addr, len,
310 DMA_TO_DEVICE);
311 }
312 }
313 desc->group_head = NULL;
314 }
315 }
316
317 /* run dependent operations */
318 dma_run_dependencies(&desc->async_tx);
319
320 return cookie;
321 }
322
323 static int
324 mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan)
325 {
326 struct mv_xor_desc_slot *iter, *_iter;
327
328 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
329 list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
330 completed_node) {
331
332 if (async_tx_test_ack(&iter->async_tx)) {
333 list_del(&iter->completed_node);
334 mv_xor_free_slots(mv_chan, iter);
335 }
336 }
337 return 0;
338 }
339
340 static int
341 mv_xor_clean_slot(struct mv_xor_desc_slot *desc,
342 struct mv_xor_chan *mv_chan)
343 {
344 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n",
345 __func__, __LINE__, desc, desc->async_tx.flags);
346 list_del(&desc->chain_node);
347 /* the client is allowed to attach dependent operations
348 * until 'ack' is set
349 */
350 if (!async_tx_test_ack(&desc->async_tx)) {
351 /* move this slot to the completed_slots */
352 list_add_tail(&desc->completed_node, &mv_chan->completed_slots);
353 return 0;
354 }
355
356 mv_xor_free_slots(mv_chan, desc);
357 return 0;
358 }
359
360 static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
361 {
362 struct mv_xor_desc_slot *iter, *_iter;
363 dma_cookie_t cookie = 0;
364 int busy = mv_chan_is_busy(mv_chan);
365 u32 current_desc = mv_chan_get_current_desc(mv_chan);
366 int current_cleaned = 0;
367 struct mv_xor_desc *hw_desc;
368
369 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
370 dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc);
371 mv_xor_clean_completed_slots(mv_chan);
372
373 /* free completed slots from the chain starting with
374 * the oldest descriptor
375 */
376
377 list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
378 chain_node) {
379
380 /* clean finished descriptors */
381 hw_desc = iter->hw_desc;
382 if (hw_desc->status & XOR_DESC_SUCCESS) {
383 cookie = mv_xor_run_tx_complete_actions(iter, mv_chan,
384 cookie);
385
386 /* done processing desc, clean slot */
387 mv_xor_clean_slot(iter, mv_chan);
388
389 /* break if we did cleaned the current */
390 if (iter->async_tx.phys == current_desc) {
391 current_cleaned = 1;
392 break;
393 }
394 } else {
395 if (iter->async_tx.phys == current_desc) {
396 current_cleaned = 0;
397 break;
398 }
399 }
400 }
401
402 if ((busy == 0) && !list_empty(&mv_chan->chain)) {
403 if (current_cleaned) {
404 /*
405 * current descriptor cleaned and removed, run
406 * from list head
407 */
408 iter = list_entry(mv_chan->chain.next,
409 struct mv_xor_desc_slot,
410 chain_node);
411 mv_xor_start_new_chain(mv_chan, iter);
412 } else {
413 if (!list_is_last(&iter->chain_node, &mv_chan->chain)) {
414 /*
415 * descriptors are still waiting after
416 * current, trigger them
417 */
418 iter = list_entry(iter->chain_node.next,
419 struct mv_xor_desc_slot,
420 chain_node);
421 mv_xor_start_new_chain(mv_chan, iter);
422 } else {
423 /*
424 * some descriptors are still waiting
425 * to be cleaned
426 */
427 tasklet_schedule(&mv_chan->irq_tasklet);
428 }
429 }
430 }
431
432 if (cookie > 0)
433 mv_chan->dmachan.completed_cookie = cookie;
434 }
435
436 static void
437 mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
438 {
439 spin_lock_bh(&mv_chan->lock);
440 __mv_xor_slot_cleanup(mv_chan);
441 spin_unlock_bh(&mv_chan->lock);
442 }
443
444 static void mv_xor_tasklet(unsigned long data)
445 {
446 struct mv_xor_chan *chan = (struct mv_xor_chan *) data;
447 mv_xor_slot_cleanup(chan);
448 }
449
450 static struct mv_xor_desc_slot *
451 mv_xor_alloc_slots(struct mv_xor_chan *mv_chan, int num_slots,
452 int slots_per_op)
453 {
454 struct mv_xor_desc_slot *iter, *_iter, *alloc_start = NULL;
455 LIST_HEAD(chain);
456 int slots_found, retry = 0;
457
458 /* start search from the last allocated descrtiptor
459 * if a contiguous allocation can not be found start searching
460 * from the beginning of the list
461 */
462 retry:
463 slots_found = 0;
464 if (retry == 0)
465 iter = mv_chan->last_used;
466 else
467 iter = list_entry(&mv_chan->all_slots,
468 struct mv_xor_desc_slot,
469 slot_node);
470
471 list_for_each_entry_safe_continue(
472 iter, _iter, &mv_chan->all_slots, slot_node) {
473 prefetch(_iter);
474 prefetch(&_iter->async_tx);
475 if (iter->slots_per_op) {
476 /* give up after finding the first busy slot
477 * on the second pass through the list
478 */
479 if (retry)
480 break;
481
482 slots_found = 0;
483 continue;
484 }
485
486 /* start the allocation if the slot is correctly aligned */
487 if (!slots_found++)
488 alloc_start = iter;
489
490 if (slots_found == num_slots) {
491 struct mv_xor_desc_slot *alloc_tail = NULL;
492 struct mv_xor_desc_slot *last_used = NULL;
493 iter = alloc_start;
494 while (num_slots) {
495 int i;
496
497 /* pre-ack all but the last descriptor */
498 async_tx_ack(&iter->async_tx);
499
500 list_add_tail(&iter->chain_node, &chain);
501 alloc_tail = iter;
502 iter->async_tx.cookie = 0;
503 iter->slot_cnt = num_slots;
504 iter->xor_check_result = NULL;
505 for (i = 0; i < slots_per_op; i++) {
506 iter->slots_per_op = slots_per_op - i;
507 last_used = iter;
508 iter = list_entry(iter->slot_node.next,
509 struct mv_xor_desc_slot,
510 slot_node);
511 }
512 num_slots -= slots_per_op;
513 }
514 alloc_tail->group_head = alloc_start;
515 alloc_tail->async_tx.cookie = -EBUSY;
516 list_splice(&chain, &alloc_tail->tx_list);
517 mv_chan->last_used = last_used;
518 mv_desc_clear_next_desc(alloc_start);
519 mv_desc_clear_next_desc(alloc_tail);
520 return alloc_tail;
521 }
522 }
523 if (!retry++)
524 goto retry;
525
526 /* try to free some slots if the allocation fails */
527 tasklet_schedule(&mv_chan->irq_tasklet);
528
529 return NULL;
530 }
531
532 /************************ DMA engine API functions ****************************/
533 static dma_cookie_t
534 mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
535 {
536 struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx);
537 struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan);
538 struct mv_xor_desc_slot *grp_start, *old_chain_tail;
539 dma_cookie_t cookie;
540 int new_hw_chain = 1;
541
542 dev_dbg(mv_chan_to_devp(mv_chan),
543 "%s sw_desc %p: async_tx %p\n",
544 __func__, sw_desc, &sw_desc->async_tx);
545
546 grp_start = sw_desc->group_head;
547
548 spin_lock_bh(&mv_chan->lock);
549 cookie = dma_cookie_assign(tx);
550
551 if (list_empty(&mv_chan->chain))
552 list_splice_init(&sw_desc->tx_list, &mv_chan->chain);
553 else {
554 new_hw_chain = 0;
555
556 old_chain_tail = list_entry(mv_chan->chain.prev,
557 struct mv_xor_desc_slot,
558 chain_node);
559 list_splice_init(&grp_start->tx_list,
560 &old_chain_tail->chain_node);
561
562 if (!mv_can_chain(grp_start))
563 goto submit_done;
564
565 dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %x\n",
566 old_chain_tail->async_tx.phys);
567
568 /* fix up the hardware chain */
569 mv_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
570
571 /* if the channel is not busy */
572 if (!mv_chan_is_busy(mv_chan)) {
573 u32 current_desc = mv_chan_get_current_desc(mv_chan);
574 /*
575 * and the curren desc is the end of the chain before
576 * the append, then we need to start the channel
577 */
578 if (current_desc == old_chain_tail->async_tx.phys)
579 new_hw_chain = 1;
580 }
581 }
582
583 if (new_hw_chain)
584 mv_xor_start_new_chain(mv_chan, grp_start);
585
586 submit_done:
587 spin_unlock_bh(&mv_chan->lock);
588
589 return cookie;
590 }
591
592 /* returns the number of allocated descriptors */
593 static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
594 {
595 char *hw_desc;
596 int idx;
597 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
598 struct mv_xor_desc_slot *slot = NULL;
599 int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE;
600
601 /* Allocate descriptor slots */
602 idx = mv_chan->slots_allocated;
603 while (idx < num_descs_in_pool) {
604 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
605 if (!slot) {
606 printk(KERN_INFO "MV XOR Channel only initialized"
607 " %d descriptor slots", idx);
608 break;
609 }
610 hw_desc = (char *) mv_chan->dma_desc_pool_virt;
611 slot->hw_desc = (void *) &hw_desc[idx * MV_XOR_SLOT_SIZE];
612
613 dma_async_tx_descriptor_init(&slot->async_tx, chan);
614 slot->async_tx.tx_submit = mv_xor_tx_submit;
615 INIT_LIST_HEAD(&slot->chain_node);
616 INIT_LIST_HEAD(&slot->slot_node);
617 INIT_LIST_HEAD(&slot->tx_list);
618 hw_desc = (char *) mv_chan->dma_desc_pool;
619 slot->async_tx.phys =
620 (dma_addr_t) &hw_desc[idx * MV_XOR_SLOT_SIZE];
621 slot->idx = idx++;
622
623 spin_lock_bh(&mv_chan->lock);
624 mv_chan->slots_allocated = idx;
625 list_add_tail(&slot->slot_node, &mv_chan->all_slots);
626 spin_unlock_bh(&mv_chan->lock);
627 }
628
629 if (mv_chan->slots_allocated && !mv_chan->last_used)
630 mv_chan->last_used = list_entry(mv_chan->all_slots.next,
631 struct mv_xor_desc_slot,
632 slot_node);
633
634 dev_dbg(mv_chan_to_devp(mv_chan),
635 "allocated %d descriptor slots last_used: %p\n",
636 mv_chan->slots_allocated, mv_chan->last_used);
637
638 return mv_chan->slots_allocated ? : -ENOMEM;
639 }
640
641 static struct dma_async_tx_descriptor *
642 mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
643 size_t len, unsigned long flags)
644 {
645 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
646 struct mv_xor_desc_slot *sw_desc, *grp_start;
647 int slot_cnt;
648
649 dev_dbg(mv_chan_to_devp(mv_chan),
650 "%s dest: %x src %x len: %u flags: %ld\n",
651 __func__, dest, src, len, flags);
652 if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
653 return NULL;
654
655 BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
656
657 spin_lock_bh(&mv_chan->lock);
658 slot_cnt = mv_chan_memcpy_slot_count(len);
659 sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
660 if (sw_desc) {
661 sw_desc->type = DMA_MEMCPY;
662 sw_desc->async_tx.flags = flags;
663 grp_start = sw_desc->group_head;
664 mv_desc_init(grp_start, flags);
665 mv_desc_set_byte_count(grp_start, len);
666 mv_desc_set_dest_addr(sw_desc->group_head, dest);
667 mv_desc_set_src_addr(grp_start, 0, src);
668 sw_desc->unmap_src_cnt = 1;
669 sw_desc->unmap_len = len;
670 }
671 spin_unlock_bh(&mv_chan->lock);
672
673 dev_dbg(mv_chan_to_devp(mv_chan),
674 "%s sw_desc %p async_tx %p\n",
675 __func__, sw_desc, sw_desc ? &sw_desc->async_tx : NULL);
676
677 return sw_desc ? &sw_desc->async_tx : NULL;
678 }
679
680 static struct dma_async_tx_descriptor *
681 mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
682 unsigned int src_cnt, size_t len, unsigned long flags)
683 {
684 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
685 struct mv_xor_desc_slot *sw_desc, *grp_start;
686 int slot_cnt;
687
688 if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
689 return NULL;
690
691 BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
692
693 dev_dbg(mv_chan_to_devp(mv_chan),
694 "%s src_cnt: %d len: dest %x %u flags: %ld\n",
695 __func__, src_cnt, len, dest, flags);
696
697 spin_lock_bh(&mv_chan->lock);
698 slot_cnt = mv_chan_xor_slot_count(len, src_cnt);
699 sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
700 if (sw_desc) {
701 sw_desc->type = DMA_XOR;
702 sw_desc->async_tx.flags = flags;
703 grp_start = sw_desc->group_head;
704 mv_desc_init(grp_start, flags);
705 /* the byte count field is the same as in memcpy desc*/
706 mv_desc_set_byte_count(grp_start, len);
707 mv_desc_set_dest_addr(sw_desc->group_head, dest);
708 sw_desc->unmap_src_cnt = src_cnt;
709 sw_desc->unmap_len = len;
710 while (src_cnt--)
711 mv_desc_set_src_addr(grp_start, src_cnt, src[src_cnt]);
712 }
713 spin_unlock_bh(&mv_chan->lock);
714 dev_dbg(mv_chan_to_devp(mv_chan),
715 "%s sw_desc %p async_tx %p \n",
716 __func__, sw_desc, &sw_desc->async_tx);
717 return sw_desc ? &sw_desc->async_tx : NULL;
718 }
719
720 static void mv_xor_free_chan_resources(struct dma_chan *chan)
721 {
722 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
723 struct mv_xor_desc_slot *iter, *_iter;
724 int in_use_descs = 0;
725
726 mv_xor_slot_cleanup(mv_chan);
727
728 spin_lock_bh(&mv_chan->lock);
729 list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
730 chain_node) {
731 in_use_descs++;
732 list_del(&iter->chain_node);
733 }
734 list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
735 completed_node) {
736 in_use_descs++;
737 list_del(&iter->completed_node);
738 }
739 list_for_each_entry_safe_reverse(
740 iter, _iter, &mv_chan->all_slots, slot_node) {
741 list_del(&iter->slot_node);
742 kfree(iter);
743 mv_chan->slots_allocated--;
744 }
745 mv_chan->last_used = NULL;
746
747 dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n",
748 __func__, mv_chan->slots_allocated);
749 spin_unlock_bh(&mv_chan->lock);
750
751 if (in_use_descs)
752 dev_err(mv_chan_to_devp(mv_chan),
753 "freeing %d in use descriptors!\n", in_use_descs);
754 }
755
756 /**
757 * mv_xor_status - poll the status of an XOR transaction
758 * @chan: XOR channel handle
759 * @cookie: XOR transaction identifier
760 * @txstate: XOR transactions state holder (or NULL)
761 */
762 static enum dma_status mv_xor_status(struct dma_chan *chan,
763 dma_cookie_t cookie,
764 struct dma_tx_state *txstate)
765 {
766 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
767 enum dma_status ret;
768
769 ret = dma_cookie_status(chan, cookie, txstate);
770 if (ret == DMA_SUCCESS) {
771 mv_xor_clean_completed_slots(mv_chan);
772 return ret;
773 }
774 mv_xor_slot_cleanup(mv_chan);
775
776 return dma_cookie_status(chan, cookie, txstate);
777 }
778
779 static void mv_dump_xor_regs(struct mv_xor_chan *chan)
780 {
781 u32 val;
782
783 val = readl_relaxed(XOR_CONFIG(chan));
784 dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val);
785
786 val = readl_relaxed(XOR_ACTIVATION(chan));
787 dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val);
788
789 val = readl_relaxed(XOR_INTR_CAUSE(chan));
790 dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val);
791
792 val = readl_relaxed(XOR_INTR_MASK(chan));
793 dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val);
794
795 val = readl_relaxed(XOR_ERROR_CAUSE(chan));
796 dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val);
797
798 val = readl_relaxed(XOR_ERROR_ADDR(chan));
799 dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val);
800 }
801
802 static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan,
803 u32 intr_cause)
804 {
805 if (intr_cause & (1 << 4)) {
806 dev_dbg(mv_chan_to_devp(chan),
807 "ignore this error\n");
808 return;
809 }
810
811 dev_err(mv_chan_to_devp(chan),
812 "error on chan %d. intr cause 0x%08x\n",
813 chan->idx, intr_cause);
814
815 mv_dump_xor_regs(chan);
816 BUG();
817 }
818
819 static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
820 {
821 struct mv_xor_chan *chan = data;
822 u32 intr_cause = mv_chan_get_intr_cause(chan);
823
824 dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause);
825
826 if (mv_is_err_intr(intr_cause))
827 mv_xor_err_interrupt_handler(chan, intr_cause);
828
829 tasklet_schedule(&chan->irq_tasklet);
830
831 mv_xor_device_clear_eoc_cause(chan);
832
833 return IRQ_HANDLED;
834 }
835
836 static void mv_xor_issue_pending(struct dma_chan *chan)
837 {
838 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
839
840 if (mv_chan->pending >= MV_XOR_THRESHOLD) {
841 mv_chan->pending = 0;
842 mv_chan_activate(mv_chan);
843 }
844 }
845
846 /*
847 * Perform a transaction to verify the HW works.
848 */
849 #define MV_XOR_TEST_SIZE 2000
850
851 static int mv_xor_memcpy_self_test(struct mv_xor_chan *mv_chan)
852 {
853 int i;
854 void *src, *dest;
855 dma_addr_t src_dma, dest_dma;
856 struct dma_chan *dma_chan;
857 dma_cookie_t cookie;
858 struct dma_async_tx_descriptor *tx;
859 int err = 0;
860
861 src = kmalloc(sizeof(u8) * MV_XOR_TEST_SIZE, GFP_KERNEL);
862 if (!src)
863 return -ENOMEM;
864
865 dest = kzalloc(sizeof(u8) * MV_XOR_TEST_SIZE, GFP_KERNEL);
866 if (!dest) {
867 kfree(src);
868 return -ENOMEM;
869 }
870
871 /* Fill in src buffer */
872 for (i = 0; i < MV_XOR_TEST_SIZE; i++)
873 ((u8 *) src)[i] = (u8)i;
874
875 dma_chan = &mv_chan->dmachan;
876 if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
877 err = -ENODEV;
878 goto out;
879 }
880
881 dest_dma = dma_map_single(dma_chan->device->dev, dest,
882 MV_XOR_TEST_SIZE, DMA_FROM_DEVICE);
883
884 src_dma = dma_map_single(dma_chan->device->dev, src,
885 MV_XOR_TEST_SIZE, DMA_TO_DEVICE);
886
887 tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
888 MV_XOR_TEST_SIZE, 0);
889 cookie = mv_xor_tx_submit(tx);
890 mv_xor_issue_pending(dma_chan);
891 async_tx_ack(tx);
892 msleep(1);
893
894 if (mv_xor_status(dma_chan, cookie, NULL) !=
895 DMA_SUCCESS) {
896 dev_err(dma_chan->device->dev,
897 "Self-test copy timed out, disabling\n");
898 err = -ENODEV;
899 goto free_resources;
900 }
901
902 dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
903 MV_XOR_TEST_SIZE, DMA_FROM_DEVICE);
904 if (memcmp(src, dest, MV_XOR_TEST_SIZE)) {
905 dev_err(dma_chan->device->dev,
906 "Self-test copy failed compare, disabling\n");
907 err = -ENODEV;
908 goto free_resources;
909 }
910
911 free_resources:
912 mv_xor_free_chan_resources(dma_chan);
913 out:
914 kfree(src);
915 kfree(dest);
916 return err;
917 }
918
919 #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
920 static int
921 mv_xor_xor_self_test(struct mv_xor_chan *mv_chan)
922 {
923 int i, src_idx;
924 struct page *dest;
925 struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
926 dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
927 dma_addr_t dest_dma;
928 struct dma_async_tx_descriptor *tx;
929 struct dma_chan *dma_chan;
930 dma_cookie_t cookie;
931 u8 cmp_byte = 0;
932 u32 cmp_word;
933 int err = 0;
934
935 for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) {
936 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
937 if (!xor_srcs[src_idx]) {
938 while (src_idx--)
939 __free_page(xor_srcs[src_idx]);
940 return -ENOMEM;
941 }
942 }
943
944 dest = alloc_page(GFP_KERNEL);
945 if (!dest) {
946 while (src_idx--)
947 __free_page(xor_srcs[src_idx]);
948 return -ENOMEM;
949 }
950
951 /* Fill in src buffers */
952 for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) {
953 u8 *ptr = page_address(xor_srcs[src_idx]);
954 for (i = 0; i < PAGE_SIZE; i++)
955 ptr[i] = (1 << src_idx);
956 }
957
958 for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++)
959 cmp_byte ^= (u8) (1 << src_idx);
960
961 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
962 (cmp_byte << 8) | cmp_byte;
963
964 memset(page_address(dest), 0, PAGE_SIZE);
965
966 dma_chan = &mv_chan->dmachan;
967 if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
968 err = -ENODEV;
969 goto out;
970 }
971
972 /* test xor */
973 dest_dma = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
974 DMA_FROM_DEVICE);
975
976 for (i = 0; i < MV_XOR_NUM_SRC_TEST; i++)
977 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
978 0, PAGE_SIZE, DMA_TO_DEVICE);
979
980 tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
981 MV_XOR_NUM_SRC_TEST, PAGE_SIZE, 0);
982
983 cookie = mv_xor_tx_submit(tx);
984 mv_xor_issue_pending(dma_chan);
985 async_tx_ack(tx);
986 msleep(8);
987
988 if (mv_xor_status(dma_chan, cookie, NULL) !=
989 DMA_SUCCESS) {
990 dev_err(dma_chan->device->dev,
991 "Self-test xor timed out, disabling\n");
992 err = -ENODEV;
993 goto free_resources;
994 }
995
996 dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
997 PAGE_SIZE, DMA_FROM_DEVICE);
998 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
999 u32 *ptr = page_address(dest);
1000 if (ptr[i] != cmp_word) {
1001 dev_err(dma_chan->device->dev,
1002 "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n",
1003 i, ptr[i], cmp_word);
1004 err = -ENODEV;
1005 goto free_resources;
1006 }
1007 }
1008
1009 free_resources:
1010 mv_xor_free_chan_resources(dma_chan);
1011 out:
1012 src_idx = MV_XOR_NUM_SRC_TEST;
1013 while (src_idx--)
1014 __free_page(xor_srcs[src_idx]);
1015 __free_page(dest);
1016 return err;
1017 }
1018
1019 /* This driver does not implement any of the optional DMA operations. */
1020 static int
1021 mv_xor_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1022 unsigned long arg)
1023 {
1024 return -ENOSYS;
1025 }
1026
1027 static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
1028 {
1029 struct dma_chan *chan, *_chan;
1030 struct device *dev = mv_chan->dmadev.dev;
1031
1032 dma_async_device_unregister(&mv_chan->dmadev);
1033
1034 dma_free_coherent(dev, MV_XOR_POOL_SIZE,
1035 mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
1036
1037 list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels,
1038 device_node) {
1039 list_del(&chan->device_node);
1040 }
1041
1042 free_irq(mv_chan->irq, mv_chan);
1043
1044 return 0;
1045 }
1046
1047 static struct mv_xor_chan *
1048 mv_xor_channel_add(struct mv_xor_device *xordev,
1049 struct platform_device *pdev,
1050 int idx, dma_cap_mask_t cap_mask, int irq)
1051 {
1052 int ret = 0;
1053 struct mv_xor_chan *mv_chan;
1054 struct dma_device *dma_dev;
1055
1056 mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
1057 if (!mv_chan)
1058 return ERR_PTR(-ENOMEM);
1059
1060 mv_chan->idx = idx;
1061 mv_chan->irq = irq;
1062
1063 dma_dev = &mv_chan->dmadev;
1064
1065 /* allocate coherent memory for hardware descriptors
1066 * note: writecombine gives slightly better performance, but
1067 * requires that we explicitly flush the writes
1068 */
1069 mv_chan->dma_desc_pool_virt =
1070 dma_alloc_writecombine(&pdev->dev, MV_XOR_POOL_SIZE,
1071 &mv_chan->dma_desc_pool, GFP_KERNEL);
1072 if (!mv_chan->dma_desc_pool_virt)
1073 return ERR_PTR(-ENOMEM);
1074
1075 /* discover transaction capabilites from the platform data */
1076 dma_dev->cap_mask = cap_mask;
1077
1078 INIT_LIST_HEAD(&dma_dev->channels);
1079
1080 /* set base routines */
1081 dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources;
1082 dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
1083 dma_dev->device_tx_status = mv_xor_status;
1084 dma_dev->device_issue_pending = mv_xor_issue_pending;
1085 dma_dev->device_control = mv_xor_control;
1086 dma_dev->dev = &pdev->dev;
1087
1088 /* set prep routines based on capability */
1089 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1090 dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy;
1091 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1092 dma_dev->max_xor = 8;
1093 dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
1094 }
1095
1096 mv_chan->mmr_base = xordev->xor_base;
1097 if (!mv_chan->mmr_base) {
1098 ret = -ENOMEM;
1099 goto err_free_dma;
1100 }
1101 tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)
1102 mv_chan);
1103
1104 /* clear errors before enabling interrupts */
1105 mv_xor_device_clear_err_status(mv_chan);
1106
1107 ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler,
1108 0, dev_name(&pdev->dev), mv_chan);
1109 if (ret)
1110 goto err_free_dma;
1111
1112 mv_chan_unmask_interrupts(mv_chan);
1113
1114 mv_set_mode(mv_chan, DMA_MEMCPY);
1115
1116 spin_lock_init(&mv_chan->lock);
1117 INIT_LIST_HEAD(&mv_chan->chain);
1118 INIT_LIST_HEAD(&mv_chan->completed_slots);
1119 INIT_LIST_HEAD(&mv_chan->all_slots);
1120 mv_chan->dmachan.device = dma_dev;
1121 dma_cookie_init(&mv_chan->dmachan);
1122
1123 list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels);
1124
1125 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1126 ret = mv_xor_memcpy_self_test(mv_chan);
1127 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1128 if (ret)
1129 goto err_free_irq;
1130 }
1131
1132 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1133 ret = mv_xor_xor_self_test(mv_chan);
1134 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1135 if (ret)
1136 goto err_free_irq;
1137 }
1138
1139 dev_info(&pdev->dev, "Marvell XOR: ( %s%s%s)\n",
1140 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1141 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1142 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1143
1144 dma_async_device_register(dma_dev);
1145 return mv_chan;
1146
1147 err_free_irq:
1148 free_irq(mv_chan->irq, mv_chan);
1149 err_free_dma:
1150 dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE,
1151 mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
1152 return ERR_PTR(ret);
1153 }
1154
1155 static void
1156 mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
1157 const struct mbus_dram_target_info *dram)
1158 {
1159 void __iomem *base = xordev->xor_base;
1160 u32 win_enable = 0;
1161 int i;
1162
1163 for (i = 0; i < 8; i++) {
1164 writel(0, base + WINDOW_BASE(i));
1165 writel(0, base + WINDOW_SIZE(i));
1166 if (i < 4)
1167 writel(0, base + WINDOW_REMAP_HIGH(i));
1168 }
1169
1170 for (i = 0; i < dram->num_cs; i++) {
1171 const struct mbus_dram_window *cs = dram->cs + i;
1172
1173 writel((cs->base & 0xffff0000) |
1174 (cs->mbus_attr << 8) |
1175 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1176 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1177
1178 win_enable |= (1 << i);
1179 win_enable |= 3 << (16 + (2 * i));
1180 }
1181
1182 writel(win_enable, base + WINDOW_BAR_ENABLE(0));
1183 writel(win_enable, base + WINDOW_BAR_ENABLE(1));
1184 writel(0, base + WINDOW_OVERRIDE_CTRL(0));
1185 writel(0, base + WINDOW_OVERRIDE_CTRL(1));
1186 }
1187
1188 static int mv_xor_probe(struct platform_device *pdev)
1189 {
1190 const struct mbus_dram_target_info *dram;
1191 struct mv_xor_device *xordev;
1192 struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev);
1193 struct resource *res;
1194 int i, ret;
1195
1196 dev_notice(&pdev->dev, "Marvell shared XOR driver\n");
1197
1198 xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL);
1199 if (!xordev)
1200 return -ENOMEM;
1201
1202 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1203 if (!res)
1204 return -ENODEV;
1205
1206 xordev->xor_base = devm_ioremap(&pdev->dev, res->start,
1207 resource_size(res));
1208 if (!xordev->xor_base)
1209 return -EBUSY;
1210
1211 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1212 if (!res)
1213 return -ENODEV;
1214
1215 xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start,
1216 resource_size(res));
1217 if (!xordev->xor_high_base)
1218 return -EBUSY;
1219
1220 platform_set_drvdata(pdev, xordev);
1221
1222 /*
1223 * (Re-)program MBUS remapping windows if we are asked to.
1224 */
1225 dram = mv_mbus_dram_info();
1226 if (dram)
1227 mv_xor_conf_mbus_windows(xordev, dram);
1228
1229 /* Not all platforms can gate the clock, so it is not
1230 * an error if the clock does not exists.
1231 */
1232 xordev->clk = clk_get(&pdev->dev, NULL);
1233 if (!IS_ERR(xordev->clk))
1234 clk_prepare_enable(xordev->clk);
1235
1236 if (pdev->dev.of_node) {
1237 struct device_node *np;
1238 int i = 0;
1239
1240 for_each_child_of_node(pdev->dev.of_node, np) {
1241 dma_cap_mask_t cap_mask;
1242 int irq;
1243
1244 dma_cap_zero(cap_mask);
1245 if (of_property_read_bool(np, "dmacap,memcpy"))
1246 dma_cap_set(DMA_MEMCPY, cap_mask);
1247 if (of_property_read_bool(np, "dmacap,xor"))
1248 dma_cap_set(DMA_XOR, cap_mask);
1249 if (of_property_read_bool(np, "dmacap,interrupt"))
1250 dma_cap_set(DMA_INTERRUPT, cap_mask);
1251
1252 irq = irq_of_parse_and_map(np, 0);
1253 if (!irq) {
1254 ret = -ENODEV;
1255 goto err_channel_add;
1256 }
1257
1258 xordev->channels[i] =
1259 mv_xor_channel_add(xordev, pdev, i,
1260 cap_mask, irq);
1261 if (IS_ERR(xordev->channels[i])) {
1262 ret = PTR_ERR(xordev->channels[i]);
1263 xordev->channels[i] = NULL;
1264 irq_dispose_mapping(irq);
1265 goto err_channel_add;
1266 }
1267
1268 i++;
1269 }
1270 } else if (pdata && pdata->channels) {
1271 for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
1272 struct mv_xor_channel_data *cd;
1273 int irq;
1274
1275 cd = &pdata->channels[i];
1276 if (!cd) {
1277 ret = -ENODEV;
1278 goto err_channel_add;
1279 }
1280
1281 irq = platform_get_irq(pdev, i);
1282 if (irq < 0) {
1283 ret = irq;
1284 goto err_channel_add;
1285 }
1286
1287 xordev->channels[i] =
1288 mv_xor_channel_add(xordev, pdev, i,
1289 cd->cap_mask, irq);
1290 if (IS_ERR(xordev->channels[i])) {
1291 ret = PTR_ERR(xordev->channels[i]);
1292 goto err_channel_add;
1293 }
1294 }
1295 }
1296
1297 return 0;
1298
1299 err_channel_add:
1300 for (i = 0; i < MV_XOR_MAX_CHANNELS; i++)
1301 if (xordev->channels[i]) {
1302 mv_xor_channel_remove(xordev->channels[i]);
1303 if (pdev->dev.of_node)
1304 irq_dispose_mapping(xordev->channels[i]->irq);
1305 }
1306
1307 if (!IS_ERR(xordev->clk)) {
1308 clk_disable_unprepare(xordev->clk);
1309 clk_put(xordev->clk);
1310 }
1311
1312 return ret;
1313 }
1314
1315 static int mv_xor_remove(struct platform_device *pdev)
1316 {
1317 struct mv_xor_device *xordev = platform_get_drvdata(pdev);
1318 int i;
1319
1320 for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
1321 if (xordev->channels[i])
1322 mv_xor_channel_remove(xordev->channels[i]);
1323 }
1324
1325 if (!IS_ERR(xordev->clk)) {
1326 clk_disable_unprepare(xordev->clk);
1327 clk_put(xordev->clk);
1328 }
1329
1330 return 0;
1331 }
1332
1333 #ifdef CONFIG_OF
1334 static struct of_device_id mv_xor_dt_ids[] = {
1335 { .compatible = "marvell,orion-xor", },
1336 {},
1337 };
1338 MODULE_DEVICE_TABLE(of, mv_xor_dt_ids);
1339 #endif
1340
1341 static struct platform_driver mv_xor_driver = {
1342 .probe = mv_xor_probe,
1343 .remove = mv_xor_remove,
1344 .driver = {
1345 .owner = THIS_MODULE,
1346 .name = MV_XOR_NAME,
1347 .of_match_table = of_match_ptr(mv_xor_dt_ids),
1348 },
1349 };
1350
1351
1352 static int __init mv_xor_init(void)
1353 {
1354 return platform_driver_register(&mv_xor_driver);
1355 }
1356 module_init(mv_xor_init);
1357
1358 /* it's currently unsafe to unload this module */
1359 #if 0
1360 static void __exit mv_xor_exit(void)
1361 {
1362 platform_driver_unregister(&mv_xor_driver);
1363 return;
1364 }
1365
1366 module_exit(mv_xor_exit);
1367 #endif
1368
1369 MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
1370 MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
1371 MODULE_LICENSE("GPL");
Linux with added FPC-III support