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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / firewire / ohci.c
blob81b45c43a91fac9bb8b80cb9bbe4343b9eb9258f
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/bitops.h>
22 #include <linux/bug.h>
23 #include <linux/compiler.h>
24 #include <linux/delay.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firewire.h>
28 #include <linux/firewire-constants.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/io.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
34 #include <linux/mm.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/string.h>
43 #include <linux/time.h>
44 #include <linux/vmalloc.h>
45 #include <linux/workqueue.h>
46
47 #include <asm/byteorder.h>
48 #include <asm/page.h>
49
50 #ifdef CONFIG_PPC_PMAC
51 #include <asm/pmac_feature.h>
52 #endif
53
54 #include "core.h"
55 #include "ohci.h"
56
57 #define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args)
58 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args)
59 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args)
60
61 #define DESCRIPTOR_OUTPUT_MORE 0
62 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
63 #define DESCRIPTOR_INPUT_MORE (2 << 12)
64 #define DESCRIPTOR_INPUT_LAST (3 << 12)
65 #define DESCRIPTOR_STATUS (1 << 11)
66 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
67 #define DESCRIPTOR_PING (1 << 7)
68 #define DESCRIPTOR_YY (1 << 6)
69 #define DESCRIPTOR_NO_IRQ (0 << 4)
70 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
71 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
72 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
73 #define DESCRIPTOR_WAIT (3 << 0)
74
75 #define DESCRIPTOR_CMD (0xf << 12)
76
77 struct descriptor {
78 __le16 req_count;
79 __le16 control;
80 __le32 data_address;
81 __le32 branch_address;
82 __le16 res_count;
83 __le16 transfer_status;
84 } __attribute__((aligned(16)));
85
86 #define CONTROL_SET(regs) (regs)
87 #define CONTROL_CLEAR(regs) ((regs) + 4)
88 #define COMMAND_PTR(regs) ((regs) + 12)
89 #define CONTEXT_MATCH(regs) ((regs) + 16)
90
91 #define AR_BUFFER_SIZE (32*1024)
92 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
93 /* we need at least two pages for proper list management */
94 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
95
96 #define MAX_ASYNC_PAYLOAD 4096
97 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
98 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
99
100 struct ar_context {
101 struct fw_ohci *ohci;
102 struct page *pages[AR_BUFFERS];
103 void *buffer;
104 struct descriptor *descriptors;
105 dma_addr_t descriptors_bus;
106 void *pointer;
107 unsigned int last_buffer_index;
108 u32 regs;
109 struct tasklet_struct tasklet;
110 };
111
112 struct context;
113
114 typedef int (*descriptor_callback_t)(struct context *ctx,
115 struct descriptor *d,
116 struct descriptor *last);
117
118 /*
119 * A buffer that contains a block of DMA-able coherent memory used for
120 * storing a portion of a DMA descriptor program.
121 */
122 struct descriptor_buffer {
123 struct list_head list;
124 dma_addr_t buffer_bus;
125 size_t buffer_size;
126 size_t used;
127 struct descriptor buffer[0];
128 };
129
130 struct context {
131 struct fw_ohci *ohci;
132 u32 regs;
133 int total_allocation;
134 u32 current_bus;
135 bool running;
136 bool flushing;
137
138 /*
139 * List of page-sized buffers for storing DMA descriptors.
140 * Head of list contains buffers in use and tail of list contains
141 * free buffers.
142 */
143 struct list_head buffer_list;
144
145 /*
146 * Pointer to a buffer inside buffer_list that contains the tail
147 * end of the current DMA program.
148 */
149 struct descriptor_buffer *buffer_tail;
150
151 /*
152 * The descriptor containing the branch address of the first
153 * descriptor that has not yet been filled by the device.
154 */
155 struct descriptor *last;
156
157 /*
158 * The last descriptor block in the DMA program. It contains the branch
159 * address that must be updated upon appending a new descriptor.
160 */
161 struct descriptor *prev;
162 int prev_z;
163
164 descriptor_callback_t callback;
165
166 struct tasklet_struct tasklet;
167 };
168
169 #define IT_HEADER_SY(v) ((v) << 0)
170 #define IT_HEADER_TCODE(v) ((v) << 4)
171 #define IT_HEADER_CHANNEL(v) ((v) << 8)
172 #define IT_HEADER_TAG(v) ((v) << 14)
173 #define IT_HEADER_SPEED(v) ((v) << 16)
174 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
175
176 struct iso_context {
177 struct fw_iso_context base;
178 struct context context;
179 void *header;
180 size_t header_length;
181 unsigned long flushing_completions;
182 u32 mc_buffer_bus;
183 u16 mc_completed;
184 u16 last_timestamp;
185 u8 sync;
186 u8 tags;
187 };
188
189 #define CONFIG_ROM_SIZE 1024
190
191 struct fw_ohci {
192 struct fw_card card;
193
194 __iomem char *registers;
195 int node_id;
196 int generation;
197 int request_generation; /* for timestamping incoming requests */
198 unsigned quirks;
199 unsigned int pri_req_max;
200 u32 bus_time;
201 bool bus_time_running;
202 bool is_root;
203 bool csr_state_setclear_abdicate;
204 int n_ir;
205 int n_it;
206 /*
207 * Spinlock for accessing fw_ohci data. Never call out of
208 * this driver with this lock held.
209 */
210 spinlock_t lock;
211
212 struct mutex phy_reg_mutex;
213
214 void *misc_buffer;
215 dma_addr_t misc_buffer_bus;
216
217 struct ar_context ar_request_ctx;
218 struct ar_context ar_response_ctx;
219 struct context at_request_ctx;
220 struct context at_response_ctx;
221
222 u32 it_context_support;
223 u32 it_context_mask; /* unoccupied IT contexts */
224 struct iso_context *it_context_list;
225 u64 ir_context_channels; /* unoccupied channels */
226 u32 ir_context_support;
227 u32 ir_context_mask; /* unoccupied IR contexts */
228 struct iso_context *ir_context_list;
229 u64 mc_channels; /* channels in use by the multichannel IR context */
230 bool mc_allocated;
231
232 __be32 *config_rom;
233 dma_addr_t config_rom_bus;
234 __be32 *next_config_rom;
235 dma_addr_t next_config_rom_bus;
236 __be32 next_header;
237
238 __le32 *self_id;
239 dma_addr_t self_id_bus;
240 struct work_struct bus_reset_work;
241
242 u32 self_id_buffer[512];
243 };
244
245 static struct workqueue_struct *selfid_workqueue;
246
247 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
248 {
249 return container_of(card, struct fw_ohci, card);
250 }
251
252 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
253 #define IR_CONTEXT_BUFFER_FILL 0x80000000
254 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
255 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
256 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
257 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
258
259 #define CONTEXT_RUN 0x8000
260 #define CONTEXT_WAKE 0x1000
261 #define CONTEXT_DEAD 0x0800
262 #define CONTEXT_ACTIVE 0x0400
263
264 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
265 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
266 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
267
268 #define OHCI1394_REGISTER_SIZE 0x800
269 #define OHCI1394_PCI_HCI_Control 0x40
270 #define SELF_ID_BUF_SIZE 0x800
271 #define OHCI_TCODE_PHY_PACKET 0x0e
272 #define OHCI_VERSION_1_1 0x010010
273
274 static char ohci_driver_name[] = KBUILD_MODNAME;
275
276 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
277 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
278 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001
279 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
280 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
281 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
282 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
283 #define PCI_DEVICE_ID_VIA_VT630X 0x3044
284 #define PCI_REV_ID_VIA_VT6306 0x46
285
286 #define QUIRK_CYCLE_TIMER 0x1
287 #define QUIRK_RESET_PACKET 0x2
288 #define QUIRK_BE_HEADERS 0x4
289 #define QUIRK_NO_1394A 0x8
290 #define QUIRK_NO_MSI 0x10
291 #define QUIRK_TI_SLLZ059 0x20
292 #define QUIRK_IR_WAKE 0x40
293
294 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
295 static const struct {
296 unsigned short vendor, device, revision, flags;
297 } ohci_quirks[] = {
298 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
299 QUIRK_CYCLE_TIMER},
300
301 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
302 QUIRK_BE_HEADERS},
303
304 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
305 QUIRK_NO_MSI},
306
307 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
308 QUIRK_RESET_PACKET},
309
310 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
311 QUIRK_NO_MSI},
312
313 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
314 QUIRK_CYCLE_TIMER},
315
316 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
317 QUIRK_NO_MSI},
318
319 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
320 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
321
322 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
323 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
324
325 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
326 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
327
328 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
329 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
330
331 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
332 QUIRK_RESET_PACKET},
333
334 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
335 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
336
337 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
338 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
339 };
340
341 /* This overrides anything that was found in ohci_quirks[]. */
342 static int param_quirks;
343 module_param_named(quirks, param_quirks, int, 0644);
344 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
345 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
346 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
347 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS)
348 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
349 ", disable MSI = " __stringify(QUIRK_NO_MSI)
350 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
351 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE)
352 ")");
353
354 #define OHCI_PARAM_DEBUG_AT_AR 1
355 #define OHCI_PARAM_DEBUG_SELFIDS 2
356 #define OHCI_PARAM_DEBUG_IRQS 4
357 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
358
359 static int param_debug;
360 module_param_named(debug, param_debug, int, 0644);
361 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
362 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
363 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
364 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
365 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
366 ", or a combination, or all = -1)");
367
368 static void log_irqs(struct fw_ohci *ohci, u32 evt)
369 {
370 if (likely(!(param_debug &
371 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
372 return;
373
374 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
375 !(evt & OHCI1394_busReset))
376 return;
377
378 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
379 evt & OHCI1394_selfIDComplete ? " selfID" : "",
380 evt & OHCI1394_RQPkt ? " AR_req" : "",
381 evt & OHCI1394_RSPkt ? " AR_resp" : "",
382 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
383 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
384 evt & OHCI1394_isochRx ? " IR" : "",
385 evt & OHCI1394_isochTx ? " IT" : "",
386 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
387 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
388 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
389 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
390 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
391 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
392 evt & OHCI1394_busReset ? " busReset" : "",
393 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
394 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
395 OHCI1394_respTxComplete | OHCI1394_isochRx |
396 OHCI1394_isochTx | OHCI1394_postedWriteErr |
397 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
398 OHCI1394_cycleInconsistent |
399 OHCI1394_regAccessFail | OHCI1394_busReset)
400 ? " ?" : "");
401 }
402
403 static const char *speed[] = {
404 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
405 };
406 static const char *power[] = {
407 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
408 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
409 };
410 static const char port[] = { '.', '-', 'p', 'c', };
411
412 static char _p(u32 *s, int shift)
413 {
414 return port[*s >> shift & 3];
415 }
416
417 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
418 {
419 u32 *s;
420
421 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
422 return;
423
424 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
425 self_id_count, generation, ohci->node_id);
426
427 for (s = ohci->self_id_buffer; self_id_count--; ++s)
428 if ((*s & 1 << 23) == 0)
429 ohci_notice(ohci,
430 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
431 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
432 speed[*s >> 14 & 3], *s >> 16 & 63,
433 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
434 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
435 else
436 ohci_notice(ohci,
437 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
438 *s, *s >> 24 & 63,
439 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
440 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
441 }
442
443 static const char *evts[] = {
444 [0x00] = "evt_no_status", [0x01] = "-reserved-",
445 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
446 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
447 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
448 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
449 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
450 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
451 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
452 [0x10] = "-reserved-", [0x11] = "ack_complete",
453 [0x12] = "ack_pending ", [0x13] = "-reserved-",
454 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
455 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
456 [0x18] = "-reserved-", [0x19] = "-reserved-",
457 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
458 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
459 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
460 [0x20] = "pending/cancelled",
461 };
462 static const char *tcodes[] = {
463 [0x0] = "QW req", [0x1] = "BW req",
464 [0x2] = "W resp", [0x3] = "-reserved-",
465 [0x4] = "QR req", [0x5] = "BR req",
466 [0x6] = "QR resp", [0x7] = "BR resp",
467 [0x8] = "cycle start", [0x9] = "Lk req",
468 [0xa] = "async stream packet", [0xb] = "Lk resp",
469 [0xc] = "-reserved-", [0xd] = "-reserved-",
470 [0xe] = "link internal", [0xf] = "-reserved-",
471 };
472
473 static void log_ar_at_event(struct fw_ohci *ohci,
474 char dir, int speed, u32 *header, int evt)
475 {
476 int tcode = header[0] >> 4 & 0xf;
477 char specific[12];
478
479 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
480 return;
481
482 if (unlikely(evt >= ARRAY_SIZE(evts)))
483 evt = 0x1f;
484
485 if (evt == OHCI1394_evt_bus_reset) {
486 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
487 dir, (header[2] >> 16) & 0xff);
488 return;
489 }
490
491 switch (tcode) {
492 case 0x0: case 0x6: case 0x8:
493 snprintf(specific, sizeof(specific), " = %08x",
494 be32_to_cpu((__force __be32)header[3]));
495 break;
496 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
497 snprintf(specific, sizeof(specific), " %x,%x",
498 header[3] >> 16, header[3] & 0xffff);
499 break;
500 default:
501 specific[0] = '\0';
502 }
503
504 switch (tcode) {
505 case 0xa:
506 ohci_notice(ohci, "A%c %s, %s\n",
507 dir, evts[evt], tcodes[tcode]);
508 break;
509 case 0xe:
510 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
511 dir, evts[evt], header[1], header[2]);
512 break;
513 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
514 ohci_notice(ohci,
515 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n",
516 dir, speed, header[0] >> 10 & 0x3f,
517 header[1] >> 16, header[0] >> 16, evts[evt],
518 tcodes[tcode], header[1] & 0xffff, header[2], specific);
519 break;
520 default:
521 ohci_notice(ohci,
522 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
523 dir, speed, header[0] >> 10 & 0x3f,
524 header[1] >> 16, header[0] >> 16, evts[evt],
525 tcodes[tcode], specific);
526 }
527 }
528
529 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
530 {
531 writel(data, ohci->registers + offset);
532 }
533
534 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
535 {
536 return readl(ohci->registers + offset);
537 }
538
539 static inline void flush_writes(const struct fw_ohci *ohci)
540 {
541 /* Do a dummy read to flush writes. */
542 reg_read(ohci, OHCI1394_Version);
543 }
544
545 /*
546 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
547 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
548 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
549 * directly. Exceptions are intrinsically serialized contexts like pci_probe.
550 */
551 static int read_phy_reg(struct fw_ohci *ohci, int addr)
552 {
553 u32 val;
554 int i;
555
556 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
557 for (i = 0; i < 3 + 100; i++) {
558 val = reg_read(ohci, OHCI1394_PhyControl);
559 if (!~val)
560 return -ENODEV; /* Card was ejected. */
561
562 if (val & OHCI1394_PhyControl_ReadDone)
563 return OHCI1394_PhyControl_ReadData(val);
564
565 /*
566 * Try a few times without waiting. Sleeping is necessary
567 * only when the link/PHY interface is busy.
568 */
569 if (i >= 3)
570 msleep(1);
571 }
572 ohci_err(ohci, "failed to read phy reg %d\n", addr);
573 dump_stack();
574
575 return -EBUSY;
576 }
577
578 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
579 {
580 int i;
581
582 reg_write(ohci, OHCI1394_PhyControl,
583 OHCI1394_PhyControl_Write(addr, val));
584 for (i = 0; i < 3 + 100; i++) {
585 val = reg_read(ohci, OHCI1394_PhyControl);
586 if (!~val)
587 return -ENODEV; /* Card was ejected. */
588
589 if (!(val & OHCI1394_PhyControl_WritePending))
590 return 0;
591
592 if (i >= 3)
593 msleep(1);
594 }
595 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
596 dump_stack();
597
598 return -EBUSY;
599 }
600
601 static int update_phy_reg(struct fw_ohci *ohci, int addr,
602 int clear_bits, int set_bits)
603 {
604 int ret = read_phy_reg(ohci, addr);
605 if (ret < 0)
606 return ret;
607
608 /*
609 * The interrupt status bits are cleared by writing a one bit.
610 * Avoid clearing them unless explicitly requested in set_bits.
611 */
612 if (addr == 5)
613 clear_bits |= PHY_INT_STATUS_BITS;
614
615 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
616 }
617
618 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
619 {
620 int ret;
621
622 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
623 if (ret < 0)
624 return ret;
625
626 return read_phy_reg(ohci, addr);
627 }
628
629 static int ohci_read_phy_reg(struct fw_card *card, int addr)
630 {
631 struct fw_ohci *ohci = fw_ohci(card);
632 int ret;
633
634 mutex_lock(&ohci->phy_reg_mutex);
635 ret = read_phy_reg(ohci, addr);
636 mutex_unlock(&ohci->phy_reg_mutex);
637
638 return ret;
639 }
640
641 static int ohci_update_phy_reg(struct fw_card *card, int addr,
642 int clear_bits, int set_bits)
643 {
644 struct fw_ohci *ohci = fw_ohci(card);
645 int ret;
646
647 mutex_lock(&ohci->phy_reg_mutex);
648 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
649 mutex_unlock(&ohci->phy_reg_mutex);
650
651 return ret;
652 }
653
654 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
655 {
656 return page_private(ctx->pages[i]);
657 }
658
659 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
660 {
661 struct descriptor *d;
662
663 d = &ctx->descriptors[index];
664 d->branch_address &= cpu_to_le32(~0xf);
665 d->res_count = cpu_to_le16(PAGE_SIZE);
666 d->transfer_status = 0;
667
668 wmb(); /* finish init of new descriptors before branch_address update */
669 d = &ctx->descriptors[ctx->last_buffer_index];
670 d->branch_address |= cpu_to_le32(1);
671
672 ctx->last_buffer_index = index;
673
674 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
675 }
676
677 static void ar_context_release(struct ar_context *ctx)
678 {
679 unsigned int i;
680
681 if (ctx->buffer)
682 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
683
684 for (i = 0; i < AR_BUFFERS; i++)
685 if (ctx->pages[i]) {
686 dma_unmap_page(ctx->ohci->card.device,
687 ar_buffer_bus(ctx, i),
688 PAGE_SIZE, DMA_FROM_DEVICE);
689 __free_page(ctx->pages[i]);
690 }
691 }
692
693 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
694 {
695 struct fw_ohci *ohci = ctx->ohci;
696
697 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
698 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
699 flush_writes(ohci);
700
701 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
702 }
703 /* FIXME: restart? */
704 }
705
706 static inline unsigned int ar_next_buffer_index(unsigned int index)
707 {
708 return (index + 1) % AR_BUFFERS;
709 }
710
711 static inline unsigned int ar_prev_buffer_index(unsigned int index)
712 {
713 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
714 }
715
716 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
717 {
718 return ar_next_buffer_index(ctx->last_buffer_index);
719 }
720
721 /*
722 * We search for the buffer that contains the last AR packet DMA data written
723 * by the controller.
724 */
725 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
726 unsigned int *buffer_offset)
727 {
728 unsigned int i, next_i, last = ctx->last_buffer_index;
729 __le16 res_count, next_res_count;
730
731 i = ar_first_buffer_index(ctx);
732 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
733
734 /* A buffer that is not yet completely filled must be the last one. */
735 while (i != last && res_count == 0) {
736
737 /* Peek at the next descriptor. */
738 next_i = ar_next_buffer_index(i);
739 rmb(); /* read descriptors in order */
740 next_res_count = ACCESS_ONCE(
741 ctx->descriptors[next_i].res_count);
742 /*
743 * If the next descriptor is still empty, we must stop at this
744 * descriptor.
745 */
746 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
747 /*
748 * The exception is when the DMA data for one packet is
749 * split over three buffers; in this case, the middle
750 * buffer's descriptor might be never updated by the
751 * controller and look still empty, and we have to peek
752 * at the third one.
753 */
754 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
755 next_i = ar_next_buffer_index(next_i);
756 rmb();
757 next_res_count = ACCESS_ONCE(
758 ctx->descriptors[next_i].res_count);
759 if (next_res_count != cpu_to_le16(PAGE_SIZE))
760 goto next_buffer_is_active;
761 }
762
763 break;
764 }
765
766 next_buffer_is_active:
767 i = next_i;
768 res_count = next_res_count;
769 }
770
771 rmb(); /* read res_count before the DMA data */
772
773 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
774 if (*buffer_offset > PAGE_SIZE) {
775 *buffer_offset = 0;
776 ar_context_abort(ctx, "corrupted descriptor");
777 }
778
779 return i;
780 }
781
782 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
783 unsigned int end_buffer_index,
784 unsigned int end_buffer_offset)
785 {
786 unsigned int i;
787
788 i = ar_first_buffer_index(ctx);
789 while (i != end_buffer_index) {
790 dma_sync_single_for_cpu(ctx->ohci->card.device,
791 ar_buffer_bus(ctx, i),
792 PAGE_SIZE, DMA_FROM_DEVICE);
793 i = ar_next_buffer_index(i);
794 }
795 if (end_buffer_offset > 0)
796 dma_sync_single_for_cpu(ctx->ohci->card.device,
797 ar_buffer_bus(ctx, i),
798 end_buffer_offset, DMA_FROM_DEVICE);
799 }
800
801 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
802 #define cond_le32_to_cpu(v) \
803 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
804 #else
805 #define cond_le32_to_cpu(v) le32_to_cpu(v)
806 #endif
807
808 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
809 {
810 struct fw_ohci *ohci = ctx->ohci;
811 struct fw_packet p;
812 u32 status, length, tcode;
813 int evt;
814
815 p.header[0] = cond_le32_to_cpu(buffer[0]);
816 p.header[1] = cond_le32_to_cpu(buffer[1]);
817 p.header[2] = cond_le32_to_cpu(buffer[2]);
818
819 tcode = (p.header[0] >> 4) & 0x0f;
820 switch (tcode) {
821 case TCODE_WRITE_QUADLET_REQUEST:
822 case TCODE_READ_QUADLET_RESPONSE:
823 p.header[3] = (__force __u32) buffer[3];
824 p.header_length = 16;
825 p.payload_length = 0;
826 break;
827
828 case TCODE_READ_BLOCK_REQUEST :
829 p.header[3] = cond_le32_to_cpu(buffer[3]);
830 p.header_length = 16;
831 p.payload_length = 0;
832 break;
833
834 case TCODE_WRITE_BLOCK_REQUEST:
835 case TCODE_READ_BLOCK_RESPONSE:
836 case TCODE_LOCK_REQUEST:
837 case TCODE_LOCK_RESPONSE:
838 p.header[3] = cond_le32_to_cpu(buffer[3]);
839 p.header_length = 16;
840 p.payload_length = p.header[3] >> 16;
841 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
842 ar_context_abort(ctx, "invalid packet length");
843 return NULL;
844 }
845 break;
846
847 case TCODE_WRITE_RESPONSE:
848 case TCODE_READ_QUADLET_REQUEST:
849 case OHCI_TCODE_PHY_PACKET:
850 p.header_length = 12;
851 p.payload_length = 0;
852 break;
853
854 default:
855 ar_context_abort(ctx, "invalid tcode");
856 return NULL;
857 }
858
859 p.payload = (void *) buffer + p.header_length;
860
861 /* FIXME: What to do about evt_* errors? */
862 length = (p.header_length + p.payload_length + 3) / 4;
863 status = cond_le32_to_cpu(buffer[length]);
864 evt = (status >> 16) & 0x1f;
865
866 p.ack = evt - 16;
867 p.speed = (status >> 21) & 0x7;
868 p.timestamp = status & 0xffff;
869 p.generation = ohci->request_generation;
870
871 log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
872
873 /*
874 * Several controllers, notably from NEC and VIA, forget to
875 * write ack_complete status at PHY packet reception.
876 */
877 if (evt == OHCI1394_evt_no_status &&
878 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
879 p.ack = ACK_COMPLETE;
880
881 /*
882 * The OHCI bus reset handler synthesizes a PHY packet with
883 * the new generation number when a bus reset happens (see
884 * section 8.4.2.3). This helps us determine when a request
885 * was received and make sure we send the response in the same
886 * generation. We only need this for requests; for responses
887 * we use the unique tlabel for finding the matching
888 * request.
889 *
890 * Alas some chips sometimes emit bus reset packets with a
891 * wrong generation. We set the correct generation for these
892 * at a slightly incorrect time (in bus_reset_work).
893 */
894 if (evt == OHCI1394_evt_bus_reset) {
895 if (!(ohci->quirks & QUIRK_RESET_PACKET))
896 ohci->request_generation = (p.header[2] >> 16) & 0xff;
897 } else if (ctx == &ohci->ar_request_ctx) {
898 fw_core_handle_request(&ohci->card, &p);
899 } else {
900 fw_core_handle_response(&ohci->card, &p);
901 }
902
903 return buffer + length + 1;
904 }
905
906 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
907 {
908 void *next;
909
910 while (p < end) {
911 next = handle_ar_packet(ctx, p);
912 if (!next)
913 return p;
914 p = next;
915 }
916
917 return p;
918 }
919
920 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
921 {
922 unsigned int i;
923
924 i = ar_first_buffer_index(ctx);
925 while (i != end_buffer) {
926 dma_sync_single_for_device(ctx->ohci->card.device,
927 ar_buffer_bus(ctx, i),
928 PAGE_SIZE, DMA_FROM_DEVICE);
929 ar_context_link_page(ctx, i);
930 i = ar_next_buffer_index(i);
931 }
932 }
933
934 static void ar_context_tasklet(unsigned long data)
935 {
936 struct ar_context *ctx = (struct ar_context *)data;
937 unsigned int end_buffer_index, end_buffer_offset;
938 void *p, *end;
939
940 p = ctx->pointer;
941 if (!p)
942 return;
943
944 end_buffer_index = ar_search_last_active_buffer(ctx,
945 &end_buffer_offset);
946 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
947 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
948
949 if (end_buffer_index < ar_first_buffer_index(ctx)) {
950 /*
951 * The filled part of the overall buffer wraps around; handle
952 * all packets up to the buffer end here. If the last packet
953 * wraps around, its tail will be visible after the buffer end
954 * because the buffer start pages are mapped there again.
955 */
956 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
957 p = handle_ar_packets(ctx, p, buffer_end);
958 if (p < buffer_end)
959 goto error;
960 /* adjust p to point back into the actual buffer */
961 p -= AR_BUFFERS * PAGE_SIZE;
962 }
963
964 p = handle_ar_packets(ctx, p, end);
965 if (p != end) {
966 if (p > end)
967 ar_context_abort(ctx, "inconsistent descriptor");
968 goto error;
969 }
970
971 ctx->pointer = p;
972 ar_recycle_buffers(ctx, end_buffer_index);
973
974 return;
975
976 error:
977 ctx->pointer = NULL;
978 }
979
980 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
981 unsigned int descriptors_offset, u32 regs)
982 {
983 unsigned int i;
984 dma_addr_t dma_addr;
985 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
986 struct descriptor *d;
987
988 ctx->regs = regs;
989 ctx->ohci = ohci;
990 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
991
992 for (i = 0; i < AR_BUFFERS; i++) {
993 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
994 if (!ctx->pages[i])
995 goto out_of_memory;
996 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
997 0, PAGE_SIZE, DMA_FROM_DEVICE);
998 if (dma_mapping_error(ohci->card.device, dma_addr)) {
999 __free_page(ctx->pages[i]);
1000 ctx->pages[i] = NULL;
1001 goto out_of_memory;
1002 }
1003 set_page_private(ctx->pages[i], dma_addr);
1004 }
1005
1006 for (i = 0; i < AR_BUFFERS; i++)
1007 pages[i] = ctx->pages[i];
1008 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1009 pages[AR_BUFFERS + i] = ctx->pages[i];
1010 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
1011 -1, PAGE_KERNEL);
1012 if (!ctx->buffer)
1013 goto out_of_memory;
1014
1015 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
1016 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1017
1018 for (i = 0; i < AR_BUFFERS; i++) {
1019 d = &ctx->descriptors[i];
1020 d->req_count = cpu_to_le16(PAGE_SIZE);
1021 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1022 DESCRIPTOR_STATUS |
1023 DESCRIPTOR_BRANCH_ALWAYS);
1024 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
1025 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1026 ar_next_buffer_index(i) * sizeof(struct descriptor));
1027 }
1028
1029 return 0;
1030
1031 out_of_memory:
1032 ar_context_release(ctx);
1033
1034 return -ENOMEM;
1035 }
1036
1037 static void ar_context_run(struct ar_context *ctx)
1038 {
1039 unsigned int i;
1040
1041 for (i = 0; i < AR_BUFFERS; i++)
1042 ar_context_link_page(ctx, i);
1043
1044 ctx->pointer = ctx->buffer;
1045
1046 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1047 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1048 }
1049
1050 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1051 {
1052 __le16 branch;
1053
1054 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1055
1056 /* figure out which descriptor the branch address goes in */
1057 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1058 return d;
1059 else
1060 return d + z - 1;
1061 }
1062
1063 static void context_tasklet(unsigned long data)
1064 {
1065 struct context *ctx = (struct context *) data;
1066 struct descriptor *d, *last;
1067 u32 address;
1068 int z;
1069 struct descriptor_buffer *desc;
1070
1071 desc = list_entry(ctx->buffer_list.next,
1072 struct descriptor_buffer, list);
1073 last = ctx->last;
1074 while (last->branch_address != 0) {
1075 struct descriptor_buffer *old_desc = desc;
1076 address = le32_to_cpu(last->branch_address);
1077 z = address & 0xf;
1078 address &= ~0xf;
1079 ctx->current_bus = address;
1080
1081 /* If the branch address points to a buffer outside of the
1082 * current buffer, advance to the next buffer. */
1083 if (address < desc->buffer_bus ||
1084 address >= desc->buffer_bus + desc->used)
1085 desc = list_entry(desc->list.next,
1086 struct descriptor_buffer, list);
1087 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1088 last = find_branch_descriptor(d, z);
1089
1090 if (!ctx->callback(ctx, d, last))
1091 break;
1092
1093 if (old_desc != desc) {
1094 /* If we've advanced to the next buffer, move the
1095 * previous buffer to the free list. */
1096 unsigned long flags;
1097 old_desc->used = 0;
1098 spin_lock_irqsave(&ctx->ohci->lock, flags);
1099 list_move_tail(&old_desc->list, &ctx->buffer_list);
1100 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1101 }
1102 ctx->last = last;
1103 }
1104 }
1105
1106 /*
1107 * Allocate a new buffer and add it to the list of free buffers for this
1108 * context. Must be called with ohci->lock held.
1109 */
1110 static int context_add_buffer(struct context *ctx)
1111 {
1112 struct descriptor_buffer *desc;
1113 dma_addr_t uninitialized_var(bus_addr);
1114 int offset;
1115
1116 /*
1117 * 16MB of descriptors should be far more than enough for any DMA
1118 * program. This will catch run-away userspace or DoS attacks.
1119 */
1120 if (ctx->total_allocation >= 16*1024*1024)
1121 return -ENOMEM;
1122
1123 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1124 &bus_addr, GFP_ATOMIC);
1125 if (!desc)
1126 return -ENOMEM;
1127
1128 offset = (void *)&desc->buffer - (void *)desc;
1129 desc->buffer_size = PAGE_SIZE - offset;
1130 desc->buffer_bus = bus_addr + offset;
1131 desc->used = 0;
1132
1133 list_add_tail(&desc->list, &ctx->buffer_list);
1134 ctx->total_allocation += PAGE_SIZE;
1135
1136 return 0;
1137 }
1138
1139 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1140 u32 regs, descriptor_callback_t callback)
1141 {
1142 ctx->ohci = ohci;
1143 ctx->regs = regs;
1144 ctx->total_allocation = 0;
1145
1146 INIT_LIST_HEAD(&ctx->buffer_list);
1147 if (context_add_buffer(ctx) < 0)
1148 return -ENOMEM;
1149
1150 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1151 struct descriptor_buffer, list);
1152
1153 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1154 ctx->callback = callback;
1155
1156 /*
1157 * We put a dummy descriptor in the buffer that has a NULL
1158 * branch address and looks like it's been sent. That way we
1159 * have a descriptor to append DMA programs to.
1160 */
1161 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1162 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1163 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1164 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1165 ctx->last = ctx->buffer_tail->buffer;
1166 ctx->prev = ctx->buffer_tail->buffer;
1167 ctx->prev_z = 1;
1168
1169 return 0;
1170 }
1171
1172 static void context_release(struct context *ctx)
1173 {
1174 struct fw_card *card = &ctx->ohci->card;
1175 struct descriptor_buffer *desc, *tmp;
1176
1177 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1178 dma_free_coherent(card->device, PAGE_SIZE, desc,
1179 desc->buffer_bus -
1180 ((void *)&desc->buffer - (void *)desc));
1181 }
1182
1183 /* Must be called with ohci->lock held */
1184 static struct descriptor *context_get_descriptors(struct context *ctx,
1185 int z, dma_addr_t *d_bus)
1186 {
1187 struct descriptor *d = NULL;
1188 struct descriptor_buffer *desc = ctx->buffer_tail;
1189
1190 if (z * sizeof(*d) > desc->buffer_size)
1191 return NULL;
1192
1193 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1194 /* No room for the descriptor in this buffer, so advance to the
1195 * next one. */
1196
1197 if (desc->list.next == &ctx->buffer_list) {
1198 /* If there is no free buffer next in the list,
1199 * allocate one. */
1200 if (context_add_buffer(ctx) < 0)
1201 return NULL;
1202 }
1203 desc = list_entry(desc->list.next,
1204 struct descriptor_buffer, list);
1205 ctx->buffer_tail = desc;
1206 }
1207
1208 d = desc->buffer + desc->used / sizeof(*d);
1209 memset(d, 0, z * sizeof(*d));
1210 *d_bus = desc->buffer_bus + desc->used;
1211
1212 return d;
1213 }
1214
1215 static void context_run(struct context *ctx, u32 extra)
1216 {
1217 struct fw_ohci *ohci = ctx->ohci;
1218
1219 reg_write(ohci, COMMAND_PTR(ctx->regs),
1220 le32_to_cpu(ctx->last->branch_address));
1221 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1222 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1223 ctx->running = true;
1224 flush_writes(ohci);
1225 }
1226
1227 static void context_append(struct context *ctx,
1228 struct descriptor *d, int z, int extra)
1229 {
1230 dma_addr_t d_bus;
1231 struct descriptor_buffer *desc = ctx->buffer_tail;
1232 struct descriptor *d_branch;
1233
1234 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1235
1236 desc->used += (z + extra) * sizeof(*d);
1237
1238 wmb(); /* finish init of new descriptors before branch_address update */
1239
1240 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
1241 d_branch->branch_address = cpu_to_le32(d_bus | z);
1242
1243 /*
1244 * VT6306 incorrectly checks only the single descriptor at the
1245 * CommandPtr when the wake bit is written, so if it's a
1246 * multi-descriptor block starting with an INPUT_MORE, put a copy of
1247 * the branch address in the first descriptor.
1248 *
1249 * Not doing this for transmit contexts since not sure how it interacts
1250 * with skip addresses.
1251 */
1252 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
1253 d_branch != ctx->prev &&
1254 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
1255 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
1256 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1257 }
1258
1259 ctx->prev = d;
1260 ctx->prev_z = z;
1261 }
1262
1263 static void context_stop(struct context *ctx)
1264 {
1265 struct fw_ohci *ohci = ctx->ohci;
1266 u32 reg;
1267 int i;
1268
1269 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1270 ctx->running = false;
1271
1272 for (i = 0; i < 1000; i++) {
1273 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1274 if ((reg & CONTEXT_ACTIVE) == 0)
1275 return;
1276
1277 if (i)
1278 udelay(10);
1279 }
1280 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
1281 }
1282
1283 struct driver_data {
1284 u8 inline_data[8];
1285 struct fw_packet *packet;
1286 };
1287
1288 /*
1289 * This function apppends a packet to the DMA queue for transmission.
1290 * Must always be called with the ochi->lock held to ensure proper
1291 * generation handling and locking around packet queue manipulation.
1292 */
1293 static int at_context_queue_packet(struct context *ctx,
1294 struct fw_packet *packet)
1295 {
1296 struct fw_ohci *ohci = ctx->ohci;
1297 dma_addr_t d_bus, uninitialized_var(payload_bus);
1298 struct driver_data *driver_data;
1299 struct descriptor *d, *last;
1300 __le32 *header;
1301 int z, tcode;
1302
1303 d = context_get_descriptors(ctx, 4, &d_bus);
1304 if (d == NULL) {
1305 packet->ack = RCODE_SEND_ERROR;
1306 return -1;
1307 }
1308
1309 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1310 d[0].res_count = cpu_to_le16(packet->timestamp);
1311
1312 /*
1313 * The DMA format for asynchronous link packets is different
1314 * from the IEEE1394 layout, so shift the fields around
1315 * accordingly.
1316 */
1317
1318 tcode = (packet->header[0] >> 4) & 0x0f;
1319 header = (__le32 *) &d[1];
1320 switch (tcode) {
1321 case TCODE_WRITE_QUADLET_REQUEST:
1322 case TCODE_WRITE_BLOCK_REQUEST:
1323 case TCODE_WRITE_RESPONSE:
1324 case TCODE_READ_QUADLET_REQUEST:
1325 case TCODE_READ_BLOCK_REQUEST:
1326 case TCODE_READ_QUADLET_RESPONSE:
1327 case TCODE_READ_BLOCK_RESPONSE:
1328 case TCODE_LOCK_REQUEST:
1329 case TCODE_LOCK_RESPONSE:
1330 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1331 (packet->speed << 16));
1332 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1333 (packet->header[0] & 0xffff0000));
1334 header[2] = cpu_to_le32(packet->header[2]);
1335
1336 if (TCODE_IS_BLOCK_PACKET(tcode))
1337 header[3] = cpu_to_le32(packet->header[3]);
1338 else
1339 header[3] = (__force __le32) packet->header[3];
1340
1341 d[0].req_count = cpu_to_le16(packet->header_length);
1342 break;
1343
1344 case TCODE_LINK_INTERNAL:
1345 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1346 (packet->speed << 16));
1347 header[1] = cpu_to_le32(packet->header[1]);
1348 header[2] = cpu_to_le32(packet->header[2]);
1349 d[0].req_count = cpu_to_le16(12);
1350
1351 if (is_ping_packet(&packet->header[1]))
1352 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1353 break;
1354
1355 case TCODE_STREAM_DATA:
1356 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1357 (packet->speed << 16));
1358 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1359 d[0].req_count = cpu_to_le16(8);
1360 break;
1361
1362 default:
1363 /* BUG(); */
1364 packet->ack = RCODE_SEND_ERROR;
1365 return -1;
1366 }
1367
1368 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1369 driver_data = (struct driver_data *) &d[3];
1370 driver_data->packet = packet;
1371 packet->driver_data = driver_data;
1372
1373 if (packet->payload_length > 0) {
1374 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1375 payload_bus = dma_map_single(ohci->card.device,
1376 packet->payload,
1377 packet->payload_length,
1378 DMA_TO_DEVICE);
1379 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1380 packet->ack = RCODE_SEND_ERROR;
1381 return -1;
1382 }
1383 packet->payload_bus = payload_bus;
1384 packet->payload_mapped = true;
1385 } else {
1386 memcpy(driver_data->inline_data, packet->payload,
1387 packet->payload_length);
1388 payload_bus = d_bus + 3 * sizeof(*d);
1389 }
1390
1391 d[2].req_count = cpu_to_le16(packet->payload_length);
1392 d[2].data_address = cpu_to_le32(payload_bus);
1393 last = &d[2];
1394 z = 3;
1395 } else {
1396 last = &d[0];
1397 z = 2;
1398 }
1399
1400 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1401 DESCRIPTOR_IRQ_ALWAYS |
1402 DESCRIPTOR_BRANCH_ALWAYS);
1403
1404 /* FIXME: Document how the locking works. */
1405 if (ohci->generation != packet->generation) {
1406 if (packet->payload_mapped)
1407 dma_unmap_single(ohci->card.device, payload_bus,
1408 packet->payload_length, DMA_TO_DEVICE);
1409 packet->ack = RCODE_GENERATION;
1410 return -1;
1411 }
1412
1413 context_append(ctx, d, z, 4 - z);
1414
1415 if (ctx->running)
1416 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1417 else
1418 context_run(ctx, 0);
1419
1420 return 0;
1421 }
1422
1423 static void at_context_flush(struct context *ctx)
1424 {
1425 tasklet_disable(&ctx->tasklet);
1426
1427 ctx->flushing = true;
1428 context_tasklet((unsigned long)ctx);
1429 ctx->flushing = false;
1430
1431 tasklet_enable(&ctx->tasklet);
1432 }
1433
1434 static int handle_at_packet(struct context *context,
1435 struct descriptor *d,
1436 struct descriptor *last)
1437 {
1438 struct driver_data *driver_data;
1439 struct fw_packet *packet;
1440 struct fw_ohci *ohci = context->ohci;
1441 int evt;
1442
1443 if (last->transfer_status == 0 && !context->flushing)
1444 /* This descriptor isn't done yet, stop iteration. */
1445 return 0;
1446
1447 driver_data = (struct driver_data *) &d[3];
1448 packet = driver_data->packet;
1449 if (packet == NULL)
1450 /* This packet was cancelled, just continue. */
1451 return 1;
1452
1453 if (packet->payload_mapped)
1454 dma_unmap_single(ohci->card.device, packet->payload_bus,
1455 packet->payload_length, DMA_TO_DEVICE);
1456
1457 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1458 packet->timestamp = le16_to_cpu(last->res_count);
1459
1460 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1461
1462 switch (evt) {
1463 case OHCI1394_evt_timeout:
1464 /* Async response transmit timed out. */
1465 packet->ack = RCODE_CANCELLED;
1466 break;
1467
1468 case OHCI1394_evt_flushed:
1469 /*
1470 * The packet was flushed should give same error as
1471 * when we try to use a stale generation count.
1472 */
1473 packet->ack = RCODE_GENERATION;
1474 break;
1475
1476 case OHCI1394_evt_missing_ack:
1477 if (context->flushing)
1478 packet->ack = RCODE_GENERATION;
1479 else {
1480 /*
1481 * Using a valid (current) generation count, but the
1482 * node is not on the bus or not sending acks.
1483 */
1484 packet->ack = RCODE_NO_ACK;
1485 }
1486 break;
1487
1488 case ACK_COMPLETE + 0x10:
1489 case ACK_PENDING + 0x10:
1490 case ACK_BUSY_X + 0x10:
1491 case ACK_BUSY_A + 0x10:
1492 case ACK_BUSY_B + 0x10:
1493 case ACK_DATA_ERROR + 0x10:
1494 case ACK_TYPE_ERROR + 0x10:
1495 packet->ack = evt - 0x10;
1496 break;
1497
1498 case OHCI1394_evt_no_status:
1499 if (context->flushing) {
1500 packet->ack = RCODE_GENERATION;
1501 break;
1502 }
1503 /* fall through */
1504
1505 default:
1506 packet->ack = RCODE_SEND_ERROR;
1507 break;
1508 }
1509
1510 packet->callback(packet, &ohci->card, packet->ack);
1511
1512 return 1;
1513 }
1514
1515 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1516 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1517 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1518 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1519 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1520
1521 static void handle_local_rom(struct fw_ohci *ohci,
1522 struct fw_packet *packet, u32 csr)
1523 {
1524 struct fw_packet response;
1525 int tcode, length, i;
1526
1527 tcode = HEADER_GET_TCODE(packet->header[0]);
1528 if (TCODE_IS_BLOCK_PACKET(tcode))
1529 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1530 else
1531 length = 4;
1532
1533 i = csr - CSR_CONFIG_ROM;
1534 if (i + length > CONFIG_ROM_SIZE) {
1535 fw_fill_response(&response, packet->header,
1536 RCODE_ADDRESS_ERROR, NULL, 0);
1537 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1538 fw_fill_response(&response, packet->header,
1539 RCODE_TYPE_ERROR, NULL, 0);
1540 } else {
1541 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1542 (void *) ohci->config_rom + i, length);
1543 }
1544
1545 fw_core_handle_response(&ohci->card, &response);
1546 }
1547
1548 static void handle_local_lock(struct fw_ohci *ohci,
1549 struct fw_packet *packet, u32 csr)
1550 {
1551 struct fw_packet response;
1552 int tcode, length, ext_tcode, sel, try;
1553 __be32 *payload, lock_old;
1554 u32 lock_arg, lock_data;
1555
1556 tcode = HEADER_GET_TCODE(packet->header[0]);
1557 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1558 payload = packet->payload;
1559 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1560
1561 if (tcode == TCODE_LOCK_REQUEST &&
1562 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1563 lock_arg = be32_to_cpu(payload[0]);
1564 lock_data = be32_to_cpu(payload[1]);
1565 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1566 lock_arg = 0;
1567 lock_data = 0;
1568 } else {
1569 fw_fill_response(&response, packet->header,
1570 RCODE_TYPE_ERROR, NULL, 0);
1571 goto out;
1572 }
1573
1574 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1575 reg_write(ohci, OHCI1394_CSRData, lock_data);
1576 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1577 reg_write(ohci, OHCI1394_CSRControl, sel);
1578
1579 for (try = 0; try < 20; try++)
1580 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1581 lock_old = cpu_to_be32(reg_read(ohci,
1582 OHCI1394_CSRData));
1583 fw_fill_response(&response, packet->header,
1584 RCODE_COMPLETE,
1585 &lock_old, sizeof(lock_old));
1586 goto out;
1587 }
1588
1589 ohci_err(ohci, "swap not done (CSR lock timeout)\n");
1590 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1591
1592 out:
1593 fw_core_handle_response(&ohci->card, &response);
1594 }
1595
1596 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1597 {
1598 u64 offset, csr;
1599
1600 if (ctx == &ctx->ohci->at_request_ctx) {
1601 packet->ack = ACK_PENDING;
1602 packet->callback(packet, &ctx->ohci->card, packet->ack);
1603 }
1604
1605 offset =
1606 ((unsigned long long)
1607 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1608 packet->header[2];
1609 csr = offset - CSR_REGISTER_BASE;
1610
1611 /* Handle config rom reads. */
1612 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1613 handle_local_rom(ctx->ohci, packet, csr);
1614 else switch (csr) {
1615 case CSR_BUS_MANAGER_ID:
1616 case CSR_BANDWIDTH_AVAILABLE:
1617 case CSR_CHANNELS_AVAILABLE_HI:
1618 case CSR_CHANNELS_AVAILABLE_LO:
1619 handle_local_lock(ctx->ohci, packet, csr);
1620 break;
1621 default:
1622 if (ctx == &ctx->ohci->at_request_ctx)
1623 fw_core_handle_request(&ctx->ohci->card, packet);
1624 else
1625 fw_core_handle_response(&ctx->ohci->card, packet);
1626 break;
1627 }
1628
1629 if (ctx == &ctx->ohci->at_response_ctx) {
1630 packet->ack = ACK_COMPLETE;
1631 packet->callback(packet, &ctx->ohci->card, packet->ack);
1632 }
1633 }
1634
1635 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1636 {
1637 unsigned long flags;
1638 int ret;
1639
1640 spin_lock_irqsave(&ctx->ohci->lock, flags);
1641
1642 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1643 ctx->ohci->generation == packet->generation) {
1644 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1645 handle_local_request(ctx, packet);
1646 return;
1647 }
1648
1649 ret = at_context_queue_packet(ctx, packet);
1650 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1651
1652 if (ret < 0)
1653 packet->callback(packet, &ctx->ohci->card, packet->ack);
1654
1655 }
1656
1657 static void detect_dead_context(struct fw_ohci *ohci,
1658 const char *name, unsigned int regs)
1659 {
1660 u32 ctl;
1661
1662 ctl = reg_read(ohci, CONTROL_SET(regs));
1663 if (ctl & CONTEXT_DEAD)
1664 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
1665 name, evts[ctl & 0x1f]);
1666 }
1667
1668 static void handle_dead_contexts(struct fw_ohci *ohci)
1669 {
1670 unsigned int i;
1671 char name[8];
1672
1673 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1674 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1675 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1676 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1677 for (i = 0; i < 32; ++i) {
1678 if (!(ohci->it_context_support & (1 << i)))
1679 continue;
1680 sprintf(name, "IT%u", i);
1681 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1682 }
1683 for (i = 0; i < 32; ++i) {
1684 if (!(ohci->ir_context_support & (1 << i)))
1685 continue;
1686 sprintf(name, "IR%u", i);
1687 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1688 }
1689 /* TODO: maybe try to flush and restart the dead contexts */
1690 }
1691
1692 static u32 cycle_timer_ticks(u32 cycle_timer)
1693 {
1694 u32 ticks;
1695
1696 ticks = cycle_timer & 0xfff;
1697 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1698 ticks += (3072 * 8000) * (cycle_timer >> 25);
1699
1700 return ticks;
1701 }
1702
1703 /*
1704 * Some controllers exhibit one or more of the following bugs when updating the
1705 * iso cycle timer register:
1706 * - When the lowest six bits are wrapping around to zero, a read that happens
1707 * at the same time will return garbage in the lowest ten bits.
1708 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1709 * not incremented for about 60 ns.
1710 * - Occasionally, the entire register reads zero.
1711 *
1712 * To catch these, we read the register three times and ensure that the
1713 * difference between each two consecutive reads is approximately the same, i.e.
1714 * less than twice the other. Furthermore, any negative difference indicates an
1715 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1716 * execute, so we have enough precision to compute the ratio of the differences.)
1717 */
1718 static u32 get_cycle_time(struct fw_ohci *ohci)
1719 {
1720 u32 c0, c1, c2;
1721 u32 t0, t1, t2;
1722 s32 diff01, diff12;
1723 int i;
1724
1725 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1726
1727 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1728 i = 0;
1729 c1 = c2;
1730 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1731 do {
1732 c0 = c1;
1733 c1 = c2;
1734 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1735 t0 = cycle_timer_ticks(c0);
1736 t1 = cycle_timer_ticks(c1);
1737 t2 = cycle_timer_ticks(c2);
1738 diff01 = t1 - t0;
1739 diff12 = t2 - t1;
1740 } while ((diff01 <= 0 || diff12 <= 0 ||
1741 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1742 && i++ < 20);
1743 }
1744
1745 return c2;
1746 }
1747
1748 /*
1749 * This function has to be called at least every 64 seconds. The bus_time
1750 * field stores not only the upper 25 bits of the BUS_TIME register but also
1751 * the most significant bit of the cycle timer in bit 6 so that we can detect
1752 * changes in this bit.
1753 */
1754 static u32 update_bus_time(struct fw_ohci *ohci)
1755 {
1756 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1757
1758 if (unlikely(!ohci->bus_time_running)) {
1759 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1760 ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
1761 (cycle_time_seconds & 0x40);
1762 ohci->bus_time_running = true;
1763 }
1764
1765 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1766 ohci->bus_time += 0x40;
1767
1768 return ohci->bus_time | cycle_time_seconds;
1769 }
1770
1771 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1772 {
1773 int reg;
1774
1775 mutex_lock(&ohci->phy_reg_mutex);
1776 reg = write_phy_reg(ohci, 7, port_index);
1777 if (reg >= 0)
1778 reg = read_phy_reg(ohci, 8);
1779 mutex_unlock(&ohci->phy_reg_mutex);
1780 if (reg < 0)
1781 return reg;
1782
1783 switch (reg & 0x0f) {
1784 case 0x06:
1785 return 2; /* is child node (connected to parent node) */
1786 case 0x0e:
1787 return 3; /* is parent node (connected to child node) */
1788 }
1789 return 1; /* not connected */
1790 }
1791
1792 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1793 int self_id_count)
1794 {
1795 int i;
1796 u32 entry;
1797
1798 for (i = 0; i < self_id_count; i++) {
1799 entry = ohci->self_id_buffer[i];
1800 if ((self_id & 0xff000000) == (entry & 0xff000000))
1801 return -1;
1802 if ((self_id & 0xff000000) < (entry & 0xff000000))
1803 return i;
1804 }
1805 return i;
1806 }
1807
1808 static int initiated_reset(struct fw_ohci *ohci)
1809 {
1810 int reg;
1811 int ret = 0;
1812
1813 mutex_lock(&ohci->phy_reg_mutex);
1814 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
1815 if (reg >= 0) {
1816 reg = read_phy_reg(ohci, 8);
1817 reg |= 0x40;
1818 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
1819 if (reg >= 0) {
1820 reg = read_phy_reg(ohci, 12); /* read register 12 */
1821 if (reg >= 0) {
1822 if ((reg & 0x08) == 0x08) {
1823 /* bit 3 indicates "initiated reset" */
1824 ret = 0x2;
1825 }
1826 }
1827 }
1828 }
1829 mutex_unlock(&ohci->phy_reg_mutex);
1830 return ret;
1831 }
1832
1833 /*
1834 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1835 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1836 * Construct the selfID from phy register contents.
1837 */
1838 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1839 {
1840 int reg, i, pos, status;
1841 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1842 u32 self_id = 0x8040c800;
1843
1844 reg = reg_read(ohci, OHCI1394_NodeID);
1845 if (!(reg & OHCI1394_NodeID_idValid)) {
1846 ohci_notice(ohci,
1847 "node ID not valid, new bus reset in progress\n");
1848 return -EBUSY;
1849 }
1850 self_id |= ((reg & 0x3f) << 24); /* phy ID */
1851
1852 reg = ohci_read_phy_reg(&ohci->card, 4);
1853 if (reg < 0)
1854 return reg;
1855 self_id |= ((reg & 0x07) << 8); /* power class */
1856
1857 reg = ohci_read_phy_reg(&ohci->card, 1);
1858 if (reg < 0)
1859 return reg;
1860 self_id |= ((reg & 0x3f) << 16); /* gap count */
1861
1862 for (i = 0; i < 3; i++) {
1863 status = get_status_for_port(ohci, i);
1864 if (status < 0)
1865 return status;
1866 self_id |= ((status & 0x3) << (6 - (i * 2)));
1867 }
1868
1869 self_id |= initiated_reset(ohci);
1870
1871 pos = get_self_id_pos(ohci, self_id, self_id_count);
1872 if (pos >= 0) {
1873 memmove(&(ohci->self_id_buffer[pos+1]),
1874 &(ohci->self_id_buffer[pos]),
1875 (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1876 ohci->self_id_buffer[pos] = self_id;
1877 self_id_count++;
1878 }
1879 return self_id_count;
1880 }
1881
1882 static void bus_reset_work(struct work_struct *work)
1883 {
1884 struct fw_ohci *ohci =
1885 container_of(work, struct fw_ohci, bus_reset_work);
1886 int self_id_count, generation, new_generation, i, j;
1887 u32 reg;
1888 void *free_rom = NULL;
1889 dma_addr_t free_rom_bus = 0;
1890 bool is_new_root;
1891
1892 reg = reg_read(ohci, OHCI1394_NodeID);
1893 if (!(reg & OHCI1394_NodeID_idValid)) {
1894 ohci_notice(ohci,
1895 "node ID not valid, new bus reset in progress\n");
1896 return;
1897 }
1898 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1899 ohci_notice(ohci, "malconfigured bus\n");
1900 return;
1901 }
1902 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1903 OHCI1394_NodeID_nodeNumber);
1904
1905 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1906 if (!(ohci->is_root && is_new_root))
1907 reg_write(ohci, OHCI1394_LinkControlSet,
1908 OHCI1394_LinkControl_cycleMaster);
1909 ohci->is_root = is_new_root;
1910
1911 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1912 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1913 ohci_notice(ohci, "self ID receive error\n");
1914 return;
1915 }
1916 /*
1917 * The count in the SelfIDCount register is the number of
1918 * bytes in the self ID receive buffer. Since we also receive
1919 * the inverted quadlets and a header quadlet, we shift one
1920 * bit extra to get the actual number of self IDs.
1921 */
1922 self_id_count = (reg >> 3) & 0xff;
1923
1924 if (self_id_count > 252) {
1925 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
1926 return;
1927 }
1928
1929 generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff;
1930 rmb();
1931
1932 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1933 u32 id = cond_le32_to_cpu(ohci->self_id[i]);
1934 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]);
1935
1936 if (id != ~id2) {
1937 /*
1938 * If the invalid data looks like a cycle start packet,
1939 * it's likely to be the result of the cycle master
1940 * having a wrong gap count. In this case, the self IDs
1941 * so far are valid and should be processed so that the
1942 * bus manager can then correct the gap count.
1943 */
1944 if (id == 0xffff008f) {
1945 ohci_notice(ohci, "ignoring spurious self IDs\n");
1946 self_id_count = j;
1947 break;
1948 }
1949
1950 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
1951 j, self_id_count, id, id2);
1952 return;
1953 }
1954 ohci->self_id_buffer[j] = id;
1955 }
1956
1957 if (ohci->quirks & QUIRK_TI_SLLZ059) {
1958 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1959 if (self_id_count < 0) {
1960 ohci_notice(ohci,
1961 "could not construct local self ID\n");
1962 return;
1963 }
1964 }
1965
1966 if (self_id_count == 0) {
1967 ohci_notice(ohci, "no self IDs\n");
1968 return;
1969 }
1970 rmb();
1971
1972 /*
1973 * Check the consistency of the self IDs we just read. The
1974 * problem we face is that a new bus reset can start while we
1975 * read out the self IDs from the DMA buffer. If this happens,
1976 * the DMA buffer will be overwritten with new self IDs and we
1977 * will read out inconsistent data. The OHCI specification
1978 * (section 11.2) recommends a technique similar to
1979 * linux/seqlock.h, where we remember the generation of the
1980 * self IDs in the buffer before reading them out and compare
1981 * it to the current generation after reading them out. If
1982 * the two generations match we know we have a consistent set
1983 * of self IDs.
1984 */
1985
1986 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1987 if (new_generation != generation) {
1988 ohci_notice(ohci, "new bus reset, discarding self ids\n");
1989 return;
1990 }
1991
1992 /* FIXME: Document how the locking works. */
1993 spin_lock_irq(&ohci->lock);
1994
1995 ohci->generation = -1; /* prevent AT packet queueing */
1996 context_stop(&ohci->at_request_ctx);
1997 context_stop(&ohci->at_response_ctx);
1998
1999 spin_unlock_irq(&ohci->lock);
2000
2001 /*
2002 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
2003 * packets in the AT queues and software needs to drain them.
2004 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
2005 */
2006 at_context_flush(&ohci->at_request_ctx);
2007 at_context_flush(&ohci->at_response_ctx);
2008
2009 spin_lock_irq(&ohci->lock);
2010
2011 ohci->generation = generation;
2012 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2013
2014 if (ohci->quirks & QUIRK_RESET_PACKET)
2015 ohci->request_generation = generation;
2016
2017 /*
2018 * This next bit is unrelated to the AT context stuff but we
2019 * have to do it under the spinlock also. If a new config rom
2020 * was set up before this reset, the old one is now no longer
2021 * in use and we can free it. Update the config rom pointers
2022 * to point to the current config rom and clear the
2023 * next_config_rom pointer so a new update can take place.
2024 */
2025
2026 if (ohci->next_config_rom != NULL) {
2027 if (ohci->next_config_rom != ohci->config_rom) {
2028 free_rom = ohci->config_rom;
2029 free_rom_bus = ohci->config_rom_bus;
2030 }
2031 ohci->config_rom = ohci->next_config_rom;
2032 ohci->config_rom_bus = ohci->next_config_rom_bus;
2033 ohci->next_config_rom = NULL;
2034
2035 /*
2036 * Restore config_rom image and manually update
2037 * config_rom registers. Writing the header quadlet
2038 * will indicate that the config rom is ready, so we
2039 * do that last.
2040 */
2041 reg_write(ohci, OHCI1394_BusOptions,
2042 be32_to_cpu(ohci->config_rom[2]));
2043 ohci->config_rom[0] = ohci->next_header;
2044 reg_write(ohci, OHCI1394_ConfigROMhdr,
2045 be32_to_cpu(ohci->next_header));
2046 }
2047
2048 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2049 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2050 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2051 #endif
2052
2053 spin_unlock_irq(&ohci->lock);
2054
2055 if (free_rom)
2056 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2057 free_rom, free_rom_bus);
2058
2059 log_selfids(ohci, generation, self_id_count);
2060
2061 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2062 self_id_count, ohci->self_id_buffer,
2063 ohci->csr_state_setclear_abdicate);
2064 ohci->csr_state_setclear_abdicate = false;
2065 }
2066
2067 static irqreturn_t irq_handler(int irq, void *data)
2068 {
2069 struct fw_ohci *ohci = data;
2070 u32 event, iso_event;
2071 int i;
2072
2073 event = reg_read(ohci, OHCI1394_IntEventClear);
2074
2075 if (!event || !~event)
2076 return IRQ_NONE;
2077
2078 /*
2079 * busReset and postedWriteErr must not be cleared yet
2080 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2081 */
2082 reg_write(ohci, OHCI1394_IntEventClear,
2083 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2084 log_irqs(ohci, event);
2085
2086 if (event & OHCI1394_selfIDComplete)
2087 queue_work(selfid_workqueue, &ohci->bus_reset_work);
2088
2089 if (event & OHCI1394_RQPkt)
2090 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2091
2092 if (event & OHCI1394_RSPkt)
2093 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2094
2095 if (event & OHCI1394_reqTxComplete)
2096 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2097
2098 if (event & OHCI1394_respTxComplete)
2099 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2100
2101 if (event & OHCI1394_isochRx) {
2102 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2103 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2104
2105 while (iso_event) {
2106 i = ffs(iso_event) - 1;
2107 tasklet_schedule(
2108 &ohci->ir_context_list[i].context.tasklet);
2109 iso_event &= ~(1 << i);
2110 }
2111 }
2112
2113 if (event & OHCI1394_isochTx) {
2114 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2115 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2116
2117 while (iso_event) {
2118 i = ffs(iso_event) - 1;
2119 tasklet_schedule(
2120 &ohci->it_context_list[i].context.tasklet);
2121 iso_event &= ~(1 << i);
2122 }
2123 }
2124
2125 if (unlikely(event & OHCI1394_regAccessFail))
2126 ohci_err(ohci, "register access failure\n");
2127
2128 if (unlikely(event & OHCI1394_postedWriteErr)) {
2129 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2130 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2131 reg_write(ohci, OHCI1394_IntEventClear,
2132 OHCI1394_postedWriteErr);
2133 if (printk_ratelimit())
2134 ohci_err(ohci, "PCI posted write error\n");
2135 }
2136
2137 if (unlikely(event & OHCI1394_cycleTooLong)) {
2138 if (printk_ratelimit())
2139 ohci_notice(ohci, "isochronous cycle too long\n");
2140 reg_write(ohci, OHCI1394_LinkControlSet,
2141 OHCI1394_LinkControl_cycleMaster);
2142 }
2143
2144 if (unlikely(event & OHCI1394_cycleInconsistent)) {
2145 /*
2146 * We need to clear this event bit in order to make
2147 * cycleMatch isochronous I/O work. In theory we should
2148 * stop active cycleMatch iso contexts now and restart
2149 * them at least two cycles later. (FIXME?)
2150 */
2151 if (printk_ratelimit())
2152 ohci_notice(ohci, "isochronous cycle inconsistent\n");
2153 }
2154
2155 if (unlikely(event & OHCI1394_unrecoverableError))
2156 handle_dead_contexts(ohci);
2157
2158 if (event & OHCI1394_cycle64Seconds) {
2159 spin_lock(&ohci->lock);
2160 update_bus_time(ohci);
2161 spin_unlock(&ohci->lock);
2162 } else
2163 flush_writes(ohci);
2164
2165 return IRQ_HANDLED;
2166 }
2167
2168 static int software_reset(struct fw_ohci *ohci)
2169 {
2170 u32 val;
2171 int i;
2172
2173 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2174 for (i = 0; i < 500; i++) {
2175 val = reg_read(ohci, OHCI1394_HCControlSet);
2176 if (!~val)
2177 return -ENODEV; /* Card was ejected. */
2178
2179 if (!(val & OHCI1394_HCControl_softReset))
2180 return 0;
2181
2182 msleep(1);
2183 }
2184
2185 return -EBUSY;
2186 }
2187
2188 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2189 {
2190 size_t size = length * 4;
2191
2192 memcpy(dest, src, size);
2193 if (size < CONFIG_ROM_SIZE)
2194 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2195 }
2196
2197 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2198 {
2199 bool enable_1394a;
2200 int ret, clear, set, offset;
2201
2202 /* Check if the driver should configure link and PHY. */
2203 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2204 OHCI1394_HCControl_programPhyEnable))
2205 return 0;
2206
2207 /* Paranoia: check whether the PHY supports 1394a, too. */
2208 enable_1394a = false;
2209 ret = read_phy_reg(ohci, 2);
2210 if (ret < 0)
2211 return ret;
2212 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2213 ret = read_paged_phy_reg(ohci, 1, 8);
2214 if (ret < 0)
2215 return ret;
2216 if (ret >= 1)
2217 enable_1394a = true;
2218 }
2219
2220 if (ohci->quirks & QUIRK_NO_1394A)
2221 enable_1394a = false;
2222
2223 /* Configure PHY and link consistently. */
2224 if (enable_1394a) {
2225 clear = 0;
2226 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2227 } else {
2228 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2229 set = 0;
2230 }
2231 ret = update_phy_reg(ohci, 5, clear, set);
2232 if (ret < 0)
2233 return ret;
2234
2235 if (enable_1394a)
2236 offset = OHCI1394_HCControlSet;
2237 else
2238 offset = OHCI1394_HCControlClear;
2239 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2240
2241 /* Clean up: configuration has been taken care of. */
2242 reg_write(ohci, OHCI1394_HCControlClear,
2243 OHCI1394_HCControl_programPhyEnable);
2244
2245 return 0;
2246 }
2247
2248 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2249 {
2250 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2251 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2252 int reg, i;
2253
2254 reg = read_phy_reg(ohci, 2);
2255 if (reg < 0)
2256 return reg;
2257 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2258 return 0;
2259
2260 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2261 reg = read_paged_phy_reg(ohci, 1, i + 10);
2262 if (reg < 0)
2263 return reg;
2264 if (reg != id[i])
2265 return 0;
2266 }
2267 return 1;
2268 }
2269
2270 static int ohci_enable(struct fw_card *card,
2271 const __be32 *config_rom, size_t length)
2272 {
2273 struct fw_ohci *ohci = fw_ohci(card);
2274 u32 lps, version, irqs;
2275 int i, ret;
2276
2277 if (software_reset(ohci)) {
2278 ohci_err(ohci, "failed to reset ohci card\n");
2279 return -EBUSY;
2280 }
2281
2282 /*
2283 * Now enable LPS, which we need in order to start accessing
2284 * most of the registers. In fact, on some cards (ALI M5251),
2285 * accessing registers in the SClk domain without LPS enabled
2286 * will lock up the machine. Wait 50msec to make sure we have
2287 * full link enabled. However, with some cards (well, at least
2288 * a JMicron PCIe card), we have to try again sometimes.
2289 *
2290 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
2291 * cannot actually use the phy at that time. These need tens of
2292 * millisecods pause between LPS write and first phy access too.
2293 */
2294
2295 reg_write(ohci, OHCI1394_HCControlSet,
2296 OHCI1394_HCControl_LPS |
2297 OHCI1394_HCControl_postedWriteEnable);
2298 flush_writes(ohci);
2299
2300 for (lps = 0, i = 0; !lps && i < 3; i++) {
2301 msleep(50);
2302 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2303 OHCI1394_HCControl_LPS;
2304 }
2305
2306 if (!lps) {
2307 ohci_err(ohci, "failed to set Link Power Status\n");
2308 return -EIO;
2309 }
2310
2311 if (ohci->quirks & QUIRK_TI_SLLZ059) {
2312 ret = probe_tsb41ba3d(ohci);
2313 if (ret < 0)
2314 return ret;
2315 if (ret)
2316 ohci_notice(ohci, "local TSB41BA3D phy\n");
2317 else
2318 ohci->quirks &= ~QUIRK_TI_SLLZ059;
2319 }
2320
2321 reg_write(ohci, OHCI1394_HCControlClear,
2322 OHCI1394_HCControl_noByteSwapData);
2323
2324 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2325 reg_write(ohci, OHCI1394_LinkControlSet,
2326 OHCI1394_LinkControl_cycleTimerEnable |
2327 OHCI1394_LinkControl_cycleMaster);
2328
2329 reg_write(ohci, OHCI1394_ATRetries,
2330 OHCI1394_MAX_AT_REQ_RETRIES |
2331 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2332 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2333 (200 << 16));
2334
2335 ohci->bus_time_running = false;
2336
2337 for (i = 0; i < 32; i++)
2338 if (ohci->ir_context_support & (1 << i))
2339 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2340 IR_CONTEXT_MULTI_CHANNEL_MODE);
2341
2342 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2343 if (version >= OHCI_VERSION_1_1) {
2344 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2345 0xfffffffe);
2346 card->broadcast_channel_auto_allocated = true;
2347 }
2348
2349 /* Get implemented bits of the priority arbitration request counter. */
2350 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2351 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2352 reg_write(ohci, OHCI1394_FairnessControl, 0);
2353 card->priority_budget_implemented = ohci->pri_req_max != 0;
2354
2355 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2356 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2357 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2358
2359 ret = configure_1394a_enhancements(ohci);
2360 if (ret < 0)
2361 return ret;
2362
2363 /* Activate link_on bit and contender bit in our self ID packets.*/
2364 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2365 if (ret < 0)
2366 return ret;
2367
2368 /*
2369 * When the link is not yet enabled, the atomic config rom
2370 * update mechanism described below in ohci_set_config_rom()
2371 * is not active. We have to update ConfigRomHeader and
2372 * BusOptions manually, and the write to ConfigROMmap takes
2373 * effect immediately. We tie this to the enabling of the
2374 * link, so we have a valid config rom before enabling - the
2375 * OHCI requires that ConfigROMhdr and BusOptions have valid
2376 * values before enabling.
2377 *
2378 * However, when the ConfigROMmap is written, some controllers
2379 * always read back quadlets 0 and 2 from the config rom to
2380 * the ConfigRomHeader and BusOptions registers on bus reset.
2381 * They shouldn't do that in this initial case where the link
2382 * isn't enabled. This means we have to use the same
2383 * workaround here, setting the bus header to 0 and then write
2384 * the right values in the bus reset tasklet.
2385 */
2386
2387 if (config_rom) {
2388 ohci->next_config_rom =
2389 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2390 &ohci->next_config_rom_bus,
2391 GFP_KERNEL);
2392 if (ohci->next_config_rom == NULL)
2393 return -ENOMEM;
2394
2395 copy_config_rom(ohci->next_config_rom, config_rom, length);
2396 } else {
2397 /*
2398 * In the suspend case, config_rom is NULL, which
2399 * means that we just reuse the old config rom.
2400 */
2401 ohci->next_config_rom = ohci->config_rom;
2402 ohci->next_config_rom_bus = ohci->config_rom_bus;
2403 }
2404
2405 ohci->next_header = ohci->next_config_rom[0];
2406 ohci->next_config_rom[0] = 0;
2407 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2408 reg_write(ohci, OHCI1394_BusOptions,
2409 be32_to_cpu(ohci->next_config_rom[2]));
2410 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2411
2412 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2413
2414 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2415 OHCI1394_RQPkt | OHCI1394_RSPkt |
2416 OHCI1394_isochTx | OHCI1394_isochRx |
2417 OHCI1394_postedWriteErr |
2418 OHCI1394_selfIDComplete |
2419 OHCI1394_regAccessFail |
2420 OHCI1394_cycleInconsistent |
2421 OHCI1394_unrecoverableError |
2422 OHCI1394_cycleTooLong |
2423 OHCI1394_masterIntEnable;
2424 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2425 irqs |= OHCI1394_busReset;
2426 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2427
2428 reg_write(ohci, OHCI1394_HCControlSet,
2429 OHCI1394_HCControl_linkEnable |
2430 OHCI1394_HCControl_BIBimageValid);
2431
2432 reg_write(ohci, OHCI1394_LinkControlSet,
2433 OHCI1394_LinkControl_rcvSelfID |
2434 OHCI1394_LinkControl_rcvPhyPkt);
2435
2436 ar_context_run(&ohci->ar_request_ctx);
2437 ar_context_run(&ohci->ar_response_ctx);
2438
2439 flush_writes(ohci);
2440
2441 /* We are ready to go, reset bus to finish initialization. */
2442 fw_schedule_bus_reset(&ohci->card, false, true);
2443
2444 return 0;
2445 }
2446
2447 static int ohci_set_config_rom(struct fw_card *card,
2448 const __be32 *config_rom, size_t length)
2449 {
2450 struct fw_ohci *ohci;
2451 __be32 *next_config_rom;
2452 dma_addr_t uninitialized_var(next_config_rom_bus);
2453
2454 ohci = fw_ohci(card);
2455
2456 /*
2457 * When the OHCI controller is enabled, the config rom update
2458 * mechanism is a bit tricky, but easy enough to use. See
2459 * section 5.5.6 in the OHCI specification.
2460 *
2461 * The OHCI controller caches the new config rom address in a
2462 * shadow register (ConfigROMmapNext) and needs a bus reset
2463 * for the changes to take place. When the bus reset is
2464 * detected, the controller loads the new values for the
2465 * ConfigRomHeader and BusOptions registers from the specified
2466 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2467 * shadow register. All automatically and atomically.
2468 *
2469 * Now, there's a twist to this story. The automatic load of
2470 * ConfigRomHeader and BusOptions doesn't honor the
2471 * noByteSwapData bit, so with a be32 config rom, the
2472 * controller will load be32 values in to these registers
2473 * during the atomic update, even on litte endian
2474 * architectures. The workaround we use is to put a 0 in the
2475 * header quadlet; 0 is endian agnostic and means that the
2476 * config rom isn't ready yet. In the bus reset tasklet we
2477 * then set up the real values for the two registers.
2478 *
2479 * We use ohci->lock to avoid racing with the code that sets
2480 * ohci->next_config_rom to NULL (see bus_reset_work).
2481 */
2482
2483 next_config_rom =
2484 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2485 &next_config_rom_bus, GFP_KERNEL);
2486 if (next_config_rom == NULL)
2487 return -ENOMEM;
2488
2489 spin_lock_irq(&ohci->lock);
2490
2491 /*
2492 * If there is not an already pending config_rom update,
2493 * push our new allocation into the ohci->next_config_rom
2494 * and then mark the local variable as null so that we
2495 * won't deallocate the new buffer.
2496 *
2497 * OTOH, if there is a pending config_rom update, just
2498 * use that buffer with the new config_rom data, and
2499 * let this routine free the unused DMA allocation.
2500 */
2501
2502 if (ohci->next_config_rom == NULL) {
2503 ohci->next_config_rom = next_config_rom;
2504 ohci->next_config_rom_bus = next_config_rom_bus;
2505 next_config_rom = NULL;
2506 }
2507
2508 copy_config_rom(ohci->next_config_rom, config_rom, length);
2509
2510 ohci->next_header = config_rom[0];
2511 ohci->next_config_rom[0] = 0;
2512
2513 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2514
2515 spin_unlock_irq(&ohci->lock);
2516
2517 /* If we didn't use the DMA allocation, delete it. */
2518 if (next_config_rom != NULL)
2519 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2520 next_config_rom, next_config_rom_bus);
2521
2522 /*
2523 * Now initiate a bus reset to have the changes take
2524 * effect. We clean up the old config rom memory and DMA
2525 * mappings in the bus reset tasklet, since the OHCI
2526 * controller could need to access it before the bus reset
2527 * takes effect.
2528 */
2529
2530 fw_schedule_bus_reset(&ohci->card, true, true);
2531
2532 return 0;
2533 }
2534
2535 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2536 {
2537 struct fw_ohci *ohci = fw_ohci(card);
2538
2539 at_context_transmit(&ohci->at_request_ctx, packet);
2540 }
2541
2542 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2543 {
2544 struct fw_ohci *ohci = fw_ohci(card);
2545
2546 at_context_transmit(&ohci->at_response_ctx, packet);
2547 }
2548
2549 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2550 {
2551 struct fw_ohci *ohci = fw_ohci(card);
2552 struct context *ctx = &ohci->at_request_ctx;
2553 struct driver_data *driver_data = packet->driver_data;
2554 int ret = -ENOENT;
2555
2556 tasklet_disable(&ctx->tasklet);
2557
2558 if (packet->ack != 0)
2559 goto out;
2560
2561 if (packet->payload_mapped)
2562 dma_unmap_single(ohci->card.device, packet->payload_bus,
2563 packet->payload_length, DMA_TO_DEVICE);
2564
2565 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2566 driver_data->packet = NULL;
2567 packet->ack = RCODE_CANCELLED;
2568 packet->callback(packet, &ohci->card, packet->ack);
2569 ret = 0;
2570 out:
2571 tasklet_enable(&ctx->tasklet);
2572
2573 return ret;
2574 }
2575
2576 static int ohci_enable_phys_dma(struct fw_card *card,
2577 int node_id, int generation)
2578 {
2579 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2580 return 0;
2581 #else
2582 struct fw_ohci *ohci = fw_ohci(card);
2583 unsigned long flags;
2584 int n, ret = 0;
2585
2586 /*
2587 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2588 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2589 */
2590
2591 spin_lock_irqsave(&ohci->lock, flags);
2592
2593 if (ohci->generation != generation) {
2594 ret = -ESTALE;
2595 goto out;
2596 }
2597
2598 /*
2599 * Note, if the node ID contains a non-local bus ID, physical DMA is
2600 * enabled for _all_ nodes on remote buses.
2601 */
2602
2603 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2604 if (n < 32)
2605 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2606 else
2607 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2608
2609 flush_writes(ohci);
2610 out:
2611 spin_unlock_irqrestore(&ohci->lock, flags);
2612
2613 return ret;
2614 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2615 }
2616
2617 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2618 {
2619 struct fw_ohci *ohci = fw_ohci(card);
2620 unsigned long flags;
2621 u32 value;
2622
2623 switch (csr_offset) {
2624 case CSR_STATE_CLEAR:
2625 case CSR_STATE_SET:
2626 if (ohci->is_root &&
2627 (reg_read(ohci, OHCI1394_LinkControlSet) &
2628 OHCI1394_LinkControl_cycleMaster))
2629 value = CSR_STATE_BIT_CMSTR;
2630 else
2631 value = 0;
2632 if (ohci->csr_state_setclear_abdicate)
2633 value |= CSR_STATE_BIT_ABDICATE;
2634
2635 return value;
2636
2637 case CSR_NODE_IDS:
2638 return reg_read(ohci, OHCI1394_NodeID) << 16;
2639
2640 case CSR_CYCLE_TIME:
2641 return get_cycle_time(ohci);
2642
2643 case CSR_BUS_TIME:
2644 /*
2645 * We might be called just after the cycle timer has wrapped
2646 * around but just before the cycle64Seconds handler, so we
2647 * better check here, too, if the bus time needs to be updated.
2648 */
2649 spin_lock_irqsave(&ohci->lock, flags);
2650 value = update_bus_time(ohci);
2651 spin_unlock_irqrestore(&ohci->lock, flags);
2652 return value;
2653
2654 case CSR_BUSY_TIMEOUT:
2655 value = reg_read(ohci, OHCI1394_ATRetries);
2656 return (value >> 4) & 0x0ffff00f;
2657
2658 case CSR_PRIORITY_BUDGET:
2659 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2660 (ohci->pri_req_max << 8);
2661
2662 default:
2663 WARN_ON(1);
2664 return 0;
2665 }
2666 }
2667
2668 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2669 {
2670 struct fw_ohci *ohci = fw_ohci(card);
2671 unsigned long flags;
2672
2673 switch (csr_offset) {
2674 case CSR_STATE_CLEAR:
2675 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2676 reg_write(ohci, OHCI1394_LinkControlClear,
2677 OHCI1394_LinkControl_cycleMaster);
2678 flush_writes(ohci);
2679 }
2680 if (value & CSR_STATE_BIT_ABDICATE)
2681 ohci->csr_state_setclear_abdicate = false;
2682 break;
2683
2684 case CSR_STATE_SET:
2685 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2686 reg_write(ohci, OHCI1394_LinkControlSet,
2687 OHCI1394_LinkControl_cycleMaster);
2688 flush_writes(ohci);
2689 }
2690 if (value & CSR_STATE_BIT_ABDICATE)
2691 ohci->csr_state_setclear_abdicate = true;
2692 break;
2693
2694 case CSR_NODE_IDS:
2695 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2696 flush_writes(ohci);
2697 break;
2698
2699 case CSR_CYCLE_TIME:
2700 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2701 reg_write(ohci, OHCI1394_IntEventSet,
2702 OHCI1394_cycleInconsistent);
2703 flush_writes(ohci);
2704 break;
2705
2706 case CSR_BUS_TIME:
2707 spin_lock_irqsave(&ohci->lock, flags);
2708 ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2709 (value & ~0x7f);
2710 spin_unlock_irqrestore(&ohci->lock, flags);
2711 break;
2712
2713 case CSR_BUSY_TIMEOUT:
2714 value = (value & 0xf) | ((value & 0xf) << 4) |
2715 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2716 reg_write(ohci, OHCI1394_ATRetries, value);
2717 flush_writes(ohci);
2718 break;
2719
2720 case CSR_PRIORITY_BUDGET:
2721 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2722 flush_writes(ohci);
2723 break;
2724
2725 default:
2726 WARN_ON(1);
2727 break;
2728 }
2729 }
2730
2731 static void flush_iso_completions(struct iso_context *ctx)
2732 {
2733 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2734 ctx->header_length, ctx->header,
2735 ctx->base.callback_data);
2736 ctx->header_length = 0;
2737 }
2738
2739 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2740 {
2741 u32 *ctx_hdr;
2742
2743 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
2744 if (ctx->base.drop_overflow_headers)
2745 return;
2746 flush_iso_completions(ctx);
2747 }
2748
2749 ctx_hdr = ctx->header + ctx->header_length;
2750 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2751
2752 /*
2753 * The two iso header quadlets are byteswapped to little
2754 * endian by the controller, but we want to present them
2755 * as big endian for consistency with the bus endianness.
2756 */
2757 if (ctx->base.header_size > 0)
2758 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2759 if (ctx->base.header_size > 4)
2760 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2761 if (ctx->base.header_size > 8)
2762 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2763 ctx->header_length += ctx->base.header_size;
2764 }
2765
2766 static int handle_ir_packet_per_buffer(struct context *context,
2767 struct descriptor *d,
2768 struct descriptor *last)
2769 {
2770 struct iso_context *ctx =
2771 container_of(context, struct iso_context, context);
2772 struct descriptor *pd;
2773 u32 buffer_dma;
2774
2775 for (pd = d; pd <= last; pd++)
2776 if (pd->transfer_status)
2777 break;
2778 if (pd > last)
2779 /* Descriptor(s) not done yet, stop iteration */
2780 return 0;
2781
2782 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2783 d++;
2784 buffer_dma = le32_to_cpu(d->data_address);
2785 dma_sync_single_range_for_cpu(context->ohci->card.device,
2786 buffer_dma & PAGE_MASK,
2787 buffer_dma & ~PAGE_MASK,
2788 le16_to_cpu(d->req_count),
2789 DMA_FROM_DEVICE);
2790 }
2791
2792 copy_iso_headers(ctx, (u32 *) (last + 1));
2793
2794 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2795 flush_iso_completions(ctx);
2796
2797 return 1;
2798 }
2799
2800 /* d == last because each descriptor block is only a single descriptor. */
2801 static int handle_ir_buffer_fill(struct context *context,
2802 struct descriptor *d,
2803 struct descriptor *last)
2804 {
2805 struct iso_context *ctx =
2806 container_of(context, struct iso_context, context);
2807 unsigned int req_count, res_count, completed;
2808 u32 buffer_dma;
2809
2810 req_count = le16_to_cpu(last->req_count);
2811 res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
2812 completed = req_count - res_count;
2813 buffer_dma = le32_to_cpu(last->data_address);
2814
2815 if (completed > 0) {
2816 ctx->mc_buffer_bus = buffer_dma;
2817 ctx->mc_completed = completed;
2818 }
2819
2820 if (res_count != 0)
2821 /* Descriptor(s) not done yet, stop iteration */
2822 return 0;
2823
2824 dma_sync_single_range_for_cpu(context->ohci->card.device,
2825 buffer_dma & PAGE_MASK,
2826 buffer_dma & ~PAGE_MASK,
2827 completed, DMA_FROM_DEVICE);
2828
2829 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2830 ctx->base.callback.mc(&ctx->base,
2831 buffer_dma + completed,
2832 ctx->base.callback_data);
2833 ctx->mc_completed = 0;
2834 }
2835
2836 return 1;
2837 }
2838
2839 static void flush_ir_buffer_fill(struct iso_context *ctx)
2840 {
2841 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2842 ctx->mc_buffer_bus & PAGE_MASK,
2843 ctx->mc_buffer_bus & ~PAGE_MASK,
2844 ctx->mc_completed, DMA_FROM_DEVICE);
2845
2846 ctx->base.callback.mc(&ctx->base,
2847 ctx->mc_buffer_bus + ctx->mc_completed,
2848 ctx->base.callback_data);
2849 ctx->mc_completed = 0;
2850 }
2851
2852 static inline void sync_it_packet_for_cpu(struct context *context,
2853 struct descriptor *pd)
2854 {
2855 __le16 control;
2856 u32 buffer_dma;
2857
2858 /* only packets beginning with OUTPUT_MORE* have data buffers */
2859 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2860 return;
2861
2862 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2863 pd += 2;
2864
2865 /*
2866 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2867 * data buffer is in the context program's coherent page and must not
2868 * be synced.
2869 */
2870 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2871 (context->current_bus & PAGE_MASK)) {
2872 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2873 return;
2874 pd++;
2875 }
2876
2877 do {
2878 buffer_dma = le32_to_cpu(pd->data_address);
2879 dma_sync_single_range_for_cpu(context->ohci->card.device,
2880 buffer_dma & PAGE_MASK,
2881 buffer_dma & ~PAGE_MASK,
2882 le16_to_cpu(pd->req_count),
2883 DMA_TO_DEVICE);
2884 control = pd->control;
2885 pd++;
2886 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2887 }
2888
2889 static int handle_it_packet(struct context *context,
2890 struct descriptor *d,
2891 struct descriptor *last)
2892 {
2893 struct iso_context *ctx =
2894 container_of(context, struct iso_context, context);
2895 struct descriptor *pd;
2896 __be32 *ctx_hdr;
2897
2898 for (pd = d; pd <= last; pd++)
2899 if (pd->transfer_status)
2900 break;
2901 if (pd > last)
2902 /* Descriptor(s) not done yet, stop iteration */
2903 return 0;
2904
2905 sync_it_packet_for_cpu(context, d);
2906
2907 if (ctx->header_length + 4 > PAGE_SIZE) {
2908 if (ctx->base.drop_overflow_headers)
2909 return 1;
2910 flush_iso_completions(ctx);
2911 }
2912
2913 ctx_hdr = ctx->header + ctx->header_length;
2914 ctx->last_timestamp = le16_to_cpu(last->res_count);
2915 /* Present this value as big-endian to match the receive code */
2916 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2917 le16_to_cpu(pd->res_count));
2918 ctx->header_length += 4;
2919
2920 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2921 flush_iso_completions(ctx);
2922
2923 return 1;
2924 }
2925
2926 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2927 {
2928 u32 hi = channels >> 32, lo = channels;
2929
2930 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2931 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2932 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2933 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2934 mmiowb();
2935 ohci->mc_channels = channels;
2936 }
2937
2938 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2939 int type, int channel, size_t header_size)
2940 {
2941 struct fw_ohci *ohci = fw_ohci(card);
2942 struct iso_context *uninitialized_var(ctx);
2943 descriptor_callback_t uninitialized_var(callback);
2944 u64 *uninitialized_var(channels);
2945 u32 *uninitialized_var(mask), uninitialized_var(regs);
2946 int index, ret = -EBUSY;
2947
2948 spin_lock_irq(&ohci->lock);
2949
2950 switch (type) {
2951 case FW_ISO_CONTEXT_TRANSMIT:
2952 mask = &ohci->it_context_mask;
2953 callback = handle_it_packet;
2954 index = ffs(*mask) - 1;
2955 if (index >= 0) {
2956 *mask &= ~(1 << index);
2957 regs = OHCI1394_IsoXmitContextBase(index);
2958 ctx = &ohci->it_context_list[index];
2959 }
2960 break;
2961
2962 case FW_ISO_CONTEXT_RECEIVE:
2963 channels = &ohci->ir_context_channels;
2964 mask = &ohci->ir_context_mask;
2965 callback = handle_ir_packet_per_buffer;
2966 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2967 if (index >= 0) {
2968 *channels &= ~(1ULL << channel);
2969 *mask &= ~(1 << index);
2970 regs = OHCI1394_IsoRcvContextBase(index);
2971 ctx = &ohci->ir_context_list[index];
2972 }
2973 break;
2974
2975 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2976 mask = &ohci->ir_context_mask;
2977 callback = handle_ir_buffer_fill;
2978 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2979 if (index >= 0) {
2980 ohci->mc_allocated = true;
2981 *mask &= ~(1 << index);
2982 regs = OHCI1394_IsoRcvContextBase(index);
2983 ctx = &ohci->ir_context_list[index];
2984 }
2985 break;
2986
2987 default:
2988 index = -1;
2989 ret = -ENOSYS;
2990 }
2991
2992 spin_unlock_irq(&ohci->lock);
2993
2994 if (index < 0)
2995 return ERR_PTR(ret);
2996
2997 memset(ctx, 0, sizeof(*ctx));
2998 ctx->header_length = 0;
2999 ctx->header = (void *) __get_free_page(GFP_KERNEL);
3000 if (ctx->header == NULL) {
3001 ret = -ENOMEM;
3002 goto out;
3003 }
3004 ret = context_init(&ctx->context, ohci, regs, callback);
3005 if (ret < 0)
3006 goto out_with_header;
3007
3008 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
3009 set_multichannel_mask(ohci, 0);
3010 ctx->mc_completed = 0;
3011 }
3012
3013 return &ctx->base;
3014
3015 out_with_header:
3016 free_page((unsigned long)ctx->header);
3017 out:
3018 spin_lock_irq(&ohci->lock);
3019
3020 switch (type) {
3021 case FW_ISO_CONTEXT_RECEIVE:
3022 *channels |= 1ULL << channel;
3023 break;
3024
3025 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3026 ohci->mc_allocated = false;
3027 break;
3028 }
3029 *mask |= 1 << index;
3030
3031 spin_unlock_irq(&ohci->lock);
3032
3033 return ERR_PTR(ret);
3034 }
3035
3036 static int ohci_start_iso(struct fw_iso_context *base,
3037 s32 cycle, u32 sync, u32 tags)
3038 {
3039 struct iso_context *ctx = container_of(base, struct iso_context, base);
3040 struct fw_ohci *ohci = ctx->context.ohci;
3041 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
3042 int index;
3043
3044 /* the controller cannot start without any queued packets */
3045 if (ctx->context.last->branch_address == 0)
3046 return -ENODATA;
3047
3048 switch (ctx->base.type) {
3049 case FW_ISO_CONTEXT_TRANSMIT:
3050 index = ctx - ohci->it_context_list;
3051 match = 0;
3052 if (cycle >= 0)
3053 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3054 (cycle & 0x7fff) << 16;
3055
3056 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3057 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3058 context_run(&ctx->context, match);
3059 break;
3060
3061 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3062 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3063 /* fall through */
3064 case FW_ISO_CONTEXT_RECEIVE:
3065 index = ctx - ohci->ir_context_list;
3066 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3067 if (cycle >= 0) {
3068 match |= (cycle & 0x07fff) << 12;
3069 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3070 }
3071
3072 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3073 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3074 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3075 context_run(&ctx->context, control);
3076
3077 ctx->sync = sync;
3078 ctx->tags = tags;
3079
3080 break;
3081 }
3082
3083 return 0;
3084 }
3085
3086 static int ohci_stop_iso(struct fw_iso_context *base)
3087 {
3088 struct fw_ohci *ohci = fw_ohci(base->card);
3089 struct iso_context *ctx = container_of(base, struct iso_context, base);
3090 int index;
3091
3092 switch (ctx->base.type) {
3093 case FW_ISO_CONTEXT_TRANSMIT:
3094 index = ctx - ohci->it_context_list;
3095 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3096 break;
3097
3098 case FW_ISO_CONTEXT_RECEIVE:
3099 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3100 index = ctx - ohci->ir_context_list;
3101 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3102 break;
3103 }
3104 flush_writes(ohci);
3105 context_stop(&ctx->context);
3106 tasklet_kill(&ctx->context.tasklet);
3107
3108 return 0;
3109 }
3110
3111 static void ohci_free_iso_context(struct fw_iso_context *base)
3112 {
3113 struct fw_ohci *ohci = fw_ohci(base->card);
3114 struct iso_context *ctx = container_of(base, struct iso_context, base);
3115 unsigned long flags;
3116 int index;
3117
3118 ohci_stop_iso(base);
3119 context_release(&ctx->context);
3120 free_page((unsigned long)ctx->header);
3121
3122 spin_lock_irqsave(&ohci->lock, flags);
3123
3124 switch (base->type) {
3125 case FW_ISO_CONTEXT_TRANSMIT:
3126 index = ctx - ohci->it_context_list;
3127 ohci->it_context_mask |= 1 << index;
3128 break;
3129
3130 case FW_ISO_CONTEXT_RECEIVE:
3131 index = ctx - ohci->ir_context_list;
3132 ohci->ir_context_mask |= 1 << index;
3133 ohci->ir_context_channels |= 1ULL << base->channel;
3134 break;
3135
3136 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3137 index = ctx - ohci->ir_context_list;
3138 ohci->ir_context_mask |= 1 << index;
3139 ohci->ir_context_channels |= ohci->mc_channels;
3140 ohci->mc_channels = 0;
3141 ohci->mc_allocated = false;
3142 break;
3143 }
3144
3145 spin_unlock_irqrestore(&ohci->lock, flags);
3146 }
3147
3148 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3149 {
3150 struct fw_ohci *ohci = fw_ohci(base->card);
3151 unsigned long flags;
3152 int ret;
3153
3154 switch (base->type) {
3155 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3156
3157 spin_lock_irqsave(&ohci->lock, flags);
3158
3159 /* Don't allow multichannel to grab other contexts' channels. */
3160 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3161 *channels = ohci->ir_context_channels;
3162 ret = -EBUSY;
3163 } else {
3164 set_multichannel_mask(ohci, *channels);
3165 ret = 0;
3166 }
3167
3168 spin_unlock_irqrestore(&ohci->lock, flags);
3169
3170 break;
3171 default:
3172 ret = -EINVAL;
3173 }
3174
3175 return ret;
3176 }
3177
3178 #ifdef CONFIG_PM
3179 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3180 {
3181 int i;
3182 struct iso_context *ctx;
3183
3184 for (i = 0 ; i < ohci->n_ir ; i++) {
3185 ctx = &ohci->ir_context_list[i];
3186 if (ctx->context.running)
3187 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3188 }
3189
3190 for (i = 0 ; i < ohci->n_it ; i++) {
3191 ctx = &ohci->it_context_list[i];
3192 if (ctx->context.running)
3193 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3194 }
3195 }
3196 #endif
3197
3198 static int queue_iso_transmit(struct iso_context *ctx,
3199 struct fw_iso_packet *packet,
3200 struct fw_iso_buffer *buffer,
3201 unsigned long payload)
3202 {
3203 struct descriptor *d, *last, *pd;
3204 struct fw_iso_packet *p;
3205 __le32 *header;
3206 dma_addr_t d_bus, page_bus;
3207 u32 z, header_z, payload_z, irq;
3208 u32 payload_index, payload_end_index, next_page_index;
3209 int page, end_page, i, length, offset;
3210
3211 p = packet;
3212 payload_index = payload;
3213
3214 if (p->skip)
3215 z = 1;
3216 else
3217 z = 2;
3218 if (p->header_length > 0)
3219 z++;
3220
3221 /* Determine the first page the payload isn't contained in. */
3222 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3223 if (p->payload_length > 0)
3224 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3225 else
3226 payload_z = 0;
3227
3228 z += payload_z;
3229
3230 /* Get header size in number of descriptors. */
3231 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3232
3233 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3234 if (d == NULL)
3235 return -ENOMEM;
3236
3237 if (!p->skip) {
3238 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3239 d[0].req_count = cpu_to_le16(8);
3240 /*
3241 * Link the skip address to this descriptor itself. This causes
3242 * a context to skip a cycle whenever lost cycles or FIFO
3243 * overruns occur, without dropping the data. The application
3244 * should then decide whether this is an error condition or not.
3245 * FIXME: Make the context's cycle-lost behaviour configurable?
3246 */
3247 d[0].branch_address = cpu_to_le32(d_bus | z);
3248
3249 header = (__le32 *) &d[1];
3250 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3251 IT_HEADER_TAG(p->tag) |
3252 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3253 IT_HEADER_CHANNEL(ctx->base.channel) |
3254 IT_HEADER_SPEED(ctx->base.speed));
3255 header[1] =
3256 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3257 p->payload_length));
3258 }
3259
3260 if (p->header_length > 0) {
3261 d[2].req_count = cpu_to_le16(p->header_length);
3262 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3263 memcpy(&d[z], p->header, p->header_length);
3264 }
3265
3266 pd = d + z - payload_z;
3267 payload_end_index = payload_index + p->payload_length;
3268 for (i = 0; i < payload_z; i++) {
3269 page = payload_index >> PAGE_SHIFT;
3270 offset = payload_index & ~PAGE_MASK;
3271 next_page_index = (page + 1) << PAGE_SHIFT;
3272 length =
3273 min(next_page_index, payload_end_index) - payload_index;
3274 pd[i].req_count = cpu_to_le16(length);
3275
3276 page_bus = page_private(buffer->pages[page]);
3277 pd[i].data_address = cpu_to_le32(page_bus + offset);
3278
3279 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3280 page_bus, offset, length,
3281 DMA_TO_DEVICE);
3282
3283 payload_index += length;
3284 }
3285
3286 if (p->interrupt)
3287 irq = DESCRIPTOR_IRQ_ALWAYS;
3288 else
3289 irq = DESCRIPTOR_NO_IRQ;
3290
3291 last = z == 2 ? d : d + z - 1;
3292 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3293 DESCRIPTOR_STATUS |
3294 DESCRIPTOR_BRANCH_ALWAYS |
3295 irq);
3296
3297 context_append(&ctx->context, d, z, header_z);
3298
3299 return 0;
3300 }
3301
3302 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3303 struct fw_iso_packet *packet,
3304 struct fw_iso_buffer *buffer,
3305 unsigned long payload)
3306 {
3307 struct device *device = ctx->context.ohci->card.device;
3308 struct descriptor *d, *pd;
3309 dma_addr_t d_bus, page_bus;
3310 u32 z, header_z, rest;
3311 int i, j, length;
3312 int page, offset, packet_count, header_size, payload_per_buffer;
3313
3314 /*
3315 * The OHCI controller puts the isochronous header and trailer in the
3316 * buffer, so we need at least 8 bytes.
3317 */
3318 packet_count = packet->header_length / ctx->base.header_size;
3319 header_size = max(ctx->base.header_size, (size_t)8);
3320
3321 /* Get header size in number of descriptors. */
3322 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3323 page = payload >> PAGE_SHIFT;
3324 offset = payload & ~PAGE_MASK;
3325 payload_per_buffer = packet->payload_length / packet_count;
3326
3327 for (i = 0; i < packet_count; i++) {
3328 /* d points to the header descriptor */
3329 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3330 d = context_get_descriptors(&ctx->context,
3331 z + header_z, &d_bus);
3332 if (d == NULL)
3333 return -ENOMEM;
3334
3335 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3336 DESCRIPTOR_INPUT_MORE);
3337 if (packet->skip && i == 0)
3338 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3339 d->req_count = cpu_to_le16(header_size);
3340 d->res_count = d->req_count;
3341 d->transfer_status = 0;
3342 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3343
3344 rest = payload_per_buffer;
3345 pd = d;
3346 for (j = 1; j < z; j++) {
3347 pd++;
3348 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3349 DESCRIPTOR_INPUT_MORE);
3350
3351 if (offset + rest < PAGE_SIZE)
3352 length = rest;
3353 else
3354 length = PAGE_SIZE - offset;
3355 pd->req_count = cpu_to_le16(length);
3356 pd->res_count = pd->req_count;
3357 pd->transfer_status = 0;
3358
3359 page_bus = page_private(buffer->pages[page]);
3360 pd->data_address = cpu_to_le32(page_bus + offset);
3361
3362 dma_sync_single_range_for_device(device, page_bus,
3363 offset, length,
3364 DMA_FROM_DEVICE);
3365
3366 offset = (offset + length) & ~PAGE_MASK;
3367 rest -= length;
3368 if (offset == 0)
3369 page++;
3370 }
3371 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3372 DESCRIPTOR_INPUT_LAST |
3373 DESCRIPTOR_BRANCH_ALWAYS);
3374 if (packet->interrupt && i == packet_count - 1)
3375 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3376
3377 context_append(&ctx->context, d, z, header_z);
3378 }
3379
3380 return 0;
3381 }
3382
3383 static int queue_iso_buffer_fill(struct iso_context *ctx,
3384 struct fw_iso_packet *packet,
3385 struct fw_iso_buffer *buffer,
3386 unsigned long payload)
3387 {
3388 struct descriptor *d;
3389 dma_addr_t d_bus, page_bus;
3390 int page, offset, rest, z, i, length;
3391
3392 page = payload >> PAGE_SHIFT;
3393 offset = payload & ~PAGE_MASK;
3394 rest = packet->payload_length;
3395
3396 /* We need one descriptor for each page in the buffer. */
3397 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3398
3399 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3400 return -EFAULT;
3401
3402 for (i = 0; i < z; i++) {
3403 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3404 if (d == NULL)
3405 return -ENOMEM;
3406
3407 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3408 DESCRIPTOR_BRANCH_ALWAYS);
3409 if (packet->skip && i == 0)
3410 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3411 if (packet->interrupt && i == z - 1)
3412 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3413
3414 if (offset + rest < PAGE_SIZE)
3415 length = rest;
3416 else
3417 length = PAGE_SIZE - offset;
3418 d->req_count = cpu_to_le16(length);
3419 d->res_count = d->req_count;
3420 d->transfer_status = 0;
3421
3422 page_bus = page_private(buffer->pages[page]);
3423 d->data_address = cpu_to_le32(page_bus + offset);
3424
3425 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3426 page_bus, offset, length,
3427 DMA_FROM_DEVICE);
3428
3429 rest -= length;
3430 offset = 0;
3431 page++;
3432
3433 context_append(&ctx->context, d, 1, 0);
3434 }
3435
3436 return 0;
3437 }
3438
3439 static int ohci_queue_iso(struct fw_iso_context *base,
3440 struct fw_iso_packet *packet,
3441 struct fw_iso_buffer *buffer,
3442 unsigned long payload)
3443 {
3444 struct iso_context *ctx = container_of(base, struct iso_context, base);
3445 unsigned long flags;
3446 int ret = -ENOSYS;
3447
3448 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3449 switch (base->type) {
3450 case FW_ISO_CONTEXT_TRANSMIT:
3451 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3452 break;
3453 case FW_ISO_CONTEXT_RECEIVE:
3454 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3455 break;
3456 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3457 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3458 break;
3459 }
3460 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3461
3462 return ret;
3463 }
3464
3465 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3466 {
3467 struct context *ctx =
3468 &container_of(base, struct iso_context, base)->context;
3469
3470 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3471 }
3472
3473 static int ohci_flush_iso_completions(struct fw_iso_context *base)
3474 {
3475 struct iso_context *ctx = container_of(base, struct iso_context, base);
3476 int ret = 0;
3477
3478 tasklet_disable(&ctx->context.tasklet);
3479
3480 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3481 context_tasklet((unsigned long)&ctx->context);
3482
3483 switch (base->type) {
3484 case FW_ISO_CONTEXT_TRANSMIT:
3485 case FW_ISO_CONTEXT_RECEIVE:
3486 if (ctx->header_length != 0)
3487 flush_iso_completions(ctx);
3488 break;
3489 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3490 if (ctx->mc_completed != 0)
3491 flush_ir_buffer_fill(ctx);
3492 break;
3493 default:
3494 ret = -ENOSYS;
3495 }
3496
3497 clear_bit_unlock(0, &ctx->flushing_completions);
3498 smp_mb__after_clear_bit();
3499 }
3500
3501 tasklet_enable(&ctx->context.tasklet);
3502
3503 return ret;
3504 }
3505
3506 static const struct fw_card_driver ohci_driver = {
3507 .enable = ohci_enable,
3508 .read_phy_reg = ohci_read_phy_reg,
3509 .update_phy_reg = ohci_update_phy_reg,
3510 .set_config_rom = ohci_set_config_rom,
3511 .send_request = ohci_send_request,
3512 .send_response = ohci_send_response,
3513 .cancel_packet = ohci_cancel_packet,
3514 .enable_phys_dma = ohci_enable_phys_dma,
3515 .read_csr = ohci_read_csr,
3516 .write_csr = ohci_write_csr,
3517
3518 .allocate_iso_context = ohci_allocate_iso_context,
3519 .free_iso_context = ohci_free_iso_context,
3520 .set_iso_channels = ohci_set_iso_channels,
3521 .queue_iso = ohci_queue_iso,
3522 .flush_queue_iso = ohci_flush_queue_iso,
3523 .flush_iso_completions = ohci_flush_iso_completions,
3524 .start_iso = ohci_start_iso,
3525 .stop_iso = ohci_stop_iso,
3526 };
3527
3528 #ifdef CONFIG_PPC_PMAC
3529 static void pmac_ohci_on(struct pci_dev *dev)
3530 {
3531 if (machine_is(powermac)) {
3532 struct device_node *ofn = pci_device_to_OF_node(dev);
3533
3534 if (ofn) {
3535 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3536 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3537 }
3538 }
3539 }
3540
3541 static void pmac_ohci_off(struct pci_dev *dev)
3542 {
3543 if (machine_is(powermac)) {
3544 struct device_node *ofn = pci_device_to_OF_node(dev);
3545
3546 if (ofn) {
3547 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3548 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3549 }
3550 }
3551 }
3552 #else
3553 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3554 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3555 #endif /* CONFIG_PPC_PMAC */
3556
3557 static int pci_probe(struct pci_dev *dev,
3558 const struct pci_device_id *ent)
3559 {
3560 struct fw_ohci *ohci;
3561 u32 bus_options, max_receive, link_speed, version;
3562 u64 guid;
3563 int i, err;
3564 size_t size;
3565
3566 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3567 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3568 return -ENOSYS;
3569 }
3570
3571 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3572 if (ohci == NULL) {
3573 err = -ENOMEM;
3574 goto fail;
3575 }
3576
3577 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3578
3579 pmac_ohci_on(dev);
3580
3581 err = pci_enable_device(dev);
3582 if (err) {
3583 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3584 goto fail_free;
3585 }
3586
3587 pci_set_master(dev);
3588 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3589 pci_set_drvdata(dev, ohci);
3590
3591 spin_lock_init(&ohci->lock);
3592 mutex_init(&ohci->phy_reg_mutex);
3593
3594 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3595
3596 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3597 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
3598 ohci_err(ohci, "invalid MMIO resource\n");
3599 err = -ENXIO;
3600 goto fail_disable;
3601 }
3602
3603 err = pci_request_region(dev, 0, ohci_driver_name);
3604 if (err) {
3605 ohci_err(ohci, "MMIO resource unavailable\n");
3606 goto fail_disable;
3607 }
3608
3609 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3610 if (ohci->registers == NULL) {
3611 ohci_err(ohci, "failed to remap registers\n");
3612 err = -ENXIO;
3613 goto fail_iomem;
3614 }
3615
3616 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3617 if ((ohci_quirks[i].vendor == dev->vendor) &&
3618 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3619 ohci_quirks[i].device == dev->device) &&
3620 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3621 ohci_quirks[i].revision >= dev->revision)) {
3622 ohci->quirks = ohci_quirks[i].flags;
3623 break;
3624 }
3625 if (param_quirks)
3626 ohci->quirks = param_quirks;
3627
3628 /*
3629 * Because dma_alloc_coherent() allocates at least one page,
3630 * we save space by using a common buffer for the AR request/
3631 * response descriptors and the self IDs buffer.
3632 */
3633 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3634 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3635 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3636 PAGE_SIZE,
3637 &ohci->misc_buffer_bus,
3638 GFP_KERNEL);
3639 if (!ohci->misc_buffer) {
3640 err = -ENOMEM;
3641 goto fail_iounmap;
3642 }
3643
3644 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3645 OHCI1394_AsReqRcvContextControlSet);
3646 if (err < 0)
3647 goto fail_misc_buf;
3648
3649 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3650 OHCI1394_AsRspRcvContextControlSet);
3651 if (err < 0)
3652 goto fail_arreq_ctx;
3653
3654 err = context_init(&ohci->at_request_ctx, ohci,
3655 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3656 if (err < 0)
3657 goto fail_arrsp_ctx;
3658
3659 err = context_init(&ohci->at_response_ctx, ohci,
3660 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3661 if (err < 0)
3662 goto fail_atreq_ctx;
3663
3664 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3665 ohci->ir_context_channels = ~0ULL;
3666 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3667 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3668 ohci->ir_context_mask = ohci->ir_context_support;
3669 ohci->n_ir = hweight32(ohci->ir_context_mask);
3670 size = sizeof(struct iso_context) * ohci->n_ir;
3671 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3672
3673 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3674 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3675 /* JMicron JMB38x often shows 0 at first read, just ignore it */
3676 if (!ohci->it_context_support) {
3677 ohci_notice(ohci, "overriding IsoXmitIntMask\n");
3678 ohci->it_context_support = 0xf;
3679 }
3680 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3681 ohci->it_context_mask = ohci->it_context_support;
3682 ohci->n_it = hweight32(ohci->it_context_mask);
3683 size = sizeof(struct iso_context) * ohci->n_it;
3684 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3685
3686 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3687 err = -ENOMEM;
3688 goto fail_contexts;
3689 }
3690
3691 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2;
3692 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3693
3694 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3695 max_receive = (bus_options >> 12) & 0xf;
3696 link_speed = bus_options & 0x7;
3697 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3698 reg_read(ohci, OHCI1394_GUIDLo);
3699
3700 if (!(ohci->quirks & QUIRK_NO_MSI))
3701 pci_enable_msi(dev);
3702 if (request_irq(dev->irq, irq_handler,
3703 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
3704 ohci_driver_name, ohci)) {
3705 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
3706 err = -EIO;
3707 goto fail_msi;
3708 }
3709
3710 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3711 if (err)
3712 goto fail_irq;
3713
3714 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3715 ohci_notice(ohci,
3716 "added OHCI v%x.%x device as card %d, "
3717 "%d IR + %d IT contexts, quirks 0x%x\n",
3718 version >> 16, version & 0xff, ohci->card.index,
3719 ohci->n_ir, ohci->n_it, ohci->quirks);
3720
3721 return 0;
3722
3723 fail_irq:
3724 free_irq(dev->irq, ohci);
3725 fail_msi:
3726 pci_disable_msi(dev);
3727 fail_contexts:
3728 kfree(ohci->ir_context_list);
3729 kfree(ohci->it_context_list);
3730 context_release(&ohci->at_response_ctx);
3731 fail_atreq_ctx:
3732 context_release(&ohci->at_request_ctx);
3733 fail_arrsp_ctx:
3734 ar_context_release(&ohci->ar_response_ctx);
3735 fail_arreq_ctx:
3736 ar_context_release(&ohci->ar_request_ctx);
3737 fail_misc_buf:
3738 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3739 ohci->misc_buffer, ohci->misc_buffer_bus);
3740 fail_iounmap:
3741 pci_iounmap(dev, ohci->registers);
3742 fail_iomem:
3743 pci_release_region(dev, 0);
3744 fail_disable:
3745 pci_disable_device(dev);
3746 fail_free:
3747 kfree(ohci);
3748 pmac_ohci_off(dev);
3749 fail:
3750 return err;
3751 }
3752
3753 static void pci_remove(struct pci_dev *dev)
3754 {
3755 struct fw_ohci *ohci = pci_get_drvdata(dev);
3756
3757 /*
3758 * If the removal is happening from the suspend state, LPS won't be
3759 * enabled and host registers (eg., IntMaskClear) won't be accessible.
3760 */
3761 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
3762 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3763 flush_writes(ohci);
3764 }
3765 cancel_work_sync(&ohci->bus_reset_work);
3766 fw_core_remove_card(&ohci->card);
3767
3768 /*
3769 * FIXME: Fail all pending packets here, now that the upper
3770 * layers can't queue any more.
3771 */
3772
3773 software_reset(ohci);
3774 free_irq(dev->irq, ohci);
3775
3776 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3777 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3778 ohci->next_config_rom, ohci->next_config_rom_bus);
3779 if (ohci->config_rom)
3780 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3781 ohci->config_rom, ohci->config_rom_bus);
3782 ar_context_release(&ohci->ar_request_ctx);
3783 ar_context_release(&ohci->ar_response_ctx);
3784 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3785 ohci->misc_buffer, ohci->misc_buffer_bus);
3786 context_release(&ohci->at_request_ctx);
3787 context_release(&ohci->at_response_ctx);
3788 kfree(ohci->it_context_list);
3789 kfree(ohci->ir_context_list);
3790 pci_disable_msi(dev);
3791 pci_iounmap(dev, ohci->registers);
3792 pci_release_region(dev, 0);
3793 pci_disable_device(dev);
3794 kfree(ohci);
3795 pmac_ohci_off(dev);
3796
3797 dev_notice(&dev->dev, "removed fw-ohci device\n");
3798 }
3799
3800 #ifdef CONFIG_PM
3801 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3802 {
3803 struct fw_ohci *ohci = pci_get_drvdata(dev);
3804 int err;
3805
3806 software_reset(ohci);
3807 err = pci_save_state(dev);
3808 if (err) {
3809 ohci_err(ohci, "pci_save_state failed\n");
3810 return err;
3811 }
3812 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3813 if (err)
3814 ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
3815 pmac_ohci_off(dev);
3816
3817 return 0;
3818 }
3819
3820 static int pci_resume(struct pci_dev *dev)
3821 {
3822 struct fw_ohci *ohci = pci_get_drvdata(dev);
3823 int err;
3824
3825 pmac_ohci_on(dev);
3826 pci_set_power_state(dev, PCI_D0);
3827 pci_restore_state(dev);
3828 err = pci_enable_device(dev);
3829 if (err) {
3830 ohci_err(ohci, "pci_enable_device failed\n");
3831 return err;
3832 }
3833
3834 /* Some systems don't setup GUID register on resume from ram */
3835 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3836 !reg_read(ohci, OHCI1394_GUIDHi)) {
3837 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3838 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3839 }
3840
3841 err = ohci_enable(&ohci->card, NULL, 0);
3842 if (err)
3843 return err;
3844
3845 ohci_resume_iso_dma(ohci);
3846
3847 return 0;
3848 }
3849 #endif
3850
3851 static const struct pci_device_id pci_table[] = {
3852 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3853 { }
3854 };
3855
3856 MODULE_DEVICE_TABLE(pci, pci_table);
3857
3858 static struct pci_driver fw_ohci_pci_driver = {
3859 .name = ohci_driver_name,
3860 .id_table = pci_table,
3861 .probe = pci_probe,
3862 .remove = pci_remove,
3863 #ifdef CONFIG_PM
3864 .resume = pci_resume,
3865 .suspend = pci_suspend,
3866 #endif
3867 };
3868
3869 static int __init fw_ohci_init(void)
3870 {
3871 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0);
3872 if (!selfid_workqueue)
3873 return -ENOMEM;
3874
3875 return pci_register_driver(&fw_ohci_pci_driver);
3876 }
3877
3878 static void __exit fw_ohci_cleanup(void)
3879 {
3880 pci_unregister_driver(&fw_ohci_pci_driver);
3881 destroy_workqueue(selfid_workqueue);
3882 }
3883
3884 module_init(fw_ohci_init);
3885 module_exit(fw_ohci_cleanup);
3886
3887 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3888 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3889 MODULE_LICENSE("GPL");
3890
3891 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3892 MODULE_ALIAS("ohci1394");
Linux with added FPC-III support