drivers/idle/intel_idle.c

   1 /*
   2  * intel_idle.c - native hardware idle loop for modern Intel processors
   3  *
   4  * Copyright (c) 2013, Intel Corporation.
   5  * Len Brown <len.brown@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 /*
  22  * intel_idle is a cpuidle driver that loads on specific Intel processors
  23  * in lieu of the legacy ACPI processor_idle driver.  The intent is to
  24  * make Linux more efficient on these processors, as intel_idle knows
  25  * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  26  */
  27
  28 /*
  29  * Design Assumptions
  30  *
  31  * All CPUs have same idle states as boot CPU
  32  *
  33  * Chipset BM_STS (bus master status) bit is a NOP
  34  *      for preventing entry into deep C-stats
  35  */
  36
  37 /*
  38  * Known limitations
  39  *
  40  * The driver currently initializes for_each_online_cpu() upon modprobe.
  41  * It it unaware of subsequent processors hot-added to the system.
  42  * This means that if you boot with maxcpus=n and later online
  43  * processors above n, those processors will use C1 only.
  44  *
  45  * ACPI has a .suspend hack to turn off deep c-statees during suspend
  46  * to avoid complications with the lapic timer workaround.
  47  * Have not seen issues with suspend, but may need same workaround here.
  48  *
  49  * There is currently no kernel-based automatic probing/loading mechanism
  50  * if the driver is built as a module.
  51  */
  52
  53 /* un-comment DEBUG to enable pr_debug() statements */
  54 #define DEBUG
  55
  56 #include <linux/kernel.h>
  57 #include <linux/cpuidle.h>
  58 #include <linux/clockchips.h>
  59 #include <trace/events/power.h>
  60 #include <linux/sched.h>
  61 #include <linux/notifier.h>
  62 #include <linux/cpu.h>
  63 #include <linux/module.h>
  64 #include <asm/cpu_device_id.h>
  65 #include <asm/mwait.h>
  66 #include <asm/msr.h>
  67
  68 #define INTEL_IDLE_VERSION "0.4"
  69 #define PREFIX "intel_idle: "
  70
  71 static struct cpuidle_driver intel_idle_driver = {
  72         .name = "intel_idle",
  73         .owner = THIS_MODULE,
  74 };
  75 /* intel_idle.max_cstate=0 disables driver */
  76 static int max_cstate = CPUIDLE_STATE_MAX - 1;
  77
  78 static unsigned int mwait_substates;
  79
  80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
  81 /* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
  82 static unsigned int lapic_timer_reliable_states = (1 << 1);      /* Default to only C1 */
  83
  84 struct idle_cpu {
  85         struct cpuidle_state *state_table;
  86
  87         /*
  88          * Hardware C-state auto-demotion may not always be optimal.
  89          * Indicate which enable bits to clear here.
  90          */
  91         unsigned long auto_demotion_disable_flags;
  92         bool disable_promotion_to_c1e;
  93 };
  94
  95 static const struct idle_cpu *icpu;
  96 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  97 static int intel_idle(struct cpuidle_device *dev,
  98                         struct cpuidle_driver *drv, int index);
  99 static int intel_idle_cpu_init(int cpu);
 100
 101 static struct cpuidle_state *cpuidle_state_table;
 102
 103 /*
 104  * Set this flag for states where the HW flushes the TLB for us
 105  * and so we don't need cross-calls to keep it consistent.
 106  * If this flag is set, SW flushes the TLB, so even if the
 107  * HW doesn't do the flushing, this flag is safe to use.
 108  */
 109 #define CPUIDLE_FLAG_TLB_FLUSHED        0x10000
 110
 111 /*
 112  * MWAIT takes an 8-bit "hint" in EAX "suggesting"
 113  * the C-state (top nibble) and sub-state (bottom nibble)
 114  * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
 115  *
 116  * We store the hint at the top of our "flags" for each state.
 117  */
 118 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
 119 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
 120
 121 /*
 122  * States are indexed by the cstate number,
 123  * which is also the index into the MWAIT hint array.
 124  * Thus C0 is a dummy.
 125  */
 126 static struct cpuidle_state nehalem_cstates[CPUIDLE_STATE_MAX] = {
 127         {
 128                 .name = "C1-NHM",
 129                 .desc = "MWAIT 0x00",
 130                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 131                 .exit_latency = 3,
 132                 .target_residency = 6,
 133                 .enter = &intel_idle },
 134         {
 135                 .name = "C1E-NHM",
 136                 .desc = "MWAIT 0x01",
 137                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 138                 .exit_latency = 10,
 139                 .target_residency = 20,
 140                 .enter = &intel_idle },
 141         {
 142                 .name = "C3-NHM",
 143                 .desc = "MWAIT 0x10",
 144                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 145                 .exit_latency = 20,
 146                 .target_residency = 80,
 147                 .enter = &intel_idle },
 148         {
 149                 .name = "C6-NHM",
 150                 .desc = "MWAIT 0x20",
 151                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 152                 .exit_latency = 200,
 153                 .target_residency = 800,
 154                 .enter = &intel_idle },
 155         {
 156                 .enter = NULL }
 157 };
 158
 159 static struct cpuidle_state snb_cstates[CPUIDLE_STATE_MAX] = {
 160         {
 161                 .name = "C1-SNB",
 162                 .desc = "MWAIT 0x00",
 163                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 164                 .exit_latency = 2,
 165                 .target_residency = 2,
 166                 .enter = &intel_idle },
 167         {
 168                 .name = "C1E-SNB",
 169                 .desc = "MWAIT 0x01",
 170                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 171                 .exit_latency = 10,
 172                 .target_residency = 20,
 173                 .enter = &intel_idle },
 174         {
 175                 .name = "C3-SNB",
 176                 .desc = "MWAIT 0x10",
 177                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 178                 .exit_latency = 80,
 179                 .target_residency = 211,
 180                 .enter = &intel_idle },
 181         {
 182                 .name = "C6-SNB",
 183                 .desc = "MWAIT 0x20",
 184                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 185                 .exit_latency = 104,
 186                 .target_residency = 345,
 187                 .enter = &intel_idle },
 188         {
 189                 .name = "C7-SNB",
 190                 .desc = "MWAIT 0x30",
 191                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 192                 .exit_latency = 109,
 193                 .target_residency = 345,
 194                 .enter = &intel_idle },
 195         {
 196                 .enter = NULL }
 197 };
 198
 199 static struct cpuidle_state ivb_cstates[CPUIDLE_STATE_MAX] = {
 200         {
 201                 .name = "C1-IVB",
 202                 .desc = "MWAIT 0x00",
 203                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 204                 .exit_latency = 1,
 205                 .target_residency = 1,
 206                 .enter = &intel_idle },
 207         {
 208                 .name = "C1E-IVB",
 209                 .desc = "MWAIT 0x01",
 210                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 211                 .exit_latency = 10,
 212                 .target_residency = 20,
 213                 .enter = &intel_idle },
 214         {
 215                 .name = "C3-IVB",
 216                 .desc = "MWAIT 0x10",
 217                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 218                 .exit_latency = 59,
 219                 .target_residency = 156,
 220                 .enter = &intel_idle },
 221         {
 222                 .name = "C6-IVB",
 223                 .desc = "MWAIT 0x20",
 224                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 225                 .exit_latency = 80,
 226                 .target_residency = 300,
 227                 .enter = &intel_idle },
 228         {
 229                 .name = "C7-IVB",
 230                 .desc = "MWAIT 0x30",
 231                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 232                 .exit_latency = 87,
 233                 .target_residency = 300,
 234                 .enter = &intel_idle },
 235         {
 236                 .enter = NULL }
 237 };
 238
 239 static struct cpuidle_state hsw_cstates[CPUIDLE_STATE_MAX] = {
 240         {
 241                 .name = "C1-HSW",
 242                 .desc = "MWAIT 0x00",
 243                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 244                 .exit_latency = 2,
 245                 .target_residency = 2,
 246                 .enter = &intel_idle },
 247         {
 248                 .name = "C1E-HSW",
 249                 .desc = "MWAIT 0x01",
 250                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 251                 .exit_latency = 10,
 252                 .target_residency = 20,
 253                 .enter = &intel_idle },
 254         {
 255                 .name = "C3-HSW",
 256                 .desc = "MWAIT 0x10",
 257                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 258                 .exit_latency = 33,
 259                 .target_residency = 100,
 260                 .enter = &intel_idle },
 261         {
 262                 .name = "C6-HSW",
 263                 .desc = "MWAIT 0x20",
 264                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 265                 .exit_latency = 133,
 266                 .target_residency = 400,
 267                 .enter = &intel_idle },
 268         {
 269                 .name = "C7s-HSW",
 270                 .desc = "MWAIT 0x32",
 271                 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 272                 .exit_latency = 166,
 273                 .target_residency = 500,
 274                 .enter = &intel_idle },
 275         {
 276                 .name = "C8-HSW",
 277                 .desc = "MWAIT 0x40",
 278                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 279                 .exit_latency = 300,
 280                 .target_residency = 900,
 281                 .enter = &intel_idle },
 282         {
 283                 .name = "C9-HSW",
 284                 .desc = "MWAIT 0x50",
 285                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 286                 .exit_latency = 600,
 287                 .target_residency = 1800,
 288                 .enter = &intel_idle },
 289         {
 290                 .name = "C10-HSW",
 291                 .desc = "MWAIT 0x60",
 292                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 293                 .exit_latency = 2600,
 294                 .target_residency = 7700,
 295                 .enter = &intel_idle },
 296         {
 297                 .enter = NULL }
 298 };
 299 static struct cpuidle_state bdw_cstates[] = {
 300         {
 301                 .name = "C1-BDW",
 302                 .desc = "MWAIT 0x00",
 303                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 304                 .exit_latency = 2,
 305                 .target_residency = 2,
 306                 .enter = &intel_idle },
 307         {
 308                 .name = "C1E-BDW",
 309                 .desc = "MWAIT 0x01",
 310                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 311                 .exit_latency = 10,
 312                 .target_residency = 20,
 313                 .enter = &intel_idle },
 314         {
 315                 .name = "C3-BDW",
 316                 .desc = "MWAIT 0x10",
 317                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 318                 .exit_latency = 40,
 319                 .target_residency = 100,
 320                 .enter = &intel_idle },
 321         {
 322                 .name = "C6-BDW",
 323                 .desc = "MWAIT 0x20",
 324                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 325                 .exit_latency = 133,
 326                 .target_residency = 400,
 327                 .enter = &intel_idle },
 328         {
 329                 .name = "C7s-BDW",
 330                 .desc = "MWAIT 0x32",
 331                 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 332                 .exit_latency = 166,
 333                 .target_residency = 500,
 334                 .enter = &intel_idle },
 335         {
 336                 .name = "C8-BDW",
 337                 .desc = "MWAIT 0x40",
 338                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 339                 .exit_latency = 300,
 340                 .target_residency = 900,
 341                 .enter = &intel_idle },
 342         {
 343                 .name = "C9-BDW",
 344                 .desc = "MWAIT 0x50",
 345                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 346                 .exit_latency = 600,
 347                 .target_residency = 1800,
 348                 .enter = &intel_idle },
 349         {
 350                 .name = "C10-BDW",
 351                 .desc = "MWAIT 0x60",
 352                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 353                 .exit_latency = 2600,
 354                 .target_residency = 7700,
 355                 .enter = &intel_idle },
 356         {
 357                 .enter = NULL }
 358 };
 359
 360 static struct cpuidle_state atom_cstates[CPUIDLE_STATE_MAX] = {
 361         {
 362                 .name = "C1E-ATM",
 363                 .desc = "MWAIT 0x00",
 364                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 365                 .exit_latency = 10,
 366                 .target_residency = 20,
 367                 .enter = &intel_idle },
 368         {
 369                 .name = "C2-ATM",
 370                 .desc = "MWAIT 0x10",
 371                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID,
 372                 .exit_latency = 20,
 373                 .target_residency = 80,
 374                 .enter = &intel_idle },
 375         {
 376                 .name = "C4-ATM",
 377                 .desc = "MWAIT 0x30",
 378                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 379                 .exit_latency = 100,
 380                 .target_residency = 400,
 381                 .enter = &intel_idle },
 382         {
 383                 .name = "C6-ATM",
 384                 .desc = "MWAIT 0x52",
 385                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 386                 .exit_latency = 140,
 387                 .target_residency = 560,
 388                 .enter = &intel_idle },
 389         {
 390                 .enter = NULL }
 391 };
 392 static struct cpuidle_state avn_cstates[] = {
 393         {
 394                 .name = "C1-AVN",
 395                 .desc = "MWAIT 0x00",
 396                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 397                 .exit_latency = 2,
 398                 .target_residency = 2,
 399                 .enter = &intel_idle },
 400         {
 401                 .name = "C6-AVN",
 402                 .desc = "MWAIT 0x51",
 403                 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 404                 .exit_latency = 15,
 405                 .target_residency = 45,
 406                 .enter = &intel_idle },
 407         {
 408                 .enter = NULL }
 409 };
 410
 411 /**
 412  * intel_idle
 413  * @dev: cpuidle_device
 414  * @drv: cpuidle driver
 415  * @index: index of cpuidle state
 416  *
 417  * Must be called under local_irq_disable().
 418  */
 419 static int intel_idle(struct cpuidle_device *dev,
 420                 struct cpuidle_driver *drv, int index)
 421 {
 422         unsigned long ecx = 1; /* break on interrupt flag */
 423         struct cpuidle_state *state = &drv->states[index];
 424         unsigned long eax = flg2MWAIT(state->flags);
 425         unsigned int cstate;
 426         int cpu = smp_processor_id();
 427
 428         cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
 429
 430         /*
 431          * leave_mm() to avoid costly and often unnecessary wakeups
 432          * for flushing the user TLB's associated with the active mm.
 433          */
 434         if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
 435                 leave_mm(cpu);
 436
 437         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 438                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 439
 440         if (!current_set_polling_and_test()) {
 441
 442                 if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
 443                         clflush((void *)&current_thread_info()->flags);
 444
 445                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 446                 smp_mb();
 447                 if (!need_resched())
 448                         __mwait(eax, ecx);
 449         }
 450
 451         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 452                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 453
 454         return index;
 455 }
 456
 457 static void __setup_broadcast_timer(void *arg)
 458 {
 459         unsigned long reason = (unsigned long)arg;
 460         int cpu = smp_processor_id();
 461
 462         reason = reason ?
 463                 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
 464
 465         clockevents_notify(reason, &cpu);
 466 }
 467
 468 static int cpu_hotplug_notify(struct notifier_block *n,
 469                               unsigned long action, void *hcpu)
 470 {
 471         int hotcpu = (unsigned long)hcpu;
 472         struct cpuidle_device *dev;
 473
 474         switch (action & 0xf) {
 475         case CPU_ONLINE:
 476
 477                 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 478                         smp_call_function_single(hotcpu, __setup_broadcast_timer,
 479                                                  (void *)true, 1);
 480
 481                 /*
 482                  * Some systems can hotplug a cpu at runtime after
 483                  * the kernel has booted, we have to initialize the
 484                  * driver in this case
 485                  */
 486                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
 487                 if (!dev->registered)
 488                         intel_idle_cpu_init(hotcpu);
 489
 490                 break;
 491         }
 492         return NOTIFY_OK;
 493 }
 494
 495 static struct notifier_block cpu_hotplug_notifier = {
 496         .notifier_call = cpu_hotplug_notify,
 497 };
 498
 499 static void auto_demotion_disable(void *dummy)
 500 {
 501         unsigned long long msr_bits;
 502
 503         rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 504         msr_bits &= ~(icpu->auto_demotion_disable_flags);
 505         wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 506 }
 507 static void c1e_promotion_disable(void *dummy)
 508 {
 509         unsigned long long msr_bits;
 510
 511         rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
 512         msr_bits &= ~0x2;
 513         wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
 514 }
 515
 516 static const struct idle_cpu idle_cpu_nehalem = {
 517         .state_table = nehalem_cstates,
 518         .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
 519         .disable_promotion_to_c1e = true,
 520 };
 521
 522 static const struct idle_cpu idle_cpu_atom = {
 523         .state_table = atom_cstates,
 524 };
 525
 526 static const struct idle_cpu idle_cpu_lincroft = {
 527         .state_table = atom_cstates,
 528         .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
 529 };
 530
 531 static const struct idle_cpu idle_cpu_snb = {
 532         .state_table = snb_cstates,
 533         .disable_promotion_to_c1e = true,
 534 };
 535
 536 static const struct idle_cpu idle_cpu_ivb = {
 537         .state_table = ivb_cstates,
 538         .disable_promotion_to_c1e = true,
 539 };
 540
 541 static const struct idle_cpu idle_cpu_hsw = {
 542         .state_table = hsw_cstates,
 543         .disable_promotion_to_c1e = true,
 544 };
 545
 546 static const struct idle_cpu idle_cpu_bdw = {
 547         .state_table = bdw_cstates,
 548         .disable_promotion_to_c1e = true,
 549 };
 550
 551 static const struct idle_cpu idle_cpu_avn = {
 552         .state_table = avn_cstates,
 553         .disable_promotion_to_c1e = true,
 554 };
 555
 556 #define ICPU(model, cpu) \
 557         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
 558
 559 static const struct x86_cpu_id intel_idle_ids[] = {
 560         ICPU(0x1a, idle_cpu_nehalem),
 561         ICPU(0x1e, idle_cpu_nehalem),
 562         ICPU(0x1f, idle_cpu_nehalem),
 563         ICPU(0x25, idle_cpu_nehalem),
 564         ICPU(0x2c, idle_cpu_nehalem),
 565         ICPU(0x2e, idle_cpu_nehalem),
 566         ICPU(0x1c, idle_cpu_atom),
 567         ICPU(0x26, idle_cpu_lincroft),
 568         ICPU(0x2f, idle_cpu_nehalem),
 569         ICPU(0x2a, idle_cpu_snb),
 570         ICPU(0x2d, idle_cpu_snb),
 571         ICPU(0x36, idle_cpu_atom),
 572         ICPU(0x3a, idle_cpu_ivb),
 573         ICPU(0x3e, idle_cpu_ivb),
 574         ICPU(0x3c, idle_cpu_hsw),
 575         ICPU(0x3f, idle_cpu_hsw),
 576         ICPU(0x45, idle_cpu_hsw),
 577         ICPU(0x46, idle_cpu_hsw),
 578         ICPU(0x4d, idle_cpu_avn),
 579         ICPU(0x3d, idle_cpu_bdw),
 580         ICPU(0x47, idle_cpu_bdw),
 581         ICPU(0x4f, idle_cpu_bdw),
 582         ICPU(0x56, idle_cpu_bdw),
 583         {}
 584 };
 585 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
 586
 587 /*
 588  * intel_idle_probe()
 589  */
 590 static int intel_idle_probe(void)
 591 {
 592         unsigned int eax, ebx, ecx;
 593         const struct x86_cpu_id *id;
 594
 595         if (max_cstate == 0) {
 596                 pr_debug(PREFIX "disabled\n");
 597                 return -EPERM;
 598         }
 599
 600         id = x86_match_cpu(intel_idle_ids);
 601         if (!id) {
 602                 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 603                     boot_cpu_data.x86 == 6)
 604                         pr_debug(PREFIX "does not run on family %d model %d\n",
 605                                 boot_cpu_data.x86, boot_cpu_data.x86_model);
 606                 return -ENODEV;
 607         }
 608
 609         if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
 610                 return -ENODEV;
 611
 612         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
 613
 614         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
 615             !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
 616             !mwait_substates)
 617                         return -ENODEV;
 618
 619         pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
 620
 621         icpu = (const struct idle_cpu *)id->driver_data;
 622         cpuidle_state_table = icpu->state_table;
 623
 624         if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
 625                 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
 626         else
 627                 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
 628
 629         pr_debug(PREFIX "v" INTEL_IDLE_VERSION
 630                 " model 0x%X\n", boot_cpu_data.x86_model);
 631
 632         pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
 633                 lapic_timer_reliable_states);
 634         return 0;
 635 }
 636
 637 /*
 638  * intel_idle_cpuidle_devices_uninit()
 639  * unregister, free cpuidle_devices
 640  */
 641 static void intel_idle_cpuidle_devices_uninit(void)
 642 {
 643         int i;
 644         struct cpuidle_device *dev;
 645
 646         for_each_online_cpu(i) {
 647                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 648                 cpuidle_unregister_device(dev);
 649         }
 650
 651         free_percpu(intel_idle_cpuidle_devices);
 652         return;
 653 }
 654 /*
 655  * intel_idle_cpuidle_driver_init()
 656  * allocate, initialize cpuidle_states
 657  */
 658 static int intel_idle_cpuidle_driver_init(void)
 659 {
 660         int cstate;
 661         struct cpuidle_driver *drv = &intel_idle_driver;
 662
 663         drv->state_count = 1;
 664
 665         for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
 666                 int num_substates, mwait_hint, mwait_cstate, mwait_substate;
 667
 668                 if (cpuidle_state_table[cstate].enter == NULL)
 669                         break;
 670
 671                 if (cstate + 1 > max_cstate) {
 672                         printk(PREFIX "max_cstate %d reached\n",
 673                                 max_cstate);
 674                         break;
 675                 }
 676
 677                 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
 678                 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
 679                 mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint);
 680
 681                 /* does the state exist in CPUID.MWAIT? */
 682                 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
 683                                         & MWAIT_SUBSTATE_MASK;
 684
 685                 /* if sub-state in table is not enumerated by CPUID */
 686                 if ((mwait_substate + 1) > num_substates)
 687                         continue;
 688
 689                 if (((mwait_cstate + 1) > 2) &&
 690                         !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 691                         mark_tsc_unstable("TSC halts in idle"
 692                                         " states deeper than C2");
 693
 694                 drv->states[drv->state_count] = /* structure copy */
 695                         cpuidle_state_table[cstate];
 696
 697                 drv->state_count += 1;
 698         }
 699
 700         if (icpu->auto_demotion_disable_flags)
 701                 on_each_cpu(auto_demotion_disable, NULL, 1);
 702
 703         if (icpu->disable_promotion_to_c1e)     /* each-cpu is redundant */
 704                 on_each_cpu(c1e_promotion_disable, NULL, 1);
 705
 706         return 0;
 707 }
 708
 709
 710 /*
 711  * intel_idle_cpu_init()
 712  * allocate, initialize, register cpuidle_devices
 713  * @cpu: cpu/core to initialize
 714  */
 715 static int intel_idle_cpu_init(int cpu)
 716 {
 717         int cstate;
 718         struct cpuidle_device *dev;
 719
 720         dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
 721
 722         dev->state_count = 1;
 723
 724         for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
 725                 int num_substates, mwait_hint, mwait_cstate, mwait_substate;
 726
 727                 if (cpuidle_state_table[cstate].enter == NULL)
 728                         continue;
 729
 730                 if (cstate + 1 > max_cstate) {
 731                         printk(PREFIX "max_cstate %d reached\n", max_cstate);
 732                         break;
 733                 }
 734
 735                 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
 736                 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
 737                 mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint);
 738
 739                 /* does the state exist in CPUID.MWAIT? */
 740                 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
 741                                         & MWAIT_SUBSTATE_MASK;
 742
 743                 /* if sub-state in table is not enumerated by CPUID */
 744                 if ((mwait_substate + 1) > num_substates)
 745                         continue;
 746
 747                 dev->state_count += 1;
 748         }
 749
 750         dev->cpu = cpu;
 751
 752         if (cpuidle_register_device(dev)) {
 753                 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
 754                 intel_idle_cpuidle_devices_uninit();
 755                 return -EIO;
 756         }
 757
 758         if (icpu->auto_demotion_disable_flags)
 759                 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
 760
 761         return 0;
 762 }
 763
 764 static int __init intel_idle_init(void)
 765 {
 766         int retval, i;
 767
 768         /* Do not load intel_idle at all for now if idle= is passed */
 769         if (boot_option_idle_override != IDLE_NO_OVERRIDE)
 770                 return -ENODEV;
 771
 772         retval = intel_idle_probe();
 773         if (retval)
 774                 return retval;
 775
 776         intel_idle_cpuidle_driver_init();
 777         retval = cpuidle_register_driver(&intel_idle_driver);
 778         if (retval) {
 779                 struct cpuidle_driver *drv = cpuidle_get_driver();
 780                 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
 781                         drv ? drv->name : "none");
 782                 return retval;
 783         }
 784
 785         intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
 786         if (intel_idle_cpuidle_devices == NULL)
 787                 return -ENOMEM;
 788
 789         for_each_online_cpu(i) {
 790                 retval = intel_idle_cpu_init(i);
 791                 if (retval) {
 792                         cpuidle_unregister_driver(&intel_idle_driver);
 793                         return retval;
 794                 }
 795         }
 796         register_cpu_notifier(&cpu_hotplug_notifier);
 797
 798         return 0;
 799 }
 800
 801 static void __exit intel_idle_exit(void)
 802 {
 803         intel_idle_cpuidle_devices_uninit();
 804         cpuidle_unregister_driver(&intel_idle_driver);
 805
 806
 807         if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 808                 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
 809         unregister_cpu_notifier(&cpu_hotplug_notifier);
 810
 811         return;
 812 }
 813
 814 module_init(intel_idle_init);
 815 module_exit(intel_idle_exit);
 816
 817 module_param(max_cstate, int, 0444);
 818
 819 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
 820 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
 821 MODULE_LICENSE("GPL");