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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / iommu / amd_iommu.c
blob73353a97aafb9a53c4afd003e723868014aad3a8
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <asm/irq_remapping.h>
37 #include <asm/io_apic.h>
38 #include <asm/apic.h>
39 #include <asm/hw_irq.h>
40 #include <asm/msidef.h>
41 #include <asm/proto.h>
42 #include <asm/iommu.h>
43 #include <asm/gart.h>
44 #include <asm/dma.h>
45
46 #include "amd_iommu_proto.h"
47 #include "amd_iommu_types.h"
48 #include "irq_remapping.h"
49 #include "pci.h"
50
51 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
52
53 #define LOOP_TIMEOUT 100000
54
55 /*
56 * This bitmap is used to advertise the page sizes our hardware support
57 * to the IOMMU core, which will then use this information to split
58 * physically contiguous memory regions it is mapping into page sizes
59 * that we support.
60 *
61 * 512GB Pages are not supported due to a hardware bug
62 */
63 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
64
65 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
66
67 /* A list of preallocated protection domains */
68 static LIST_HEAD(iommu_pd_list);
69 static DEFINE_SPINLOCK(iommu_pd_list_lock);
70
71 /* List of all available dev_data structures */
72 static LIST_HEAD(dev_data_list);
73 static DEFINE_SPINLOCK(dev_data_list_lock);
74
75 LIST_HEAD(ioapic_map);
76 LIST_HEAD(hpet_map);
77
78 /*
79 * Domain for untranslated devices - only allocated
80 * if iommu=pt passed on kernel cmd line.
81 */
82 static struct protection_domain *pt_domain;
83
84 static struct iommu_ops amd_iommu_ops;
85
86 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
87 int amd_iommu_max_glx_val = -1;
88
89 static struct dma_map_ops amd_iommu_dma_ops;
90
91 /*
92 * general struct to manage commands send to an IOMMU
93 */
94 struct iommu_cmd {
95 u32 data[4];
96 };
97
98 struct kmem_cache *amd_iommu_irq_cache;
99
100 static void update_domain(struct protection_domain *domain);
101 static int __init alloc_passthrough_domain(void);
102
103 /****************************************************************************
104 *
105 * Helper functions
106 *
107 ****************************************************************************/
108
109 static struct iommu_dev_data *alloc_dev_data(u16 devid)
110 {
111 struct iommu_dev_data *dev_data;
112 unsigned long flags;
113
114 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
115 if (!dev_data)
116 return NULL;
117
118 dev_data->devid = devid;
119 atomic_set(&dev_data->bind, 0);
120
121 spin_lock_irqsave(&dev_data_list_lock, flags);
122 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
123 spin_unlock_irqrestore(&dev_data_list_lock, flags);
124
125 return dev_data;
126 }
127
128 static void free_dev_data(struct iommu_dev_data *dev_data)
129 {
130 unsigned long flags;
131
132 spin_lock_irqsave(&dev_data_list_lock, flags);
133 list_del(&dev_data->dev_data_list);
134 spin_unlock_irqrestore(&dev_data_list_lock, flags);
135
136 if (dev_data->group)
137 iommu_group_put(dev_data->group);
138
139 kfree(dev_data);
140 }
141
142 static struct iommu_dev_data *search_dev_data(u16 devid)
143 {
144 struct iommu_dev_data *dev_data;
145 unsigned long flags;
146
147 spin_lock_irqsave(&dev_data_list_lock, flags);
148 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
149 if (dev_data->devid == devid)
150 goto out_unlock;
151 }
152
153 dev_data = NULL;
154
155 out_unlock:
156 spin_unlock_irqrestore(&dev_data_list_lock, flags);
157
158 return dev_data;
159 }
160
161 static struct iommu_dev_data *find_dev_data(u16 devid)
162 {
163 struct iommu_dev_data *dev_data;
164
165 dev_data = search_dev_data(devid);
166
167 if (dev_data == NULL)
168 dev_data = alloc_dev_data(devid);
169
170 return dev_data;
171 }
172
173 static inline u16 get_device_id(struct device *dev)
174 {
175 struct pci_dev *pdev = to_pci_dev(dev);
176
177 return PCI_DEVID(pdev->bus->number, pdev->devfn);
178 }
179
180 static struct iommu_dev_data *get_dev_data(struct device *dev)
181 {
182 return dev->archdata.iommu;
183 }
184
185 static bool pci_iommuv2_capable(struct pci_dev *pdev)
186 {
187 static const int caps[] = {
188 PCI_EXT_CAP_ID_ATS,
189 PCI_EXT_CAP_ID_PRI,
190 PCI_EXT_CAP_ID_PASID,
191 };
192 int i, pos;
193
194 for (i = 0; i < 3; ++i) {
195 pos = pci_find_ext_capability(pdev, caps[i]);
196 if (pos == 0)
197 return false;
198 }
199
200 return true;
201 }
202
203 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
204 {
205 struct iommu_dev_data *dev_data;
206
207 dev_data = get_dev_data(&pdev->dev);
208
209 return dev_data->errata & (1 << erratum) ? true : false;
210 }
211
212 /*
213 * In this function the list of preallocated protection domains is traversed to
214 * find the domain for a specific device
215 */
216 static struct dma_ops_domain *find_protection_domain(u16 devid)
217 {
218 struct dma_ops_domain *entry, *ret = NULL;
219 unsigned long flags;
220 u16 alias = amd_iommu_alias_table[devid];
221
222 if (list_empty(&iommu_pd_list))
223 return NULL;
224
225 spin_lock_irqsave(&iommu_pd_list_lock, flags);
226
227 list_for_each_entry(entry, &iommu_pd_list, list) {
228 if (entry->target_dev == devid ||
229 entry->target_dev == alias) {
230 ret = entry;
231 break;
232 }
233 }
234
235 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
236
237 return ret;
238 }
239
240 /*
241 * This function checks if the driver got a valid device from the caller to
242 * avoid dereferencing invalid pointers.
243 */
244 static bool check_device(struct device *dev)
245 {
246 u16 devid;
247
248 if (!dev || !dev->dma_mask)
249 return false;
250
251 /* No device or no PCI device */
252 if (dev->bus != &pci_bus_type)
253 return false;
254
255 devid = get_device_id(dev);
256
257 /* Out of our scope? */
258 if (devid > amd_iommu_last_bdf)
259 return false;
260
261 if (amd_iommu_rlookup_table[devid] == NULL)
262 return false;
263
264 return true;
265 }
266
267 static struct pci_bus *find_hosted_bus(struct pci_bus *bus)
268 {
269 while (!bus->self) {
270 if (!pci_is_root_bus(bus))
271 bus = bus->parent;
272 else
273 return ERR_PTR(-ENODEV);
274 }
275
276 return bus;
277 }
278
279 #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
280
281 static struct pci_dev *get_isolation_root(struct pci_dev *pdev)
282 {
283 struct pci_dev *dma_pdev = pdev;
284
285 /* Account for quirked devices */
286 swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));
287
288 /*
289 * If it's a multifunction device that does not support our
290 * required ACS flags, add to the same group as lowest numbered
291 * function that also does not suport the required ACS flags.
292 */
293 if (dma_pdev->multifunction &&
294 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) {
295 u8 i, slot = PCI_SLOT(dma_pdev->devfn);
296
297 for (i = 0; i < 8; i++) {
298 struct pci_dev *tmp;
299
300 tmp = pci_get_slot(dma_pdev->bus, PCI_DEVFN(slot, i));
301 if (!tmp)
302 continue;
303
304 if (!pci_acs_enabled(tmp, REQ_ACS_FLAGS)) {
305 swap_pci_ref(&dma_pdev, tmp);
306 break;
307 }
308 pci_dev_put(tmp);
309 }
310 }
311
312 /*
313 * Devices on the root bus go through the iommu. If that's not us,
314 * find the next upstream device and test ACS up to the root bus.
315 * Finding the next device may require skipping virtual buses.
316 */
317 while (!pci_is_root_bus(dma_pdev->bus)) {
318 struct pci_bus *bus = find_hosted_bus(dma_pdev->bus);
319 if (IS_ERR(bus))
320 break;
321
322 if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS))
323 break;
324
325 swap_pci_ref(&dma_pdev, pci_dev_get(bus->self));
326 }
327
328 return dma_pdev;
329 }
330
331 static int use_pdev_iommu_group(struct pci_dev *pdev, struct device *dev)
332 {
333 struct iommu_group *group = iommu_group_get(&pdev->dev);
334 int ret;
335
336 if (!group) {
337 group = iommu_group_alloc();
338 if (IS_ERR(group))
339 return PTR_ERR(group);
340
341 WARN_ON(&pdev->dev != dev);
342 }
343
344 ret = iommu_group_add_device(group, dev);
345 iommu_group_put(group);
346 return ret;
347 }
348
349 static int use_dev_data_iommu_group(struct iommu_dev_data *dev_data,
350 struct device *dev)
351 {
352 if (!dev_data->group) {
353 struct iommu_group *group = iommu_group_alloc();
354 if (IS_ERR(group))
355 return PTR_ERR(group);
356
357 dev_data->group = group;
358 }
359
360 return iommu_group_add_device(dev_data->group, dev);
361 }
362
363 static int init_iommu_group(struct device *dev)
364 {
365 struct iommu_dev_data *dev_data;
366 struct iommu_group *group;
367 struct pci_dev *dma_pdev;
368 int ret;
369
370 group = iommu_group_get(dev);
371 if (group) {
372 iommu_group_put(group);
373 return 0;
374 }
375
376 dev_data = find_dev_data(get_device_id(dev));
377 if (!dev_data)
378 return -ENOMEM;
379
380 if (dev_data->alias_data) {
381 u16 alias;
382 struct pci_bus *bus;
383
384 if (dev_data->alias_data->group)
385 goto use_group;
386
387 /*
388 * If the alias device exists, it's effectively just a first
389 * level quirk for finding the DMA source.
390 */
391 alias = amd_iommu_alias_table[dev_data->devid];
392 dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff);
393 if (dma_pdev) {
394 dma_pdev = get_isolation_root(dma_pdev);
395 goto use_pdev;
396 }
397
398 /*
399 * If the alias is virtual, try to find a parent device
400 * and test whether the IOMMU group is actualy rooted above
401 * the alias. Be careful to also test the parent device if
402 * we think the alias is the root of the group.
403 */
404 bus = pci_find_bus(0, alias >> 8);
405 if (!bus)
406 goto use_group;
407
408 bus = find_hosted_bus(bus);
409 if (IS_ERR(bus) || !bus->self)
410 goto use_group;
411
412 dma_pdev = get_isolation_root(pci_dev_get(bus->self));
413 if (dma_pdev != bus->self || (dma_pdev->multifunction &&
414 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)))
415 goto use_pdev;
416
417 pci_dev_put(dma_pdev);
418 goto use_group;
419 }
420
421 dma_pdev = get_isolation_root(pci_dev_get(to_pci_dev(dev)));
422 use_pdev:
423 ret = use_pdev_iommu_group(dma_pdev, dev);
424 pci_dev_put(dma_pdev);
425 return ret;
426 use_group:
427 return use_dev_data_iommu_group(dev_data->alias_data, dev);
428 }
429
430 static int iommu_init_device(struct device *dev)
431 {
432 struct pci_dev *pdev = to_pci_dev(dev);
433 struct iommu_dev_data *dev_data;
434 u16 alias;
435 int ret;
436
437 if (dev->archdata.iommu)
438 return 0;
439
440 dev_data = find_dev_data(get_device_id(dev));
441 if (!dev_data)
442 return -ENOMEM;
443
444 alias = amd_iommu_alias_table[dev_data->devid];
445 if (alias != dev_data->devid) {
446 struct iommu_dev_data *alias_data;
447
448 alias_data = find_dev_data(alias);
449 if (alias_data == NULL) {
450 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
451 dev_name(dev));
452 free_dev_data(dev_data);
453 return -ENOTSUPP;
454 }
455 dev_data->alias_data = alias_data;
456 }
457
458 ret = init_iommu_group(dev);
459 if (ret) {
460 free_dev_data(dev_data);
461 return ret;
462 }
463
464 if (pci_iommuv2_capable(pdev)) {
465 struct amd_iommu *iommu;
466
467 iommu = amd_iommu_rlookup_table[dev_data->devid];
468 dev_data->iommu_v2 = iommu->is_iommu_v2;
469 }
470
471 dev->archdata.iommu = dev_data;
472
473 return 0;
474 }
475
476 static void iommu_ignore_device(struct device *dev)
477 {
478 u16 devid, alias;
479
480 devid = get_device_id(dev);
481 alias = amd_iommu_alias_table[devid];
482
483 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
484 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
485
486 amd_iommu_rlookup_table[devid] = NULL;
487 amd_iommu_rlookup_table[alias] = NULL;
488 }
489
490 static void iommu_uninit_device(struct device *dev)
491 {
492 iommu_group_remove_device(dev);
493
494 /*
495 * Nothing to do here - we keep dev_data around for unplugged devices
496 * and reuse it when the device is re-plugged - not doing so would
497 * introduce a ton of races.
498 */
499 }
500
501 void __init amd_iommu_uninit_devices(void)
502 {
503 struct iommu_dev_data *dev_data, *n;
504 struct pci_dev *pdev = NULL;
505
506 for_each_pci_dev(pdev) {
507
508 if (!check_device(&pdev->dev))
509 continue;
510
511 iommu_uninit_device(&pdev->dev);
512 }
513
514 /* Free all of our dev_data structures */
515 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
516 free_dev_data(dev_data);
517 }
518
519 int __init amd_iommu_init_devices(void)
520 {
521 struct pci_dev *pdev = NULL;
522 int ret = 0;
523
524 for_each_pci_dev(pdev) {
525
526 if (!check_device(&pdev->dev))
527 continue;
528
529 ret = iommu_init_device(&pdev->dev);
530 if (ret == -ENOTSUPP)
531 iommu_ignore_device(&pdev->dev);
532 else if (ret)
533 goto out_free;
534 }
535
536 return 0;
537
538 out_free:
539
540 amd_iommu_uninit_devices();
541
542 return ret;
543 }
544 #ifdef CONFIG_AMD_IOMMU_STATS
545
546 /*
547 * Initialization code for statistics collection
548 */
549
550 DECLARE_STATS_COUNTER(compl_wait);
551 DECLARE_STATS_COUNTER(cnt_map_single);
552 DECLARE_STATS_COUNTER(cnt_unmap_single);
553 DECLARE_STATS_COUNTER(cnt_map_sg);
554 DECLARE_STATS_COUNTER(cnt_unmap_sg);
555 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
556 DECLARE_STATS_COUNTER(cnt_free_coherent);
557 DECLARE_STATS_COUNTER(cross_page);
558 DECLARE_STATS_COUNTER(domain_flush_single);
559 DECLARE_STATS_COUNTER(domain_flush_all);
560 DECLARE_STATS_COUNTER(alloced_io_mem);
561 DECLARE_STATS_COUNTER(total_map_requests);
562 DECLARE_STATS_COUNTER(complete_ppr);
563 DECLARE_STATS_COUNTER(invalidate_iotlb);
564 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
565 DECLARE_STATS_COUNTER(pri_requests);
566
567 static struct dentry *stats_dir;
568 static struct dentry *de_fflush;
569
570 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
571 {
572 if (stats_dir == NULL)
573 return;
574
575 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
576 &cnt->value);
577 }
578
579 static void amd_iommu_stats_init(void)
580 {
581 stats_dir = debugfs_create_dir("amd-iommu", NULL);
582 if (stats_dir == NULL)
583 return;
584
585 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
586 &amd_iommu_unmap_flush);
587
588 amd_iommu_stats_add(&compl_wait);
589 amd_iommu_stats_add(&cnt_map_single);
590 amd_iommu_stats_add(&cnt_unmap_single);
591 amd_iommu_stats_add(&cnt_map_sg);
592 amd_iommu_stats_add(&cnt_unmap_sg);
593 amd_iommu_stats_add(&cnt_alloc_coherent);
594 amd_iommu_stats_add(&cnt_free_coherent);
595 amd_iommu_stats_add(&cross_page);
596 amd_iommu_stats_add(&domain_flush_single);
597 amd_iommu_stats_add(&domain_flush_all);
598 amd_iommu_stats_add(&alloced_io_mem);
599 amd_iommu_stats_add(&total_map_requests);
600 amd_iommu_stats_add(&complete_ppr);
601 amd_iommu_stats_add(&invalidate_iotlb);
602 amd_iommu_stats_add(&invalidate_iotlb_all);
603 amd_iommu_stats_add(&pri_requests);
604 }
605
606 #endif
607
608 /****************************************************************************
609 *
610 * Interrupt handling functions
611 *
612 ****************************************************************************/
613
614 static void dump_dte_entry(u16 devid)
615 {
616 int i;
617
618 for (i = 0; i < 4; ++i)
619 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
620 amd_iommu_dev_table[devid].data[i]);
621 }
622
623 static void dump_command(unsigned long phys_addr)
624 {
625 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
626 int i;
627
628 for (i = 0; i < 4; ++i)
629 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
630 }
631
632 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
633 {
634 int type, devid, domid, flags;
635 volatile u32 *event = __evt;
636 int count = 0;
637 u64 address;
638
639 retry:
640 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
641 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
642 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
643 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
644 address = (u64)(((u64)event[3]) << 32) | event[2];
645
646 if (type == 0) {
647 /* Did we hit the erratum? */
648 if (++count == LOOP_TIMEOUT) {
649 pr_err("AMD-Vi: No event written to event log\n");
650 return;
651 }
652 udelay(1);
653 goto retry;
654 }
655
656 printk(KERN_ERR "AMD-Vi: Event logged [");
657
658 switch (type) {
659 case EVENT_TYPE_ILL_DEV:
660 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
661 "address=0x%016llx flags=0x%04x]\n",
662 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
663 address, flags);
664 dump_dte_entry(devid);
665 break;
666 case EVENT_TYPE_IO_FAULT:
667 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
668 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
669 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
670 domid, address, flags);
671 break;
672 case EVENT_TYPE_DEV_TAB_ERR:
673 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
674 "address=0x%016llx flags=0x%04x]\n",
675 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
676 address, flags);
677 break;
678 case EVENT_TYPE_PAGE_TAB_ERR:
679 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
680 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
681 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
682 domid, address, flags);
683 break;
684 case EVENT_TYPE_ILL_CMD:
685 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
686 dump_command(address);
687 break;
688 case EVENT_TYPE_CMD_HARD_ERR:
689 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
690 "flags=0x%04x]\n", address, flags);
691 break;
692 case EVENT_TYPE_IOTLB_INV_TO:
693 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
694 "address=0x%016llx]\n",
695 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
696 address);
697 break;
698 case EVENT_TYPE_INV_DEV_REQ:
699 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
700 "address=0x%016llx flags=0x%04x]\n",
701 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
702 address, flags);
703 break;
704 default:
705 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
706 }
707
708 memset(__evt, 0, 4 * sizeof(u32));
709 }
710
711 static void iommu_poll_events(struct amd_iommu *iommu)
712 {
713 u32 head, tail;
714
715 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
716 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
717
718 while (head != tail) {
719 iommu_print_event(iommu, iommu->evt_buf + head);
720 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
721 }
722
723 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
724 }
725
726 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
727 {
728 struct amd_iommu_fault fault;
729
730 INC_STATS_COUNTER(pri_requests);
731
732 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
733 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
734 return;
735 }
736
737 fault.address = raw[1];
738 fault.pasid = PPR_PASID(raw[0]);
739 fault.device_id = PPR_DEVID(raw[0]);
740 fault.tag = PPR_TAG(raw[0]);
741 fault.flags = PPR_FLAGS(raw[0]);
742
743 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
744 }
745
746 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
747 {
748 u32 head, tail;
749
750 if (iommu->ppr_log == NULL)
751 return;
752
753 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
754 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
755
756 while (head != tail) {
757 volatile u64 *raw;
758 u64 entry[2];
759 int i;
760
761 raw = (u64 *)(iommu->ppr_log + head);
762
763 /*
764 * Hardware bug: Interrupt may arrive before the entry is
765 * written to memory. If this happens we need to wait for the
766 * entry to arrive.
767 */
768 for (i = 0; i < LOOP_TIMEOUT; ++i) {
769 if (PPR_REQ_TYPE(raw[0]) != 0)
770 break;
771 udelay(1);
772 }
773
774 /* Avoid memcpy function-call overhead */
775 entry[0] = raw[0];
776 entry[1] = raw[1];
777
778 /*
779 * To detect the hardware bug we need to clear the entry
780 * back to zero.
781 */
782 raw[0] = raw[1] = 0UL;
783
784 /* Update head pointer of hardware ring-buffer */
785 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
786 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
787
788 /* Handle PPR entry */
789 iommu_handle_ppr_entry(iommu, entry);
790
791 /* Refresh ring-buffer information */
792 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
793 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
794 }
795 }
796
797 irqreturn_t amd_iommu_int_thread(int irq, void *data)
798 {
799 struct amd_iommu *iommu = (struct amd_iommu *) data;
800 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
801
802 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
803 /* Enable EVT and PPR interrupts again */
804 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
805 iommu->mmio_base + MMIO_STATUS_OFFSET);
806
807 if (status & MMIO_STATUS_EVT_INT_MASK) {
808 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
809 iommu_poll_events(iommu);
810 }
811
812 if (status & MMIO_STATUS_PPR_INT_MASK) {
813 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
814 iommu_poll_ppr_log(iommu);
815 }
816
817 /*
818 * Hardware bug: ERBT1312
819 * When re-enabling interrupt (by writing 1
820 * to clear the bit), the hardware might also try to set
821 * the interrupt bit in the event status register.
822 * In this scenario, the bit will be set, and disable
823 * subsequent interrupts.
824 *
825 * Workaround: The IOMMU driver should read back the
826 * status register and check if the interrupt bits are cleared.
827 * If not, driver will need to go through the interrupt handler
828 * again and re-clear the bits
829 */
830 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
831 }
832 return IRQ_HANDLED;
833 }
834
835 irqreturn_t amd_iommu_int_handler(int irq, void *data)
836 {
837 return IRQ_WAKE_THREAD;
838 }
839
840 /****************************************************************************
841 *
842 * IOMMU command queuing functions
843 *
844 ****************************************************************************/
845
846 static int wait_on_sem(volatile u64 *sem)
847 {
848 int i = 0;
849
850 while (*sem == 0 && i < LOOP_TIMEOUT) {
851 udelay(1);
852 i += 1;
853 }
854
855 if (i == LOOP_TIMEOUT) {
856 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
857 return -EIO;
858 }
859
860 return 0;
861 }
862
863 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
864 struct iommu_cmd *cmd,
865 u32 tail)
866 {
867 u8 *target;
868
869 target = iommu->cmd_buf + tail;
870 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
871
872 /* Copy command to buffer */
873 memcpy(target, cmd, sizeof(*cmd));
874
875 /* Tell the IOMMU about it */
876 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
877 }
878
879 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
880 {
881 WARN_ON(address & 0x7ULL);
882
883 memset(cmd, 0, sizeof(*cmd));
884 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
885 cmd->data[1] = upper_32_bits(__pa(address));
886 cmd->data[2] = 1;
887 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
888 }
889
890 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
891 {
892 memset(cmd, 0, sizeof(*cmd));
893 cmd->data[0] = devid;
894 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
895 }
896
897 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
898 size_t size, u16 domid, int pde)
899 {
900 u64 pages;
901 int s;
902
903 pages = iommu_num_pages(address, size, PAGE_SIZE);
904 s = 0;
905
906 if (pages > 1) {
907 /*
908 * If we have to flush more than one page, flush all
909 * TLB entries for this domain
910 */
911 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
912 s = 1;
913 }
914
915 address &= PAGE_MASK;
916
917 memset(cmd, 0, sizeof(*cmd));
918 cmd->data[1] |= domid;
919 cmd->data[2] = lower_32_bits(address);
920 cmd->data[3] = upper_32_bits(address);
921 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
922 if (s) /* size bit - we flush more than one 4kb page */
923 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
924 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
925 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
926 }
927
928 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
929 u64 address, size_t size)
930 {
931 u64 pages;
932 int s;
933
934 pages = iommu_num_pages(address, size, PAGE_SIZE);
935 s = 0;
936
937 if (pages > 1) {
938 /*
939 * If we have to flush more than one page, flush all
940 * TLB entries for this domain
941 */
942 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
943 s = 1;
944 }
945
946 address &= PAGE_MASK;
947
948 memset(cmd, 0, sizeof(*cmd));
949 cmd->data[0] = devid;
950 cmd->data[0] |= (qdep & 0xff) << 24;
951 cmd->data[1] = devid;
952 cmd->data[2] = lower_32_bits(address);
953 cmd->data[3] = upper_32_bits(address);
954 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
955 if (s)
956 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
957 }
958
959 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
960 u64 address, bool size)
961 {
962 memset(cmd, 0, sizeof(*cmd));
963
964 address &= ~(0xfffULL);
965
966 cmd->data[0] = pasid & PASID_MASK;
967 cmd->data[1] = domid;
968 cmd->data[2] = lower_32_bits(address);
969 cmd->data[3] = upper_32_bits(address);
970 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
971 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
972 if (size)
973 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
974 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
975 }
976
977 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
978 int qdep, u64 address, bool size)
979 {
980 memset(cmd, 0, sizeof(*cmd));
981
982 address &= ~(0xfffULL);
983
984 cmd->data[0] = devid;
985 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
986 cmd->data[0] |= (qdep & 0xff) << 24;
987 cmd->data[1] = devid;
988 cmd->data[1] |= (pasid & 0xff) << 16;
989 cmd->data[2] = lower_32_bits(address);
990 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
991 cmd->data[3] = upper_32_bits(address);
992 if (size)
993 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
994 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
995 }
996
997 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
998 int status, int tag, bool gn)
999 {
1000 memset(cmd, 0, sizeof(*cmd));
1001
1002 cmd->data[0] = devid;
1003 if (gn) {
1004 cmd->data[1] = pasid & PASID_MASK;
1005 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1006 }
1007 cmd->data[3] = tag & 0x1ff;
1008 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1009
1010 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1011 }
1012
1013 static void build_inv_all(struct iommu_cmd *cmd)
1014 {
1015 memset(cmd, 0, sizeof(*cmd));
1016 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1017 }
1018
1019 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1020 {
1021 memset(cmd, 0, sizeof(*cmd));
1022 cmd->data[0] = devid;
1023 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1024 }
1025
1026 /*
1027 * Writes the command to the IOMMUs command buffer and informs the
1028 * hardware about the new command.
1029 */
1030 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1031 struct iommu_cmd *cmd,
1032 bool sync)
1033 {
1034 u32 left, tail, head, next_tail;
1035 unsigned long flags;
1036
1037 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
1038
1039 again:
1040 spin_lock_irqsave(&iommu->lock, flags);
1041
1042 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
1043 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
1044 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
1045 left = (head - next_tail) % iommu->cmd_buf_size;
1046
1047 if (left <= 2) {
1048 struct iommu_cmd sync_cmd;
1049 volatile u64 sem = 0;
1050 int ret;
1051
1052 build_completion_wait(&sync_cmd, (u64)&sem);
1053 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
1054
1055 spin_unlock_irqrestore(&iommu->lock, flags);
1056
1057 if ((ret = wait_on_sem(&sem)) != 0)
1058 return ret;
1059
1060 goto again;
1061 }
1062
1063 copy_cmd_to_buffer(iommu, cmd, tail);
1064
1065 /* We need to sync now to make sure all commands are processed */
1066 iommu->need_sync = sync;
1067
1068 spin_unlock_irqrestore(&iommu->lock, flags);
1069
1070 return 0;
1071 }
1072
1073 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1074 {
1075 return iommu_queue_command_sync(iommu, cmd, true);
1076 }
1077
1078 /*
1079 * This function queues a completion wait command into the command
1080 * buffer of an IOMMU
1081 */
1082 static int iommu_completion_wait(struct amd_iommu *iommu)
1083 {
1084 struct iommu_cmd cmd;
1085 volatile u64 sem = 0;
1086 int ret;
1087
1088 if (!iommu->need_sync)
1089 return 0;
1090
1091 build_completion_wait(&cmd, (u64)&sem);
1092
1093 ret = iommu_queue_command_sync(iommu, &cmd, false);
1094 if (ret)
1095 return ret;
1096
1097 return wait_on_sem(&sem);
1098 }
1099
1100 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1101 {
1102 struct iommu_cmd cmd;
1103
1104 build_inv_dte(&cmd, devid);
1105
1106 return iommu_queue_command(iommu, &cmd);
1107 }
1108
1109 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1110 {
1111 u32 devid;
1112
1113 for (devid = 0; devid <= 0xffff; ++devid)
1114 iommu_flush_dte(iommu, devid);
1115
1116 iommu_completion_wait(iommu);
1117 }
1118
1119 /*
1120 * This function uses heavy locking and may disable irqs for some time. But
1121 * this is no issue because it is only called during resume.
1122 */
1123 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1124 {
1125 u32 dom_id;
1126
1127 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1128 struct iommu_cmd cmd;
1129 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1130 dom_id, 1);
1131 iommu_queue_command(iommu, &cmd);
1132 }
1133
1134 iommu_completion_wait(iommu);
1135 }
1136
1137 static void iommu_flush_all(struct amd_iommu *iommu)
1138 {
1139 struct iommu_cmd cmd;
1140
1141 build_inv_all(&cmd);
1142
1143 iommu_queue_command(iommu, &cmd);
1144 iommu_completion_wait(iommu);
1145 }
1146
1147 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1148 {
1149 struct iommu_cmd cmd;
1150
1151 build_inv_irt(&cmd, devid);
1152
1153 iommu_queue_command(iommu, &cmd);
1154 }
1155
1156 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1157 {
1158 u32 devid;
1159
1160 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1161 iommu_flush_irt(iommu, devid);
1162
1163 iommu_completion_wait(iommu);
1164 }
1165
1166 void iommu_flush_all_caches(struct amd_iommu *iommu)
1167 {
1168 if (iommu_feature(iommu, FEATURE_IA)) {
1169 iommu_flush_all(iommu);
1170 } else {
1171 iommu_flush_dte_all(iommu);
1172 iommu_flush_irt_all(iommu);
1173 iommu_flush_tlb_all(iommu);
1174 }
1175 }
1176
1177 /*
1178 * Command send function for flushing on-device TLB
1179 */
1180 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1181 u64 address, size_t size)
1182 {
1183 struct amd_iommu *iommu;
1184 struct iommu_cmd cmd;
1185 int qdep;
1186
1187 qdep = dev_data->ats.qdep;
1188 iommu = amd_iommu_rlookup_table[dev_data->devid];
1189
1190 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1191
1192 return iommu_queue_command(iommu, &cmd);
1193 }
1194
1195 /*
1196 * Command send function for invalidating a device table entry
1197 */
1198 static int device_flush_dte(struct iommu_dev_data *dev_data)
1199 {
1200 struct amd_iommu *iommu;
1201 int ret;
1202
1203 iommu = amd_iommu_rlookup_table[dev_data->devid];
1204
1205 ret = iommu_flush_dte(iommu, dev_data->devid);
1206 if (ret)
1207 return ret;
1208
1209 if (dev_data->ats.enabled)
1210 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1211
1212 return ret;
1213 }
1214
1215 /*
1216 * TLB invalidation function which is called from the mapping functions.
1217 * It invalidates a single PTE if the range to flush is within a single
1218 * page. Otherwise it flushes the whole TLB of the IOMMU.
1219 */
1220 static void __domain_flush_pages(struct protection_domain *domain,
1221 u64 address, size_t size, int pde)
1222 {
1223 struct iommu_dev_data *dev_data;
1224 struct iommu_cmd cmd;
1225 int ret = 0, i;
1226
1227 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1228
1229 for (i = 0; i < amd_iommus_present; ++i) {
1230 if (!domain->dev_iommu[i])
1231 continue;
1232
1233 /*
1234 * Devices of this domain are behind this IOMMU
1235 * We need a TLB flush
1236 */
1237 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1238 }
1239
1240 list_for_each_entry(dev_data, &domain->dev_list, list) {
1241
1242 if (!dev_data->ats.enabled)
1243 continue;
1244
1245 ret |= device_flush_iotlb(dev_data, address, size);
1246 }
1247
1248 WARN_ON(ret);
1249 }
1250
1251 static void domain_flush_pages(struct protection_domain *domain,
1252 u64 address, size_t size)
1253 {
1254 __domain_flush_pages(domain, address, size, 0);
1255 }
1256
1257 /* Flush the whole IO/TLB for a given protection domain */
1258 static void domain_flush_tlb(struct protection_domain *domain)
1259 {
1260 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1261 }
1262
1263 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1264 static void domain_flush_tlb_pde(struct protection_domain *domain)
1265 {
1266 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1267 }
1268
1269 static void domain_flush_complete(struct protection_domain *domain)
1270 {
1271 int i;
1272
1273 for (i = 0; i < amd_iommus_present; ++i) {
1274 if (!domain->dev_iommu[i])
1275 continue;
1276
1277 /*
1278 * Devices of this domain are behind this IOMMU
1279 * We need to wait for completion of all commands.
1280 */
1281 iommu_completion_wait(amd_iommus[i]);
1282 }
1283 }
1284
1285
1286 /*
1287 * This function flushes the DTEs for all devices in domain
1288 */
1289 static void domain_flush_devices(struct protection_domain *domain)
1290 {
1291 struct iommu_dev_data *dev_data;
1292
1293 list_for_each_entry(dev_data, &domain->dev_list, list)
1294 device_flush_dte(dev_data);
1295 }
1296
1297 /****************************************************************************
1298 *
1299 * The functions below are used the create the page table mappings for
1300 * unity mapped regions.
1301 *
1302 ****************************************************************************/
1303
1304 /*
1305 * This function is used to add another level to an IO page table. Adding
1306 * another level increases the size of the address space by 9 bits to a size up
1307 * to 64 bits.
1308 */
1309 static bool increase_address_space(struct protection_domain *domain,
1310 gfp_t gfp)
1311 {
1312 u64 *pte;
1313
1314 if (domain->mode == PAGE_MODE_6_LEVEL)
1315 /* address space already 64 bit large */
1316 return false;
1317
1318 pte = (void *)get_zeroed_page(gfp);
1319 if (!pte)
1320 return false;
1321
1322 *pte = PM_LEVEL_PDE(domain->mode,
1323 virt_to_phys(domain->pt_root));
1324 domain->pt_root = pte;
1325 domain->mode += 1;
1326 domain->updated = true;
1327
1328 return true;
1329 }
1330
1331 static u64 *alloc_pte(struct protection_domain *domain,
1332 unsigned long address,
1333 unsigned long page_size,
1334 u64 **pte_page,
1335 gfp_t gfp)
1336 {
1337 int level, end_lvl;
1338 u64 *pte, *page;
1339
1340 BUG_ON(!is_power_of_2(page_size));
1341
1342 while (address > PM_LEVEL_SIZE(domain->mode))
1343 increase_address_space(domain, gfp);
1344
1345 level = domain->mode - 1;
1346 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1347 address = PAGE_SIZE_ALIGN(address, page_size);
1348 end_lvl = PAGE_SIZE_LEVEL(page_size);
1349
1350 while (level > end_lvl) {
1351 if (!IOMMU_PTE_PRESENT(*pte)) {
1352 page = (u64 *)get_zeroed_page(gfp);
1353 if (!page)
1354 return NULL;
1355 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1356 }
1357
1358 /* No level skipping support yet */
1359 if (PM_PTE_LEVEL(*pte) != level)
1360 return NULL;
1361
1362 level -= 1;
1363
1364 pte = IOMMU_PTE_PAGE(*pte);
1365
1366 if (pte_page && level == end_lvl)
1367 *pte_page = pte;
1368
1369 pte = &pte[PM_LEVEL_INDEX(level, address)];
1370 }
1371
1372 return pte;
1373 }
1374
1375 /*
1376 * This function checks if there is a PTE for a given dma address. If
1377 * there is one, it returns the pointer to it.
1378 */
1379 static u64 *fetch_pte(struct protection_domain *domain,
1380 unsigned long address,
1381 unsigned long *page_size)
1382 {
1383 int level;
1384 u64 *pte;
1385
1386 if (address > PM_LEVEL_SIZE(domain->mode))
1387 return NULL;
1388
1389 level = domain->mode - 1;
1390 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1391 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1392
1393 while (level > 0) {
1394
1395 /* Not Present */
1396 if (!IOMMU_PTE_PRESENT(*pte))
1397 return NULL;
1398
1399 /* Large PTE */
1400 if (PM_PTE_LEVEL(*pte) == 7 ||
1401 PM_PTE_LEVEL(*pte) == 0)
1402 break;
1403
1404 /* No level skipping support yet */
1405 if (PM_PTE_LEVEL(*pte) != level)
1406 return NULL;
1407
1408 level -= 1;
1409
1410 /* Walk to the next level */
1411 pte = IOMMU_PTE_PAGE(*pte);
1412 pte = &pte[PM_LEVEL_INDEX(level, address)];
1413 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1414 }
1415
1416 if (PM_PTE_LEVEL(*pte) == 0x07) {
1417 unsigned long pte_mask;
1418
1419 /*
1420 * If we have a series of large PTEs, make
1421 * sure to return a pointer to the first one.
1422 */
1423 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1424 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1425 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1426 }
1427
1428 return pte;
1429 }
1430
1431 /*
1432 * Generic mapping functions. It maps a physical address into a DMA
1433 * address space. It allocates the page table pages if necessary.
1434 * In the future it can be extended to a generic mapping function
1435 * supporting all features of AMD IOMMU page tables like level skipping
1436 * and full 64 bit address spaces.
1437 */
1438 static int iommu_map_page(struct protection_domain *dom,
1439 unsigned long bus_addr,
1440 unsigned long phys_addr,
1441 int prot,
1442 unsigned long page_size)
1443 {
1444 u64 __pte, *pte;
1445 int i, count;
1446
1447 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1448 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1449
1450 if (!(prot & IOMMU_PROT_MASK))
1451 return -EINVAL;
1452
1453 count = PAGE_SIZE_PTE_COUNT(page_size);
1454 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1455
1456 for (i = 0; i < count; ++i)
1457 if (IOMMU_PTE_PRESENT(pte[i]))
1458 return -EBUSY;
1459
1460 if (count > 1) {
1461 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1462 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1463 } else
1464 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1465
1466 if (prot & IOMMU_PROT_IR)
1467 __pte |= IOMMU_PTE_IR;
1468 if (prot & IOMMU_PROT_IW)
1469 __pte |= IOMMU_PTE_IW;
1470
1471 for (i = 0; i < count; ++i)
1472 pte[i] = __pte;
1473
1474 update_domain(dom);
1475
1476 return 0;
1477 }
1478
1479 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1480 unsigned long bus_addr,
1481 unsigned long page_size)
1482 {
1483 unsigned long long unmapped;
1484 unsigned long unmap_size;
1485 u64 *pte;
1486
1487 BUG_ON(!is_power_of_2(page_size));
1488
1489 unmapped = 0;
1490
1491 while (unmapped < page_size) {
1492
1493 pte = fetch_pte(dom, bus_addr, &unmap_size);
1494
1495 if (pte) {
1496 int i, count;
1497
1498 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1499 for (i = 0; i < count; i++)
1500 pte[i] = 0ULL;
1501 }
1502
1503 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1504 unmapped += unmap_size;
1505 }
1506
1507 BUG_ON(unmapped && !is_power_of_2(unmapped));
1508
1509 return unmapped;
1510 }
1511
1512 /*
1513 * This function checks if a specific unity mapping entry is needed for
1514 * this specific IOMMU.
1515 */
1516 static int iommu_for_unity_map(struct amd_iommu *iommu,
1517 struct unity_map_entry *entry)
1518 {
1519 u16 bdf, i;
1520
1521 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1522 bdf = amd_iommu_alias_table[i];
1523 if (amd_iommu_rlookup_table[bdf] == iommu)
1524 return 1;
1525 }
1526
1527 return 0;
1528 }
1529
1530 /*
1531 * This function actually applies the mapping to the page table of the
1532 * dma_ops domain.
1533 */
1534 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1535 struct unity_map_entry *e)
1536 {
1537 u64 addr;
1538 int ret;
1539
1540 for (addr = e->address_start; addr < e->address_end;
1541 addr += PAGE_SIZE) {
1542 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1543 PAGE_SIZE);
1544 if (ret)
1545 return ret;
1546 /*
1547 * if unity mapping is in aperture range mark the page
1548 * as allocated in the aperture
1549 */
1550 if (addr < dma_dom->aperture_size)
1551 __set_bit(addr >> PAGE_SHIFT,
1552 dma_dom->aperture[0]->bitmap);
1553 }
1554
1555 return 0;
1556 }
1557
1558 /*
1559 * Init the unity mappings for a specific IOMMU in the system
1560 *
1561 * Basically iterates over all unity mapping entries and applies them to
1562 * the default domain DMA of that IOMMU if necessary.
1563 */
1564 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1565 {
1566 struct unity_map_entry *entry;
1567 int ret;
1568
1569 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1570 if (!iommu_for_unity_map(iommu, entry))
1571 continue;
1572 ret = dma_ops_unity_map(iommu->default_dom, entry);
1573 if (ret)
1574 return ret;
1575 }
1576
1577 return 0;
1578 }
1579
1580 /*
1581 * Inits the unity mappings required for a specific device
1582 */
1583 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1584 u16 devid)
1585 {
1586 struct unity_map_entry *e;
1587 int ret;
1588
1589 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1590 if (!(devid >= e->devid_start && devid <= e->devid_end))
1591 continue;
1592 ret = dma_ops_unity_map(dma_dom, e);
1593 if (ret)
1594 return ret;
1595 }
1596
1597 return 0;
1598 }
1599
1600 /****************************************************************************
1601 *
1602 * The next functions belong to the address allocator for the dma_ops
1603 * interface functions. They work like the allocators in the other IOMMU
1604 * drivers. Its basically a bitmap which marks the allocated pages in
1605 * the aperture. Maybe it could be enhanced in the future to a more
1606 * efficient allocator.
1607 *
1608 ****************************************************************************/
1609
1610 /*
1611 * The address allocator core functions.
1612 *
1613 * called with domain->lock held
1614 */
1615
1616 /*
1617 * Used to reserve address ranges in the aperture (e.g. for exclusion
1618 * ranges.
1619 */
1620 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1621 unsigned long start_page,
1622 unsigned int pages)
1623 {
1624 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1625
1626 if (start_page + pages > last_page)
1627 pages = last_page - start_page;
1628
1629 for (i = start_page; i < start_page + pages; ++i) {
1630 int index = i / APERTURE_RANGE_PAGES;
1631 int page = i % APERTURE_RANGE_PAGES;
1632 __set_bit(page, dom->aperture[index]->bitmap);
1633 }
1634 }
1635
1636 /*
1637 * This function is used to add a new aperture range to an existing
1638 * aperture in case of dma_ops domain allocation or address allocation
1639 * failure.
1640 */
1641 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1642 bool populate, gfp_t gfp)
1643 {
1644 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1645 struct amd_iommu *iommu;
1646 unsigned long i, old_size, pte_pgsize;
1647
1648 #ifdef CONFIG_IOMMU_STRESS
1649 populate = false;
1650 #endif
1651
1652 if (index >= APERTURE_MAX_RANGES)
1653 return -ENOMEM;
1654
1655 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1656 if (!dma_dom->aperture[index])
1657 return -ENOMEM;
1658
1659 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1660 if (!dma_dom->aperture[index]->bitmap)
1661 goto out_free;
1662
1663 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1664
1665 if (populate) {
1666 unsigned long address = dma_dom->aperture_size;
1667 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1668 u64 *pte, *pte_page;
1669
1670 for (i = 0; i < num_ptes; ++i) {
1671 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1672 &pte_page, gfp);
1673 if (!pte)
1674 goto out_free;
1675
1676 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1677
1678 address += APERTURE_RANGE_SIZE / 64;
1679 }
1680 }
1681
1682 old_size = dma_dom->aperture_size;
1683 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1684
1685 /* Reserve address range used for MSI messages */
1686 if (old_size < MSI_ADDR_BASE_LO &&
1687 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1688 unsigned long spage;
1689 int pages;
1690
1691 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1692 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1693
1694 dma_ops_reserve_addresses(dma_dom, spage, pages);
1695 }
1696
1697 /* Initialize the exclusion range if necessary */
1698 for_each_iommu(iommu) {
1699 if (iommu->exclusion_start &&
1700 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1701 && iommu->exclusion_start < dma_dom->aperture_size) {
1702 unsigned long startpage;
1703 int pages = iommu_num_pages(iommu->exclusion_start,
1704 iommu->exclusion_length,
1705 PAGE_SIZE);
1706 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1707 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1708 }
1709 }
1710
1711 /*
1712 * Check for areas already mapped as present in the new aperture
1713 * range and mark those pages as reserved in the allocator. Such
1714 * mappings may already exist as a result of requested unity
1715 * mappings for devices.
1716 */
1717 for (i = dma_dom->aperture[index]->offset;
1718 i < dma_dom->aperture_size;
1719 i += pte_pgsize) {
1720 u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize);
1721 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1722 continue;
1723
1724 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT,
1725 pte_pgsize >> 12);
1726 }
1727
1728 update_domain(&dma_dom->domain);
1729
1730 return 0;
1731
1732 out_free:
1733 update_domain(&dma_dom->domain);
1734
1735 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1736
1737 kfree(dma_dom->aperture[index]);
1738 dma_dom->aperture[index] = NULL;
1739
1740 return -ENOMEM;
1741 }
1742
1743 static unsigned long dma_ops_area_alloc(struct device *dev,
1744 struct dma_ops_domain *dom,
1745 unsigned int pages,
1746 unsigned long align_mask,
1747 u64 dma_mask,
1748 unsigned long start)
1749 {
1750 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1751 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1752 int i = start >> APERTURE_RANGE_SHIFT;
1753 unsigned long boundary_size, mask;
1754 unsigned long address = -1;
1755 unsigned long limit;
1756
1757 next_bit >>= PAGE_SHIFT;
1758
1759 mask = dma_get_seg_boundary(dev);
1760
1761 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
1762 1UL << (BITS_PER_LONG - PAGE_SHIFT);
1763
1764 for (;i < max_index; ++i) {
1765 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1766
1767 if (dom->aperture[i]->offset >= dma_mask)
1768 break;
1769
1770 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1771 dma_mask >> PAGE_SHIFT);
1772
1773 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1774 limit, next_bit, pages, 0,
1775 boundary_size, align_mask);
1776 if (address != -1) {
1777 address = dom->aperture[i]->offset +
1778 (address << PAGE_SHIFT);
1779 dom->next_address = address + (pages << PAGE_SHIFT);
1780 break;
1781 }
1782
1783 next_bit = 0;
1784 }
1785
1786 return address;
1787 }
1788
1789 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1790 struct dma_ops_domain *dom,
1791 unsigned int pages,
1792 unsigned long align_mask,
1793 u64 dma_mask)
1794 {
1795 unsigned long address;
1796
1797 #ifdef CONFIG_IOMMU_STRESS
1798 dom->next_address = 0;
1799 dom->need_flush = true;
1800 #endif
1801
1802 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1803 dma_mask, dom->next_address);
1804
1805 if (address == -1) {
1806 dom->next_address = 0;
1807 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1808 dma_mask, 0);
1809 dom->need_flush = true;
1810 }
1811
1812 if (unlikely(address == -1))
1813 address = DMA_ERROR_CODE;
1814
1815 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1816
1817 return address;
1818 }
1819
1820 /*
1821 * The address free function.
1822 *
1823 * called with domain->lock held
1824 */
1825 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1826 unsigned long address,
1827 unsigned int pages)
1828 {
1829 unsigned i = address >> APERTURE_RANGE_SHIFT;
1830 struct aperture_range *range = dom->aperture[i];
1831
1832 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1833
1834 #ifdef CONFIG_IOMMU_STRESS
1835 if (i < 4)
1836 return;
1837 #endif
1838
1839 if (address >= dom->next_address)
1840 dom->need_flush = true;
1841
1842 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1843
1844 bitmap_clear(range->bitmap, address, pages);
1845
1846 }
1847
1848 /****************************************************************************
1849 *
1850 * The next functions belong to the domain allocation. A domain is
1851 * allocated for every IOMMU as the default domain. If device isolation
1852 * is enabled, every device get its own domain. The most important thing
1853 * about domains is the page table mapping the DMA address space they
1854 * contain.
1855 *
1856 ****************************************************************************/
1857
1858 /*
1859 * This function adds a protection domain to the global protection domain list
1860 */
1861 static void add_domain_to_list(struct protection_domain *domain)
1862 {
1863 unsigned long flags;
1864
1865 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1866 list_add(&domain->list, &amd_iommu_pd_list);
1867 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1868 }
1869
1870 /*
1871 * This function removes a protection domain to the global
1872 * protection domain list
1873 */
1874 static void del_domain_from_list(struct protection_domain *domain)
1875 {
1876 unsigned long flags;
1877
1878 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1879 list_del(&domain->list);
1880 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1881 }
1882
1883 static u16 domain_id_alloc(void)
1884 {
1885 unsigned long flags;
1886 int id;
1887
1888 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1889 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1890 BUG_ON(id == 0);
1891 if (id > 0 && id < MAX_DOMAIN_ID)
1892 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1893 else
1894 id = 0;
1895 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1896
1897 return id;
1898 }
1899
1900 static void domain_id_free(int id)
1901 {
1902 unsigned long flags;
1903
1904 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1905 if (id > 0 && id < MAX_DOMAIN_ID)
1906 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1907 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1908 }
1909
1910 #define DEFINE_FREE_PT_FN(LVL, FN) \
1911 static void free_pt_##LVL (unsigned long __pt) \
1912 { \
1913 unsigned long p; \
1914 u64 *pt; \
1915 int i; \
1916 \
1917 pt = (u64 *)__pt; \
1918 \
1919 for (i = 0; i < 512; ++i) { \
1920 /* PTE present? */ \
1921 if (!IOMMU_PTE_PRESENT(pt[i])) \
1922 continue; \
1923 \
1924 /* Large PTE? */ \
1925 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1926 PM_PTE_LEVEL(pt[i]) == 7) \
1927 continue; \
1928 \
1929 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1930 FN(p); \
1931 } \
1932 free_page((unsigned long)pt); \
1933 }
1934
1935 DEFINE_FREE_PT_FN(l2, free_page)
1936 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1937 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1938 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1939 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1940
1941 static void free_pagetable(struct protection_domain *domain)
1942 {
1943 unsigned long root = (unsigned long)domain->pt_root;
1944
1945 switch (domain->mode) {
1946 case PAGE_MODE_NONE:
1947 break;
1948 case PAGE_MODE_1_LEVEL:
1949 free_page(root);
1950 break;
1951 case PAGE_MODE_2_LEVEL:
1952 free_pt_l2(root);
1953 break;
1954 case PAGE_MODE_3_LEVEL:
1955 free_pt_l3(root);
1956 break;
1957 case PAGE_MODE_4_LEVEL:
1958 free_pt_l4(root);
1959 break;
1960 case PAGE_MODE_5_LEVEL:
1961 free_pt_l5(root);
1962 break;
1963 case PAGE_MODE_6_LEVEL:
1964 free_pt_l6(root);
1965 break;
1966 default:
1967 BUG();
1968 }
1969 }
1970
1971 static void free_gcr3_tbl_level1(u64 *tbl)
1972 {
1973 u64 *ptr;
1974 int i;
1975
1976 for (i = 0; i < 512; ++i) {
1977 if (!(tbl[i] & GCR3_VALID))
1978 continue;
1979
1980 ptr = __va(tbl[i] & PAGE_MASK);
1981
1982 free_page((unsigned long)ptr);
1983 }
1984 }
1985
1986 static void free_gcr3_tbl_level2(u64 *tbl)
1987 {
1988 u64 *ptr;
1989 int i;
1990
1991 for (i = 0; i < 512; ++i) {
1992 if (!(tbl[i] & GCR3_VALID))
1993 continue;
1994
1995 ptr = __va(tbl[i] & PAGE_MASK);
1996
1997 free_gcr3_tbl_level1(ptr);
1998 }
1999 }
2000
2001 static void free_gcr3_table(struct protection_domain *domain)
2002 {
2003 if (domain->glx == 2)
2004 free_gcr3_tbl_level2(domain->gcr3_tbl);
2005 else if (domain->glx == 1)
2006 free_gcr3_tbl_level1(domain->gcr3_tbl);
2007 else if (domain->glx != 0)
2008 BUG();
2009
2010 free_page((unsigned long)domain->gcr3_tbl);
2011 }
2012
2013 /*
2014 * Free a domain, only used if something went wrong in the
2015 * allocation path and we need to free an already allocated page table
2016 */
2017 static void dma_ops_domain_free(struct dma_ops_domain *dom)
2018 {
2019 int i;
2020
2021 if (!dom)
2022 return;
2023
2024 del_domain_from_list(&dom->domain);
2025
2026 free_pagetable(&dom->domain);
2027
2028 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
2029 if (!dom->aperture[i])
2030 continue;
2031 free_page((unsigned long)dom->aperture[i]->bitmap);
2032 kfree(dom->aperture[i]);
2033 }
2034
2035 kfree(dom);
2036 }
2037
2038 /*
2039 * Allocates a new protection domain usable for the dma_ops functions.
2040 * It also initializes the page table and the address allocator data
2041 * structures required for the dma_ops interface
2042 */
2043 static struct dma_ops_domain *dma_ops_domain_alloc(void)
2044 {
2045 struct dma_ops_domain *dma_dom;
2046
2047 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
2048 if (!dma_dom)
2049 return NULL;
2050
2051 spin_lock_init(&dma_dom->domain.lock);
2052
2053 dma_dom->domain.id = domain_id_alloc();
2054 if (dma_dom->domain.id == 0)
2055 goto free_dma_dom;
2056 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
2057 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
2058 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2059 dma_dom->domain.flags = PD_DMA_OPS_MASK;
2060 dma_dom->domain.priv = dma_dom;
2061 if (!dma_dom->domain.pt_root)
2062 goto free_dma_dom;
2063
2064 dma_dom->need_flush = false;
2065 dma_dom->target_dev = 0xffff;
2066
2067 add_domain_to_list(&dma_dom->domain);
2068
2069 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
2070 goto free_dma_dom;
2071
2072 /*
2073 * mark the first page as allocated so we never return 0 as
2074 * a valid dma-address. So we can use 0 as error value
2075 */
2076 dma_dom->aperture[0]->bitmap[0] = 1;
2077 dma_dom->next_address = 0;
2078
2079
2080 return dma_dom;
2081
2082 free_dma_dom:
2083 dma_ops_domain_free(dma_dom);
2084
2085 return NULL;
2086 }
2087
2088 /*
2089 * little helper function to check whether a given protection domain is a
2090 * dma_ops domain
2091 */
2092 static bool dma_ops_domain(struct protection_domain *domain)
2093 {
2094 return domain->flags & PD_DMA_OPS_MASK;
2095 }
2096
2097 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
2098 {
2099 u64 pte_root = 0;
2100 u64 flags = 0;
2101
2102 if (domain->mode != PAGE_MODE_NONE)
2103 pte_root = virt_to_phys(domain->pt_root);
2104
2105 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2106 << DEV_ENTRY_MODE_SHIFT;
2107 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
2108
2109 flags = amd_iommu_dev_table[devid].data[1];
2110
2111 if (ats)
2112 flags |= DTE_FLAG_IOTLB;
2113
2114 if (domain->flags & PD_IOMMUV2_MASK) {
2115 u64 gcr3 = __pa(domain->gcr3_tbl);
2116 u64 glx = domain->glx;
2117 u64 tmp;
2118
2119 pte_root |= DTE_FLAG_GV;
2120 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2121
2122 /* First mask out possible old values for GCR3 table */
2123 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2124 flags &= ~tmp;
2125
2126 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2127 flags &= ~tmp;
2128
2129 /* Encode GCR3 table into DTE */
2130 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2131 pte_root |= tmp;
2132
2133 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2134 flags |= tmp;
2135
2136 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2137 flags |= tmp;
2138 }
2139
2140 flags &= ~(0xffffUL);
2141 flags |= domain->id;
2142
2143 amd_iommu_dev_table[devid].data[1] = flags;
2144 amd_iommu_dev_table[devid].data[0] = pte_root;
2145 }
2146
2147 static void clear_dte_entry(u16 devid)
2148 {
2149 /* remove entry from the device table seen by the hardware */
2150 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2151 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
2152
2153 amd_iommu_apply_erratum_63(devid);
2154 }
2155
2156 static void do_attach(struct iommu_dev_data *dev_data,
2157 struct protection_domain *domain)
2158 {
2159 struct amd_iommu *iommu;
2160 bool ats;
2161
2162 iommu = amd_iommu_rlookup_table[dev_data->devid];
2163 ats = dev_data->ats.enabled;
2164
2165 /* Update data structures */
2166 dev_data->domain = domain;
2167 list_add(&dev_data->list, &domain->dev_list);
2168 set_dte_entry(dev_data->devid, domain, ats);
2169
2170 /* Do reference counting */
2171 domain->dev_iommu[iommu->index] += 1;
2172 domain->dev_cnt += 1;
2173
2174 /* Flush the DTE entry */
2175 device_flush_dte(dev_data);
2176 }
2177
2178 static void do_detach(struct iommu_dev_data *dev_data)
2179 {
2180 struct amd_iommu *iommu;
2181
2182 iommu = amd_iommu_rlookup_table[dev_data->devid];
2183
2184 /* decrease reference counters */
2185 dev_data->domain->dev_iommu[iommu->index] -= 1;
2186 dev_data->domain->dev_cnt -= 1;
2187
2188 /* Update data structures */
2189 dev_data->domain = NULL;
2190 list_del(&dev_data->list);
2191 clear_dte_entry(dev_data->devid);
2192
2193 /* Flush the DTE entry */
2194 device_flush_dte(dev_data);
2195 }
2196
2197 /*
2198 * If a device is not yet associated with a domain, this function does
2199 * assigns it visible for the hardware
2200 */
2201 static int __attach_device(struct iommu_dev_data *dev_data,
2202 struct protection_domain *domain)
2203 {
2204 int ret;
2205
2206 /* lock domain */
2207 spin_lock(&domain->lock);
2208
2209 if (dev_data->alias_data != NULL) {
2210 struct iommu_dev_data *alias_data = dev_data->alias_data;
2211
2212 /* Some sanity checks */
2213 ret = -EBUSY;
2214 if (alias_data->domain != NULL &&
2215 alias_data->domain != domain)
2216 goto out_unlock;
2217
2218 if (dev_data->domain != NULL &&
2219 dev_data->domain != domain)
2220 goto out_unlock;
2221
2222 /* Do real assignment */
2223 if (alias_data->domain == NULL)
2224 do_attach(alias_data, domain);
2225
2226 atomic_inc(&alias_data->bind);
2227 }
2228
2229 if (dev_data->domain == NULL)
2230 do_attach(dev_data, domain);
2231
2232 atomic_inc(&dev_data->bind);
2233
2234 ret = 0;
2235
2236 out_unlock:
2237
2238 /* ready */
2239 spin_unlock(&domain->lock);
2240
2241 return ret;
2242 }
2243
2244
2245 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2246 {
2247 pci_disable_ats(pdev);
2248 pci_disable_pri(pdev);
2249 pci_disable_pasid(pdev);
2250 }
2251
2252 /* FIXME: Change generic reset-function to do the same */
2253 static int pri_reset_while_enabled(struct pci_dev *pdev)
2254 {
2255 u16 control;
2256 int pos;
2257
2258 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2259 if (!pos)
2260 return -EINVAL;
2261
2262 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2263 control |= PCI_PRI_CTRL_RESET;
2264 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2265
2266 return 0;
2267 }
2268
2269 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2270 {
2271 bool reset_enable;
2272 int reqs, ret;
2273
2274 /* FIXME: Hardcode number of outstanding requests for now */
2275 reqs = 32;
2276 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2277 reqs = 1;
2278 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2279
2280 /* Only allow access to user-accessible pages */
2281 ret = pci_enable_pasid(pdev, 0);
2282 if (ret)
2283 goto out_err;
2284
2285 /* First reset the PRI state of the device */
2286 ret = pci_reset_pri(pdev);
2287 if (ret)
2288 goto out_err;
2289
2290 /* Enable PRI */
2291 ret = pci_enable_pri(pdev, reqs);
2292 if (ret)
2293 goto out_err;
2294
2295 if (reset_enable) {
2296 ret = pri_reset_while_enabled(pdev);
2297 if (ret)
2298 goto out_err;
2299 }
2300
2301 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2302 if (ret)
2303 goto out_err;
2304
2305 return 0;
2306
2307 out_err:
2308 pci_disable_pri(pdev);
2309 pci_disable_pasid(pdev);
2310
2311 return ret;
2312 }
2313
2314 /* FIXME: Move this to PCI code */
2315 #define PCI_PRI_TLP_OFF (1 << 15)
2316
2317 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2318 {
2319 u16 status;
2320 int pos;
2321
2322 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2323 if (!pos)
2324 return false;
2325
2326 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2327
2328 return (status & PCI_PRI_TLP_OFF) ? true : false;
2329 }
2330
2331 /*
2332 * If a device is not yet associated with a domain, this function
2333 * assigns it visible for the hardware
2334 */
2335 static int attach_device(struct device *dev,
2336 struct protection_domain *domain)
2337 {
2338 struct pci_dev *pdev = to_pci_dev(dev);
2339 struct iommu_dev_data *dev_data;
2340 unsigned long flags;
2341 int ret;
2342
2343 dev_data = get_dev_data(dev);
2344
2345 if (domain->flags & PD_IOMMUV2_MASK) {
2346 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2347 return -EINVAL;
2348
2349 if (pdev_iommuv2_enable(pdev) != 0)
2350 return -EINVAL;
2351
2352 dev_data->ats.enabled = true;
2353 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2354 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2355 } else if (amd_iommu_iotlb_sup &&
2356 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2357 dev_data->ats.enabled = true;
2358 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2359 }
2360
2361 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2362 ret = __attach_device(dev_data, domain);
2363 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2364
2365 /*
2366 * We might boot into a crash-kernel here. The crashed kernel
2367 * left the caches in the IOMMU dirty. So we have to flush
2368 * here to evict all dirty stuff.
2369 */
2370 domain_flush_tlb_pde(domain);
2371
2372 return ret;
2373 }
2374
2375 /*
2376 * Removes a device from a protection domain (unlocked)
2377 */
2378 static void __detach_device(struct iommu_dev_data *dev_data)
2379 {
2380 struct protection_domain *domain;
2381 unsigned long flags;
2382
2383 BUG_ON(!dev_data->domain);
2384
2385 domain = dev_data->domain;
2386
2387 spin_lock_irqsave(&domain->lock, flags);
2388
2389 if (dev_data->alias_data != NULL) {
2390 struct iommu_dev_data *alias_data = dev_data->alias_data;
2391
2392 if (atomic_dec_and_test(&alias_data->bind))
2393 do_detach(alias_data);
2394 }
2395
2396 if (atomic_dec_and_test(&dev_data->bind))
2397 do_detach(dev_data);
2398
2399 spin_unlock_irqrestore(&domain->lock, flags);
2400
2401 /*
2402 * If we run in passthrough mode the device must be assigned to the
2403 * passthrough domain if it is detached from any other domain.
2404 * Make sure we can deassign from the pt_domain itself.
2405 */
2406 if (dev_data->passthrough &&
2407 (dev_data->domain == NULL && domain != pt_domain))
2408 __attach_device(dev_data, pt_domain);
2409 }
2410
2411 /*
2412 * Removes a device from a protection domain (with devtable_lock held)
2413 */
2414 static void detach_device(struct device *dev)
2415 {
2416 struct protection_domain *domain;
2417 struct iommu_dev_data *dev_data;
2418 unsigned long flags;
2419
2420 dev_data = get_dev_data(dev);
2421 domain = dev_data->domain;
2422
2423 /* lock device table */
2424 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2425 __detach_device(dev_data);
2426 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2427
2428 if (domain->flags & PD_IOMMUV2_MASK)
2429 pdev_iommuv2_disable(to_pci_dev(dev));
2430 else if (dev_data->ats.enabled)
2431 pci_disable_ats(to_pci_dev(dev));
2432
2433 dev_data->ats.enabled = false;
2434 }
2435
2436 /*
2437 * Find out the protection domain structure for a given PCI device. This
2438 * will give us the pointer to the page table root for example.
2439 */
2440 static struct protection_domain *domain_for_device(struct device *dev)
2441 {
2442 struct iommu_dev_data *dev_data;
2443 struct protection_domain *dom = NULL;
2444 unsigned long flags;
2445
2446 dev_data = get_dev_data(dev);
2447
2448 if (dev_data->domain)
2449 return dev_data->domain;
2450
2451 if (dev_data->alias_data != NULL) {
2452 struct iommu_dev_data *alias_data = dev_data->alias_data;
2453
2454 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2455 if (alias_data->domain != NULL) {
2456 __attach_device(dev_data, alias_data->domain);
2457 dom = alias_data->domain;
2458 }
2459 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2460 }
2461
2462 return dom;
2463 }
2464
2465 static int device_change_notifier(struct notifier_block *nb,
2466 unsigned long action, void *data)
2467 {
2468 struct dma_ops_domain *dma_domain;
2469 struct protection_domain *domain;
2470 struct iommu_dev_data *dev_data;
2471 struct device *dev = data;
2472 struct amd_iommu *iommu;
2473 unsigned long flags;
2474 u16 devid;
2475
2476 if (!check_device(dev))
2477 return 0;
2478
2479 devid = get_device_id(dev);
2480 iommu = amd_iommu_rlookup_table[devid];
2481 dev_data = get_dev_data(dev);
2482
2483 switch (action) {
2484 case BUS_NOTIFY_UNBOUND_DRIVER:
2485
2486 domain = domain_for_device(dev);
2487
2488 if (!domain)
2489 goto out;
2490 if (dev_data->passthrough)
2491 break;
2492 detach_device(dev);
2493 break;
2494 case BUS_NOTIFY_ADD_DEVICE:
2495
2496 iommu_init_device(dev);
2497
2498 /*
2499 * dev_data is still NULL and
2500 * got initialized in iommu_init_device
2501 */
2502 dev_data = get_dev_data(dev);
2503
2504 if (iommu_pass_through || dev_data->iommu_v2) {
2505 dev_data->passthrough = true;
2506 attach_device(dev, pt_domain);
2507 break;
2508 }
2509
2510 domain = domain_for_device(dev);
2511
2512 /* allocate a protection domain if a device is added */
2513 dma_domain = find_protection_domain(devid);
2514 if (!dma_domain) {
2515 dma_domain = dma_ops_domain_alloc();
2516 if (!dma_domain)
2517 goto out;
2518 dma_domain->target_dev = devid;
2519
2520 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2521 list_add_tail(&dma_domain->list, &iommu_pd_list);
2522 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2523 }
2524
2525 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2526
2527 break;
2528 case BUS_NOTIFY_DEL_DEVICE:
2529
2530 iommu_uninit_device(dev);
2531
2532 default:
2533 goto out;
2534 }
2535
2536 iommu_completion_wait(iommu);
2537
2538 out:
2539 return 0;
2540 }
2541
2542 static struct notifier_block device_nb = {
2543 .notifier_call = device_change_notifier,
2544 };
2545
2546 void amd_iommu_init_notifier(void)
2547 {
2548 bus_register_notifier(&pci_bus_type, &device_nb);
2549 }
2550
2551 /*****************************************************************************
2552 *
2553 * The next functions belong to the dma_ops mapping/unmapping code.
2554 *
2555 *****************************************************************************/
2556
2557 /*
2558 * In the dma_ops path we only have the struct device. This function
2559 * finds the corresponding IOMMU, the protection domain and the
2560 * requestor id for a given device.
2561 * If the device is not yet associated with a domain this is also done
2562 * in this function.
2563 */
2564 static struct protection_domain *get_domain(struct device *dev)
2565 {
2566 struct protection_domain *domain;
2567 struct dma_ops_domain *dma_dom;
2568 u16 devid = get_device_id(dev);
2569
2570 if (!check_device(dev))
2571 return ERR_PTR(-EINVAL);
2572
2573 domain = domain_for_device(dev);
2574 if (domain != NULL && !dma_ops_domain(domain))
2575 return ERR_PTR(-EBUSY);
2576
2577 if (domain != NULL)
2578 return domain;
2579
2580 /* Device not bound yet - bind it */
2581 dma_dom = find_protection_domain(devid);
2582 if (!dma_dom)
2583 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2584 attach_device(dev, &dma_dom->domain);
2585 DUMP_printk("Using protection domain %d for device %s\n",
2586 dma_dom->domain.id, dev_name(dev));
2587
2588 return &dma_dom->domain;
2589 }
2590
2591 static void update_device_table(struct protection_domain *domain)
2592 {
2593 struct iommu_dev_data *dev_data;
2594
2595 list_for_each_entry(dev_data, &domain->dev_list, list) {
2596 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2597
2598 if (dev_data->alias_data == NULL)
2599 continue;
2600
2601 /* There is an alias, update device table entry for it */
2602 set_dte_entry(dev_data->alias_data->devid, domain,
2603 dev_data->alias_data->ats.enabled);
2604 }
2605 }
2606
2607 static void update_domain(struct protection_domain *domain)
2608 {
2609 if (!domain->updated)
2610 return;
2611
2612 update_device_table(domain);
2613
2614 domain_flush_devices(domain);
2615 domain_flush_tlb_pde(domain);
2616
2617 domain->updated = false;
2618 }
2619
2620 /*
2621 * This function fetches the PTE for a given address in the aperture
2622 */
2623 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2624 unsigned long address)
2625 {
2626 struct aperture_range *aperture;
2627 u64 *pte, *pte_page;
2628
2629 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2630 if (!aperture)
2631 return NULL;
2632
2633 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2634 if (!pte) {
2635 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2636 GFP_ATOMIC);
2637 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2638 } else
2639 pte += PM_LEVEL_INDEX(0, address);
2640
2641 update_domain(&dom->domain);
2642
2643 return pte;
2644 }
2645
2646 /*
2647 * This is the generic map function. It maps one 4kb page at paddr to
2648 * the given address in the DMA address space for the domain.
2649 */
2650 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2651 unsigned long address,
2652 phys_addr_t paddr,
2653 int direction)
2654 {
2655 u64 *pte, __pte;
2656
2657 WARN_ON(address > dom->aperture_size);
2658
2659 paddr &= PAGE_MASK;
2660
2661 pte = dma_ops_get_pte(dom, address);
2662 if (!pte)
2663 return DMA_ERROR_CODE;
2664
2665 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2666
2667 if (direction == DMA_TO_DEVICE)
2668 __pte |= IOMMU_PTE_IR;
2669 else if (direction == DMA_FROM_DEVICE)
2670 __pte |= IOMMU_PTE_IW;
2671 else if (direction == DMA_BIDIRECTIONAL)
2672 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2673
2674 WARN_ON(*pte);
2675
2676 *pte = __pte;
2677
2678 return (dma_addr_t)address;
2679 }
2680
2681 /*
2682 * The generic unmapping function for on page in the DMA address space.
2683 */
2684 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2685 unsigned long address)
2686 {
2687 struct aperture_range *aperture;
2688 u64 *pte;
2689
2690 if (address >= dom->aperture_size)
2691 return;
2692
2693 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2694 if (!aperture)
2695 return;
2696
2697 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2698 if (!pte)
2699 return;
2700
2701 pte += PM_LEVEL_INDEX(0, address);
2702
2703 WARN_ON(!*pte);
2704
2705 *pte = 0ULL;
2706 }
2707
2708 /*
2709 * This function contains common code for mapping of a physically
2710 * contiguous memory region into DMA address space. It is used by all
2711 * mapping functions provided with this IOMMU driver.
2712 * Must be called with the domain lock held.
2713 */
2714 static dma_addr_t __map_single(struct device *dev,
2715 struct dma_ops_domain *dma_dom,
2716 phys_addr_t paddr,
2717 size_t size,
2718 int dir,
2719 bool align,
2720 u64 dma_mask)
2721 {
2722 dma_addr_t offset = paddr & ~PAGE_MASK;
2723 dma_addr_t address, start, ret;
2724 unsigned int pages;
2725 unsigned long align_mask = 0;
2726 int i;
2727
2728 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2729 paddr &= PAGE_MASK;
2730
2731 INC_STATS_COUNTER(total_map_requests);
2732
2733 if (pages > 1)
2734 INC_STATS_COUNTER(cross_page);
2735
2736 if (align)
2737 align_mask = (1UL << get_order(size)) - 1;
2738
2739 retry:
2740 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2741 dma_mask);
2742 if (unlikely(address == DMA_ERROR_CODE)) {
2743 /*
2744 * setting next_address here will let the address
2745 * allocator only scan the new allocated range in the
2746 * first run. This is a small optimization.
2747 */
2748 dma_dom->next_address = dma_dom->aperture_size;
2749
2750 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2751 goto out;
2752
2753 /*
2754 * aperture was successfully enlarged by 128 MB, try
2755 * allocation again
2756 */
2757 goto retry;
2758 }
2759
2760 start = address;
2761 for (i = 0; i < pages; ++i) {
2762 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2763 if (ret == DMA_ERROR_CODE)
2764 goto out_unmap;
2765
2766 paddr += PAGE_SIZE;
2767 start += PAGE_SIZE;
2768 }
2769 address += offset;
2770
2771 ADD_STATS_COUNTER(alloced_io_mem, size);
2772
2773 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2774 domain_flush_tlb(&dma_dom->domain);
2775 dma_dom->need_flush = false;
2776 } else if (unlikely(amd_iommu_np_cache))
2777 domain_flush_pages(&dma_dom->domain, address, size);
2778
2779 out:
2780 return address;
2781
2782 out_unmap:
2783
2784 for (--i; i >= 0; --i) {
2785 start -= PAGE_SIZE;
2786 dma_ops_domain_unmap(dma_dom, start);
2787 }
2788
2789 dma_ops_free_addresses(dma_dom, address, pages);
2790
2791 return DMA_ERROR_CODE;
2792 }
2793
2794 /*
2795 * Does the reverse of the __map_single function. Must be called with
2796 * the domain lock held too
2797 */
2798 static void __unmap_single(struct dma_ops_domain *dma_dom,
2799 dma_addr_t dma_addr,
2800 size_t size,
2801 int dir)
2802 {
2803 dma_addr_t flush_addr;
2804 dma_addr_t i, start;
2805 unsigned int pages;
2806
2807 if ((dma_addr == DMA_ERROR_CODE) ||
2808 (dma_addr + size > dma_dom->aperture_size))
2809 return;
2810
2811 flush_addr = dma_addr;
2812 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2813 dma_addr &= PAGE_MASK;
2814 start = dma_addr;
2815
2816 for (i = 0; i < pages; ++i) {
2817 dma_ops_domain_unmap(dma_dom, start);
2818 start += PAGE_SIZE;
2819 }
2820
2821 SUB_STATS_COUNTER(alloced_io_mem, size);
2822
2823 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2824
2825 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2826 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2827 dma_dom->need_flush = false;
2828 }
2829 }
2830
2831 /*
2832 * The exported map_single function for dma_ops.
2833 */
2834 static dma_addr_t map_page(struct device *dev, struct page *page,
2835 unsigned long offset, size_t size,
2836 enum dma_data_direction dir,
2837 struct dma_attrs *attrs)
2838 {
2839 unsigned long flags;
2840 struct protection_domain *domain;
2841 dma_addr_t addr;
2842 u64 dma_mask;
2843 phys_addr_t paddr = page_to_phys(page) + offset;
2844
2845 INC_STATS_COUNTER(cnt_map_single);
2846
2847 domain = get_domain(dev);
2848 if (PTR_ERR(domain) == -EINVAL)
2849 return (dma_addr_t)paddr;
2850 else if (IS_ERR(domain))
2851 return DMA_ERROR_CODE;
2852
2853 dma_mask = *dev->dma_mask;
2854
2855 spin_lock_irqsave(&domain->lock, flags);
2856
2857 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2858 dma_mask);
2859 if (addr == DMA_ERROR_CODE)
2860 goto out;
2861
2862 domain_flush_complete(domain);
2863
2864 out:
2865 spin_unlock_irqrestore(&domain->lock, flags);
2866
2867 return addr;
2868 }
2869
2870 /*
2871 * The exported unmap_single function for dma_ops.
2872 */
2873 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2874 enum dma_data_direction dir, struct dma_attrs *attrs)
2875 {
2876 unsigned long flags;
2877 struct protection_domain *domain;
2878
2879 INC_STATS_COUNTER(cnt_unmap_single);
2880
2881 domain = get_domain(dev);
2882 if (IS_ERR(domain))
2883 return;
2884
2885 spin_lock_irqsave(&domain->lock, flags);
2886
2887 __unmap_single(domain->priv, dma_addr, size, dir);
2888
2889 domain_flush_complete(domain);
2890
2891 spin_unlock_irqrestore(&domain->lock, flags);
2892 }
2893
2894 /*
2895 * The exported map_sg function for dma_ops (handles scatter-gather
2896 * lists).
2897 */
2898 static int map_sg(struct device *dev, struct scatterlist *sglist,
2899 int nelems, enum dma_data_direction dir,
2900 struct dma_attrs *attrs)
2901 {
2902 unsigned long flags;
2903 struct protection_domain *domain;
2904 int i;
2905 struct scatterlist *s;
2906 phys_addr_t paddr;
2907 int mapped_elems = 0;
2908 u64 dma_mask;
2909
2910 INC_STATS_COUNTER(cnt_map_sg);
2911
2912 domain = get_domain(dev);
2913 if (IS_ERR(domain))
2914 return 0;
2915
2916 dma_mask = *dev->dma_mask;
2917
2918 spin_lock_irqsave(&domain->lock, flags);
2919
2920 for_each_sg(sglist, s, nelems, i) {
2921 paddr = sg_phys(s);
2922
2923 s->dma_address = __map_single(dev, domain->priv,
2924 paddr, s->length, dir, false,
2925 dma_mask);
2926
2927 if (s->dma_address) {
2928 s->dma_length = s->length;
2929 mapped_elems++;
2930 } else
2931 goto unmap;
2932 }
2933
2934 domain_flush_complete(domain);
2935
2936 out:
2937 spin_unlock_irqrestore(&domain->lock, flags);
2938
2939 return mapped_elems;
2940 unmap:
2941 for_each_sg(sglist, s, mapped_elems, i) {
2942 if (s->dma_address)
2943 __unmap_single(domain->priv, s->dma_address,
2944 s->dma_length, dir);
2945 s->dma_address = s->dma_length = 0;
2946 }
2947
2948 mapped_elems = 0;
2949
2950 goto out;
2951 }
2952
2953 /*
2954 * The exported map_sg function for dma_ops (handles scatter-gather
2955 * lists).
2956 */
2957 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2958 int nelems, enum dma_data_direction dir,
2959 struct dma_attrs *attrs)
2960 {
2961 unsigned long flags;
2962 struct protection_domain *domain;
2963 struct scatterlist *s;
2964 int i;
2965
2966 INC_STATS_COUNTER(cnt_unmap_sg);
2967
2968 domain = get_domain(dev);
2969 if (IS_ERR(domain))
2970 return;
2971
2972 spin_lock_irqsave(&domain->lock, flags);
2973
2974 for_each_sg(sglist, s, nelems, i) {
2975 __unmap_single(domain->priv, s->dma_address,
2976 s->dma_length, dir);
2977 s->dma_address = s->dma_length = 0;
2978 }
2979
2980 domain_flush_complete(domain);
2981
2982 spin_unlock_irqrestore(&domain->lock, flags);
2983 }
2984
2985 /*
2986 * The exported alloc_coherent function for dma_ops.
2987 */
2988 static void *alloc_coherent(struct device *dev, size_t size,
2989 dma_addr_t *dma_addr, gfp_t flag,
2990 struct dma_attrs *attrs)
2991 {
2992 unsigned long flags;
2993 void *virt_addr;
2994 struct protection_domain *domain;
2995 phys_addr_t paddr;
2996 u64 dma_mask = dev->coherent_dma_mask;
2997
2998 INC_STATS_COUNTER(cnt_alloc_coherent);
2999
3000 domain = get_domain(dev);
3001 if (PTR_ERR(domain) == -EINVAL) {
3002 virt_addr = (void *)__get_free_pages(flag, get_order(size));
3003 *dma_addr = __pa(virt_addr);
3004 return virt_addr;
3005 } else if (IS_ERR(domain))
3006 return NULL;
3007
3008 dma_mask = dev->coherent_dma_mask;
3009 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
3010 flag |= __GFP_ZERO;
3011
3012 virt_addr = (void *)__get_free_pages(flag, get_order(size));
3013 if (!virt_addr)
3014 return NULL;
3015
3016 paddr = virt_to_phys(virt_addr);
3017
3018 if (!dma_mask)
3019 dma_mask = *dev->dma_mask;
3020
3021 spin_lock_irqsave(&domain->lock, flags);
3022
3023 *dma_addr = __map_single(dev, domain->priv, paddr,
3024 size, DMA_BIDIRECTIONAL, true, dma_mask);
3025
3026 if (*dma_addr == DMA_ERROR_CODE) {
3027 spin_unlock_irqrestore(&domain->lock, flags);
3028 goto out_free;
3029 }
3030
3031 domain_flush_complete(domain);
3032
3033 spin_unlock_irqrestore(&domain->lock, flags);
3034
3035 return virt_addr;
3036
3037 out_free:
3038
3039 free_pages((unsigned long)virt_addr, get_order(size));
3040
3041 return NULL;
3042 }
3043
3044 /*
3045 * The exported free_coherent function for dma_ops.
3046 */
3047 static void free_coherent(struct device *dev, size_t size,
3048 void *virt_addr, dma_addr_t dma_addr,
3049 struct dma_attrs *attrs)
3050 {
3051 unsigned long flags;
3052 struct protection_domain *domain;
3053
3054 INC_STATS_COUNTER(cnt_free_coherent);
3055
3056 domain = get_domain(dev);
3057 if (IS_ERR(domain))
3058 goto free_mem;
3059
3060 spin_lock_irqsave(&domain->lock, flags);
3061
3062 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
3063
3064 domain_flush_complete(domain);
3065
3066 spin_unlock_irqrestore(&domain->lock, flags);
3067
3068 free_mem:
3069 free_pages((unsigned long)virt_addr, get_order(size));
3070 }
3071
3072 /*
3073 * This function is called by the DMA layer to find out if we can handle a
3074 * particular device. It is part of the dma_ops.
3075 */
3076 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
3077 {
3078 return check_device(dev);
3079 }
3080
3081 /*
3082 * The function for pre-allocating protection domains.
3083 *
3084 * If the driver core informs the DMA layer if a driver grabs a device
3085 * we don't need to preallocate the protection domains anymore.
3086 * For now we have to.
3087 */
3088 static void __init prealloc_protection_domains(void)
3089 {
3090 struct iommu_dev_data *dev_data;
3091 struct dma_ops_domain *dma_dom;
3092 struct pci_dev *dev = NULL;
3093 u16 devid;
3094
3095 for_each_pci_dev(dev) {
3096
3097 /* Do we handle this device? */
3098 if (!check_device(&dev->dev))
3099 continue;
3100
3101 dev_data = get_dev_data(&dev->dev);
3102 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
3103 /* Make sure passthrough domain is allocated */
3104 alloc_passthrough_domain();
3105 dev_data->passthrough = true;
3106 attach_device(&dev->dev, pt_domain);
3107 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
3108 dev_name(&dev->dev));
3109 }
3110
3111 /* Is there already any domain for it? */
3112 if (domain_for_device(&dev->dev))
3113 continue;
3114
3115 devid = get_device_id(&dev->dev);
3116
3117 dma_dom = dma_ops_domain_alloc();
3118 if (!dma_dom)
3119 continue;
3120 init_unity_mappings_for_device(dma_dom, devid);
3121 dma_dom->target_dev = devid;
3122
3123 attach_device(&dev->dev, &dma_dom->domain);
3124
3125 list_add_tail(&dma_dom->list, &iommu_pd_list);
3126 }
3127 }
3128
3129 static struct dma_map_ops amd_iommu_dma_ops = {
3130 .alloc = alloc_coherent,
3131 .free = free_coherent,
3132 .map_page = map_page,
3133 .unmap_page = unmap_page,
3134 .map_sg = map_sg,
3135 .unmap_sg = unmap_sg,
3136 .dma_supported = amd_iommu_dma_supported,
3137 };
3138
3139 static unsigned device_dma_ops_init(void)
3140 {
3141 struct iommu_dev_data *dev_data;
3142 struct pci_dev *pdev = NULL;
3143 unsigned unhandled = 0;
3144
3145 for_each_pci_dev(pdev) {
3146 if (!check_device(&pdev->dev)) {
3147
3148 iommu_ignore_device(&pdev->dev);
3149
3150 unhandled += 1;
3151 continue;
3152 }
3153
3154 dev_data = get_dev_data(&pdev->dev);
3155
3156 if (!dev_data->passthrough)
3157 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
3158 else
3159 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
3160 }
3161
3162 return unhandled;
3163 }
3164
3165 /*
3166 * The function which clues the AMD IOMMU driver into dma_ops.
3167 */
3168
3169 void __init amd_iommu_init_api(void)
3170 {
3171 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
3172 }
3173
3174 int __init amd_iommu_init_dma_ops(void)
3175 {
3176 struct amd_iommu *iommu;
3177 int ret, unhandled;
3178
3179 /*
3180 * first allocate a default protection domain for every IOMMU we
3181 * found in the system. Devices not assigned to any other
3182 * protection domain will be assigned to the default one.
3183 */
3184 for_each_iommu(iommu) {
3185 iommu->default_dom = dma_ops_domain_alloc();
3186 if (iommu->default_dom == NULL)
3187 return -ENOMEM;
3188 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
3189 ret = iommu_init_unity_mappings(iommu);
3190 if (ret)
3191 goto free_domains;
3192 }
3193
3194 /*
3195 * Pre-allocate the protection domains for each device.
3196 */
3197 prealloc_protection_domains();
3198
3199 iommu_detected = 1;
3200 swiotlb = 0;
3201
3202 /* Make the driver finally visible to the drivers */
3203 unhandled = device_dma_ops_init();
3204 if (unhandled && max_pfn > MAX_DMA32_PFN) {
3205 /* There are unhandled devices - initialize swiotlb for them */
3206 swiotlb = 1;
3207 }
3208
3209 amd_iommu_stats_init();
3210
3211 if (amd_iommu_unmap_flush)
3212 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3213 else
3214 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3215
3216 return 0;
3217
3218 free_domains:
3219
3220 for_each_iommu(iommu) {
3221 dma_ops_domain_free(iommu->default_dom);
3222 }
3223
3224 return ret;
3225 }
3226
3227 /*****************************************************************************
3228 *
3229 * The following functions belong to the exported interface of AMD IOMMU
3230 *
3231 * This interface allows access to lower level functions of the IOMMU
3232 * like protection domain handling and assignement of devices to domains
3233 * which is not possible with the dma_ops interface.
3234 *
3235 *****************************************************************************/
3236
3237 static void cleanup_domain(struct protection_domain *domain)
3238 {
3239 struct iommu_dev_data *entry;
3240 unsigned long flags;
3241
3242 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3243
3244 while (!list_empty(&domain->dev_list)) {
3245 entry = list_first_entry(&domain->dev_list,
3246 struct iommu_dev_data, list);
3247 __detach_device(entry);
3248 atomic_set(&entry->bind, 0);
3249 }
3250
3251 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3252 }
3253
3254 static void protection_domain_free(struct protection_domain *domain)
3255 {
3256 if (!domain)
3257 return;
3258
3259 del_domain_from_list(domain);
3260
3261 if (domain->id)
3262 domain_id_free(domain->id);
3263
3264 kfree(domain);
3265 }
3266
3267 static struct protection_domain *protection_domain_alloc(void)
3268 {
3269 struct protection_domain *domain;
3270
3271 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3272 if (!domain)
3273 return NULL;
3274
3275 spin_lock_init(&domain->lock);
3276 mutex_init(&domain->api_lock);
3277 domain->id = domain_id_alloc();
3278 if (!domain->id)
3279 goto out_err;
3280 INIT_LIST_HEAD(&domain->dev_list);
3281
3282 add_domain_to_list(domain);
3283
3284 return domain;
3285
3286 out_err:
3287 kfree(domain);
3288
3289 return NULL;
3290 }
3291
3292 static int __init alloc_passthrough_domain(void)
3293 {
3294 if (pt_domain != NULL)
3295 return 0;
3296
3297 /* allocate passthrough domain */
3298 pt_domain = protection_domain_alloc();
3299 if (!pt_domain)
3300 return -ENOMEM;
3301
3302 pt_domain->mode = PAGE_MODE_NONE;
3303
3304 return 0;
3305 }
3306 static int amd_iommu_domain_init(struct iommu_domain *dom)
3307 {
3308 struct protection_domain *domain;
3309
3310 domain = protection_domain_alloc();
3311 if (!domain)
3312 goto out_free;
3313
3314 domain->mode = PAGE_MODE_3_LEVEL;
3315 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3316 if (!domain->pt_root)
3317 goto out_free;
3318
3319 domain->iommu_domain = dom;
3320
3321 dom->priv = domain;
3322
3323 dom->geometry.aperture_start = 0;
3324 dom->geometry.aperture_end = ~0ULL;
3325 dom->geometry.force_aperture = true;
3326
3327 return 0;
3328
3329 out_free:
3330 protection_domain_free(domain);
3331
3332 return -ENOMEM;
3333 }
3334
3335 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3336 {
3337 struct protection_domain *domain = dom->priv;
3338
3339 if (!domain)
3340 return;
3341
3342 if (domain->dev_cnt > 0)
3343 cleanup_domain(domain);
3344
3345 BUG_ON(domain->dev_cnt != 0);
3346
3347 if (domain->mode != PAGE_MODE_NONE)
3348 free_pagetable(domain);
3349
3350 if (domain->flags & PD_IOMMUV2_MASK)
3351 free_gcr3_table(domain);
3352
3353 protection_domain_free(domain);
3354
3355 dom->priv = NULL;
3356 }
3357
3358 static void amd_iommu_detach_device(struct iommu_domain *dom,
3359 struct device *dev)
3360 {
3361 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3362 struct amd_iommu *iommu;
3363 u16 devid;
3364
3365 if (!check_device(dev))
3366 return;
3367
3368 devid = get_device_id(dev);
3369
3370 if (dev_data->domain != NULL)
3371 detach_device(dev);
3372
3373 iommu = amd_iommu_rlookup_table[devid];
3374 if (!iommu)
3375 return;
3376
3377 iommu_completion_wait(iommu);
3378 }
3379
3380 static int amd_iommu_attach_device(struct iommu_domain *dom,
3381 struct device *dev)
3382 {
3383 struct protection_domain *domain = dom->priv;
3384 struct iommu_dev_data *dev_data;
3385 struct amd_iommu *iommu;
3386 int ret;
3387
3388 if (!check_device(dev))
3389 return -EINVAL;
3390
3391 dev_data = dev->archdata.iommu;
3392
3393 iommu = amd_iommu_rlookup_table[dev_data->devid];
3394 if (!iommu)
3395 return -EINVAL;
3396
3397 if (dev_data->domain)
3398 detach_device(dev);
3399
3400 ret = attach_device(dev, domain);
3401
3402 iommu_completion_wait(iommu);
3403
3404 return ret;
3405 }
3406
3407 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3408 phys_addr_t paddr, size_t page_size, int iommu_prot)
3409 {
3410 struct protection_domain *domain = dom->priv;
3411 int prot = 0;
3412 int ret;
3413
3414 if (domain->mode == PAGE_MODE_NONE)
3415 return -EINVAL;
3416
3417 if (iommu_prot & IOMMU_READ)
3418 prot |= IOMMU_PROT_IR;
3419 if (iommu_prot & IOMMU_WRITE)
3420 prot |= IOMMU_PROT_IW;
3421
3422 mutex_lock(&domain->api_lock);
3423 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3424 mutex_unlock(&domain->api_lock);
3425
3426 return ret;
3427 }
3428
3429 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3430 size_t page_size)
3431 {
3432 struct protection_domain *domain = dom->priv;
3433 size_t unmap_size;
3434
3435 if (domain->mode == PAGE_MODE_NONE)
3436 return -EINVAL;
3437
3438 mutex_lock(&domain->api_lock);
3439 unmap_size = iommu_unmap_page(domain, iova, page_size);
3440 mutex_unlock(&domain->api_lock);
3441
3442 domain_flush_tlb_pde(domain);
3443
3444 return unmap_size;
3445 }
3446
3447 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3448 dma_addr_t iova)
3449 {
3450 struct protection_domain *domain = dom->priv;
3451 unsigned long offset_mask, pte_pgsize;
3452 u64 *pte, __pte;
3453
3454 if (domain->mode == PAGE_MODE_NONE)
3455 return iova;
3456
3457 pte = fetch_pte(domain, iova, &pte_pgsize);
3458
3459 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3460 return 0;
3461
3462 offset_mask = pte_pgsize - 1;
3463 __pte = *pte & PM_ADDR_MASK;
3464
3465 return (__pte & ~offset_mask) | (iova & offset_mask);
3466 }
3467
3468 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3469 unsigned long cap)
3470 {
3471 switch (cap) {
3472 case IOMMU_CAP_CACHE_COHERENCY:
3473 return 1;
3474 case IOMMU_CAP_INTR_REMAP:
3475 return irq_remapping_enabled;
3476 }
3477
3478 return 0;
3479 }
3480
3481 static struct iommu_ops amd_iommu_ops = {
3482 .domain_init = amd_iommu_domain_init,
3483 .domain_destroy = amd_iommu_domain_destroy,
3484 .attach_dev = amd_iommu_attach_device,
3485 .detach_dev = amd_iommu_detach_device,
3486 .map = amd_iommu_map,
3487 .unmap = amd_iommu_unmap,
3488 .iova_to_phys = amd_iommu_iova_to_phys,
3489 .domain_has_cap = amd_iommu_domain_has_cap,
3490 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3491 };
3492
3493 /*****************************************************************************
3494 *
3495 * The next functions do a basic initialization of IOMMU for pass through
3496 * mode
3497 *
3498 * In passthrough mode the IOMMU is initialized and enabled but not used for
3499 * DMA-API translation.
3500 *
3501 *****************************************************************************/
3502
3503 int __init amd_iommu_init_passthrough(void)
3504 {
3505 struct iommu_dev_data *dev_data;
3506 struct pci_dev *dev = NULL;
3507 struct amd_iommu *iommu;
3508 u16 devid;
3509 int ret;
3510
3511 ret = alloc_passthrough_domain();
3512 if (ret)
3513 return ret;
3514
3515 for_each_pci_dev(dev) {
3516 if (!check_device(&dev->dev))
3517 continue;
3518
3519 dev_data = get_dev_data(&dev->dev);
3520 dev_data->passthrough = true;
3521
3522 devid = get_device_id(&dev->dev);
3523
3524 iommu = amd_iommu_rlookup_table[devid];
3525 if (!iommu)
3526 continue;
3527
3528 attach_device(&dev->dev, pt_domain);
3529 }
3530
3531 amd_iommu_stats_init();
3532
3533 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3534
3535 return 0;
3536 }
3537
3538 /* IOMMUv2 specific functions */
3539 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3540 {
3541 return atomic_notifier_chain_register(&ppr_notifier, nb);
3542 }
3543 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3544
3545 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3546 {
3547 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3548 }
3549 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3550
3551 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3552 {
3553 struct protection_domain *domain = dom->priv;
3554 unsigned long flags;
3555
3556 spin_lock_irqsave(&domain->lock, flags);
3557
3558 /* Update data structure */
3559 domain->mode = PAGE_MODE_NONE;
3560 domain->updated = true;
3561
3562 /* Make changes visible to IOMMUs */
3563 update_domain(domain);
3564
3565 /* Page-table is not visible to IOMMU anymore, so free it */
3566 free_pagetable(domain);
3567
3568 spin_unlock_irqrestore(&domain->lock, flags);
3569 }
3570 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3571
3572 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3573 {
3574 struct protection_domain *domain = dom->priv;
3575 unsigned long flags;
3576 int levels, ret;
3577
3578 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3579 return -EINVAL;
3580
3581 /* Number of GCR3 table levels required */
3582 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3583 levels += 1;
3584
3585 if (levels > amd_iommu_max_glx_val)
3586 return -EINVAL;
3587
3588 spin_lock_irqsave(&domain->lock, flags);
3589
3590 /*
3591 * Save us all sanity checks whether devices already in the
3592 * domain support IOMMUv2. Just force that the domain has no
3593 * devices attached when it is switched into IOMMUv2 mode.
3594 */
3595 ret = -EBUSY;
3596 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3597 goto out;
3598
3599 ret = -ENOMEM;
3600 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3601 if (domain->gcr3_tbl == NULL)
3602 goto out;
3603
3604 domain->glx = levels;
3605 domain->flags |= PD_IOMMUV2_MASK;
3606 domain->updated = true;
3607
3608 update_domain(domain);
3609
3610 ret = 0;
3611
3612 out:
3613 spin_unlock_irqrestore(&domain->lock, flags);
3614
3615 return ret;
3616 }
3617 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3618
3619 static int __flush_pasid(struct protection_domain *domain, int pasid,
3620 u64 address, bool size)
3621 {
3622 struct iommu_dev_data *dev_data;
3623 struct iommu_cmd cmd;
3624 int i, ret;
3625
3626 if (!(domain->flags & PD_IOMMUV2_MASK))
3627 return -EINVAL;
3628
3629 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3630
3631 /*
3632 * IOMMU TLB needs to be flushed before Device TLB to
3633 * prevent device TLB refill from IOMMU TLB
3634 */
3635 for (i = 0; i < amd_iommus_present; ++i) {
3636 if (domain->dev_iommu[i] == 0)
3637 continue;
3638
3639 ret = iommu_queue_command(amd_iommus[i], &cmd);
3640 if (ret != 0)
3641 goto out;
3642 }
3643
3644 /* Wait until IOMMU TLB flushes are complete */
3645 domain_flush_complete(domain);
3646
3647 /* Now flush device TLBs */
3648 list_for_each_entry(dev_data, &domain->dev_list, list) {
3649 struct amd_iommu *iommu;
3650 int qdep;
3651
3652 BUG_ON(!dev_data->ats.enabled);
3653
3654 qdep = dev_data->ats.qdep;
3655 iommu = amd_iommu_rlookup_table[dev_data->devid];
3656
3657 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3658 qdep, address, size);
3659
3660 ret = iommu_queue_command(iommu, &cmd);
3661 if (ret != 0)
3662 goto out;
3663 }
3664
3665 /* Wait until all device TLBs are flushed */
3666 domain_flush_complete(domain);
3667
3668 ret = 0;
3669
3670 out:
3671
3672 return ret;
3673 }
3674
3675 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3676 u64 address)
3677 {
3678 INC_STATS_COUNTER(invalidate_iotlb);
3679
3680 return __flush_pasid(domain, pasid, address, false);
3681 }
3682
3683 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3684 u64 address)
3685 {
3686 struct protection_domain *domain = dom->priv;
3687 unsigned long flags;
3688 int ret;
3689
3690 spin_lock_irqsave(&domain->lock, flags);
3691 ret = __amd_iommu_flush_page(domain, pasid, address);
3692 spin_unlock_irqrestore(&domain->lock, flags);
3693
3694 return ret;
3695 }
3696 EXPORT_SYMBOL(amd_iommu_flush_page);
3697
3698 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3699 {
3700 INC_STATS_COUNTER(invalidate_iotlb_all);
3701
3702 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3703 true);
3704 }
3705
3706 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3707 {
3708 struct protection_domain *domain = dom->priv;
3709 unsigned long flags;
3710 int ret;
3711
3712 spin_lock_irqsave(&domain->lock, flags);
3713 ret = __amd_iommu_flush_tlb(domain, pasid);
3714 spin_unlock_irqrestore(&domain->lock, flags);
3715
3716 return ret;
3717 }
3718 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3719
3720 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3721 {
3722 int index;
3723 u64 *pte;
3724
3725 while (true) {
3726
3727 index = (pasid >> (9 * level)) & 0x1ff;
3728 pte = &root[index];
3729
3730 if (level == 0)
3731 break;
3732
3733 if (!(*pte & GCR3_VALID)) {
3734 if (!alloc)
3735 return NULL;
3736
3737 root = (void *)get_zeroed_page(GFP_ATOMIC);
3738 if (root == NULL)
3739 return NULL;
3740
3741 *pte = __pa(root) | GCR3_VALID;
3742 }
3743
3744 root = __va(*pte & PAGE_MASK);
3745
3746 level -= 1;
3747 }
3748
3749 return pte;
3750 }
3751
3752 static int __set_gcr3(struct protection_domain *domain, int pasid,
3753 unsigned long cr3)
3754 {
3755 u64 *pte;
3756
3757 if (domain->mode != PAGE_MODE_NONE)
3758 return -EINVAL;
3759
3760 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3761 if (pte == NULL)
3762 return -ENOMEM;
3763
3764 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3765
3766 return __amd_iommu_flush_tlb(domain, pasid);
3767 }
3768
3769 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3770 {
3771 u64 *pte;
3772
3773 if (domain->mode != PAGE_MODE_NONE)
3774 return -EINVAL;
3775
3776 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3777 if (pte == NULL)
3778 return 0;
3779
3780 *pte = 0;
3781
3782 return __amd_iommu_flush_tlb(domain, pasid);
3783 }
3784
3785 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3786 unsigned long cr3)
3787 {
3788 struct protection_domain *domain = dom->priv;
3789 unsigned long flags;
3790 int ret;
3791
3792 spin_lock_irqsave(&domain->lock, flags);
3793 ret = __set_gcr3(domain, pasid, cr3);
3794 spin_unlock_irqrestore(&domain->lock, flags);
3795
3796 return ret;
3797 }
3798 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3799
3800 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3801 {
3802 struct protection_domain *domain = dom->priv;
3803 unsigned long flags;
3804 int ret;
3805
3806 spin_lock_irqsave(&domain->lock, flags);
3807 ret = __clear_gcr3(domain, pasid);
3808 spin_unlock_irqrestore(&domain->lock, flags);
3809
3810 return ret;
3811 }
3812 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3813
3814 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3815 int status, int tag)
3816 {
3817 struct iommu_dev_data *dev_data;
3818 struct amd_iommu *iommu;
3819 struct iommu_cmd cmd;
3820
3821 INC_STATS_COUNTER(complete_ppr);
3822
3823 dev_data = get_dev_data(&pdev->dev);
3824 iommu = amd_iommu_rlookup_table[dev_data->devid];
3825
3826 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3827 tag, dev_data->pri_tlp);
3828
3829 return iommu_queue_command(iommu, &cmd);
3830 }
3831 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3832
3833 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3834 {
3835 struct protection_domain *domain;
3836
3837 domain = get_domain(&pdev->dev);
3838 if (IS_ERR(domain))
3839 return NULL;
3840
3841 /* Only return IOMMUv2 domains */
3842 if (!(domain->flags & PD_IOMMUV2_MASK))
3843 return NULL;
3844
3845 return domain->iommu_domain;
3846 }
3847 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3848
3849 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3850 {
3851 struct iommu_dev_data *dev_data;
3852
3853 if (!amd_iommu_v2_supported())
3854 return;
3855
3856 dev_data = get_dev_data(&pdev->dev);
3857 dev_data->errata |= (1 << erratum);
3858 }
3859 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3860
3861 int amd_iommu_device_info(struct pci_dev *pdev,
3862 struct amd_iommu_device_info *info)
3863 {
3864 int max_pasids;
3865 int pos;
3866
3867 if (pdev == NULL || info == NULL)
3868 return -EINVAL;
3869
3870 if (!amd_iommu_v2_supported())
3871 return -EINVAL;
3872
3873 memset(info, 0, sizeof(*info));
3874
3875 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3876 if (pos)
3877 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3878
3879 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3880 if (pos)
3881 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3882
3883 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3884 if (pos) {
3885 int features;
3886
3887 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3888 max_pasids = min(max_pasids, (1 << 20));
3889
3890 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3891 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3892
3893 features = pci_pasid_features(pdev);
3894 if (features & PCI_PASID_CAP_EXEC)
3895 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3896 if (features & PCI_PASID_CAP_PRIV)
3897 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3898 }
3899
3900 return 0;
3901 }
3902 EXPORT_SYMBOL(amd_iommu_device_info);
3903
3904 #ifdef CONFIG_IRQ_REMAP
3905
3906 /*****************************************************************************
3907 *
3908 * Interrupt Remapping Implementation
3909 *
3910 *****************************************************************************/
3911
3912 union irte {
3913 u32 val;
3914 struct {
3915 u32 valid : 1,
3916 no_fault : 1,
3917 int_type : 3,
3918 rq_eoi : 1,
3919 dm : 1,
3920 rsvd_1 : 1,
3921 destination : 8,
3922 vector : 8,
3923 rsvd_2 : 8;
3924 } fields;
3925 };
3926
3927 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3928 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3929 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3930 #define DTE_IRQ_REMAP_ENABLE 1ULL
3931
3932 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3933 {
3934 u64 dte;
3935
3936 dte = amd_iommu_dev_table[devid].data[2];
3937 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3938 dte |= virt_to_phys(table->table);
3939 dte |= DTE_IRQ_REMAP_INTCTL;
3940 dte |= DTE_IRQ_TABLE_LEN;
3941 dte |= DTE_IRQ_REMAP_ENABLE;
3942
3943 amd_iommu_dev_table[devid].data[2] = dte;
3944 }
3945
3946 #define IRTE_ALLOCATED (~1U)
3947
3948 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3949 {
3950 struct irq_remap_table *table = NULL;
3951 struct amd_iommu *iommu;
3952 unsigned long flags;
3953 u16 alias;
3954
3955 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3956
3957 iommu = amd_iommu_rlookup_table[devid];
3958 if (!iommu)
3959 goto out_unlock;
3960
3961 table = irq_lookup_table[devid];
3962 if (table)
3963 goto out;
3964
3965 alias = amd_iommu_alias_table[devid];
3966 table = irq_lookup_table[alias];
3967 if (table) {
3968 irq_lookup_table[devid] = table;
3969 set_dte_irq_entry(devid, table);
3970 iommu_flush_dte(iommu, devid);
3971 goto out;
3972 }
3973
3974 /* Nothing there yet, allocate new irq remapping table */
3975 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3976 if (!table)
3977 goto out;
3978
3979 /* Initialize table spin-lock */
3980 spin_lock_init(&table->lock);
3981
3982 if (ioapic)
3983 /* Keep the first 32 indexes free for IOAPIC interrupts */
3984 table->min_index = 32;
3985
3986 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3987 if (!table->table) {
3988 kfree(table);
3989 table = NULL;
3990 goto out;
3991 }
3992
3993 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3994
3995 if (ioapic) {
3996 int i;
3997
3998 for (i = 0; i < 32; ++i)
3999 table->table[i] = IRTE_ALLOCATED;
4000 }
4001
4002 irq_lookup_table[devid] = table;
4003 set_dte_irq_entry(devid, table);
4004 iommu_flush_dte(iommu, devid);
4005 if (devid != alias) {
4006 irq_lookup_table[alias] = table;
4007 set_dte_irq_entry(alias, table);
4008 iommu_flush_dte(iommu, alias);
4009 }
4010
4011 out:
4012 iommu_completion_wait(iommu);
4013
4014 out_unlock:
4015 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
4016
4017 return table;
4018 }
4019
4020 static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
4021 {
4022 struct irq_remap_table *table;
4023 unsigned long flags;
4024 int index, c;
4025
4026 table = get_irq_table(devid, false);
4027 if (!table)
4028 return -ENODEV;
4029
4030 spin_lock_irqsave(&table->lock, flags);
4031
4032 /* Scan table for free entries */
4033 for (c = 0, index = table->min_index;
4034 index < MAX_IRQS_PER_TABLE;
4035 ++index) {
4036 if (table->table[index] == 0)
4037 c += 1;
4038 else
4039 c = 0;
4040
4041 if (c == count) {
4042 struct irq_2_irte *irte_info;
4043
4044 for (; c != 0; --c)
4045 table->table[index - c + 1] = IRTE_ALLOCATED;
4046
4047 index -= count - 1;
4048
4049 cfg->remapped = 1;
4050 irte_info = &cfg->irq_2_irte;
4051 irte_info->devid = devid;
4052 irte_info->index = index;
4053
4054 goto out;
4055 }
4056 }
4057
4058 index = -ENOSPC;
4059
4060 out:
4061 spin_unlock_irqrestore(&table->lock, flags);
4062
4063 return index;
4064 }
4065
4066 static int get_irte(u16 devid, int index, union irte *irte)
4067 {
4068 struct irq_remap_table *table;
4069 unsigned long flags;
4070
4071 table = get_irq_table(devid, false);
4072 if (!table)
4073 return -ENOMEM;
4074
4075 spin_lock_irqsave(&table->lock, flags);
4076 irte->val = table->table[index];
4077 spin_unlock_irqrestore(&table->lock, flags);
4078
4079 return 0;
4080 }
4081
4082 static int modify_irte(u16 devid, int index, union irte irte)
4083 {
4084 struct irq_remap_table *table;
4085 struct amd_iommu *iommu;
4086 unsigned long flags;
4087
4088 iommu = amd_iommu_rlookup_table[devid];
4089 if (iommu == NULL)
4090 return -EINVAL;
4091
4092 table = get_irq_table(devid, false);
4093 if (!table)
4094 return -ENOMEM;
4095
4096 spin_lock_irqsave(&table->lock, flags);
4097 table->table[index] = irte.val;
4098 spin_unlock_irqrestore(&table->lock, flags);
4099
4100 iommu_flush_irt(iommu, devid);
4101 iommu_completion_wait(iommu);
4102
4103 return 0;
4104 }
4105
4106 static void free_irte(u16 devid, int index)
4107 {
4108 struct irq_remap_table *table;
4109 struct amd_iommu *iommu;
4110 unsigned long flags;
4111
4112 iommu = amd_iommu_rlookup_table[devid];
4113 if (iommu == NULL)
4114 return;
4115
4116 table = get_irq_table(devid, false);
4117 if (!table)
4118 return;
4119
4120 spin_lock_irqsave(&table->lock, flags);
4121 table->table[index] = 0;
4122 spin_unlock_irqrestore(&table->lock, flags);
4123
4124 iommu_flush_irt(iommu, devid);
4125 iommu_completion_wait(iommu);
4126 }
4127
4128 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4129 unsigned int destination, int vector,
4130 struct io_apic_irq_attr *attr)
4131 {
4132 struct irq_remap_table *table;
4133 struct irq_2_irte *irte_info;
4134 struct irq_cfg *cfg;
4135 union irte irte;
4136 int ioapic_id;
4137 int index;
4138 int devid;
4139 int ret;
4140
4141 cfg = irq_get_chip_data(irq);
4142 if (!cfg)
4143 return -EINVAL;
4144
4145 irte_info = &cfg->irq_2_irte;
4146 ioapic_id = mpc_ioapic_id(attr->ioapic);
4147 devid = get_ioapic_devid(ioapic_id);
4148
4149 if (devid < 0)
4150 return devid;
4151
4152 table = get_irq_table(devid, true);
4153 if (table == NULL)
4154 return -ENOMEM;
4155
4156 index = attr->ioapic_pin;
4157
4158 /* Setup IRQ remapping info */
4159 cfg->remapped = 1;
4160 irte_info->devid = devid;
4161 irte_info->index = index;
4162
4163 /* Setup IRTE for IOMMU */
4164 irte.val = 0;
4165 irte.fields.vector = vector;
4166 irte.fields.int_type = apic->irq_delivery_mode;
4167 irte.fields.destination = destination;
4168 irte.fields.dm = apic->irq_dest_mode;
4169 irte.fields.valid = 1;
4170
4171 ret = modify_irte(devid, index, irte);
4172 if (ret)
4173 return ret;
4174
4175 /* Setup IOAPIC entry */
4176 memset(entry, 0, sizeof(*entry));
4177
4178 entry->vector = index;
4179 entry->mask = 0;
4180 entry->trigger = attr->trigger;
4181 entry->polarity = attr->polarity;
4182
4183 /*
4184 * Mask level triggered irqs.
4185 */
4186 if (attr->trigger)
4187 entry->mask = 1;
4188
4189 return 0;
4190 }
4191
4192 static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4193 bool force)
4194 {
4195 struct irq_2_irte *irte_info;
4196 unsigned int dest, irq;
4197 struct irq_cfg *cfg;
4198 union irte irte;
4199 int err;
4200
4201 if (!config_enabled(CONFIG_SMP))
4202 return -1;
4203
4204 cfg = data->chip_data;
4205 irq = data->irq;
4206 irte_info = &cfg->irq_2_irte;
4207
4208 if (!cpumask_intersects(mask, cpu_online_mask))
4209 return -EINVAL;
4210
4211 if (get_irte(irte_info->devid, irte_info->index, &irte))
4212 return -EBUSY;
4213
4214 if (assign_irq_vector(irq, cfg, mask))
4215 return -EBUSY;
4216
4217 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
4218 if (err) {
4219 if (assign_irq_vector(irq, cfg, data->affinity))
4220 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq);
4221 return err;
4222 }
4223
4224 irte.fields.vector = cfg->vector;
4225 irte.fields.destination = dest;
4226
4227 modify_irte(irte_info->devid, irte_info->index, irte);
4228
4229 if (cfg->move_in_progress)
4230 send_cleanup_vector(cfg);
4231
4232 cpumask_copy(data->affinity, mask);
4233
4234 return 0;
4235 }
4236
4237 static int free_irq(int irq)
4238 {
4239 struct irq_2_irte *irte_info;
4240 struct irq_cfg *cfg;
4241
4242 cfg = irq_get_chip_data(irq);
4243 if (!cfg)
4244 return -EINVAL;
4245
4246 irte_info = &cfg->irq_2_irte;
4247
4248 free_irte(irte_info->devid, irte_info->index);
4249
4250 return 0;
4251 }
4252
4253 static void compose_msi_msg(struct pci_dev *pdev,
4254 unsigned int irq, unsigned int dest,
4255 struct msi_msg *msg, u8 hpet_id)
4256 {
4257 struct irq_2_irte *irte_info;
4258 struct irq_cfg *cfg;
4259 union irte irte;
4260
4261 cfg = irq_get_chip_data(irq);
4262 if (!cfg)
4263 return;
4264
4265 irte_info = &cfg->irq_2_irte;
4266
4267 irte.val = 0;
4268 irte.fields.vector = cfg->vector;
4269 irte.fields.int_type = apic->irq_delivery_mode;
4270 irte.fields.destination = dest;
4271 irte.fields.dm = apic->irq_dest_mode;
4272 irte.fields.valid = 1;
4273
4274 modify_irte(irte_info->devid, irte_info->index, irte);
4275
4276 msg->address_hi = MSI_ADDR_BASE_HI;
4277 msg->address_lo = MSI_ADDR_BASE_LO;
4278 msg->data = irte_info->index;
4279 }
4280
4281 static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
4282 {
4283 struct irq_cfg *cfg;
4284 int index;
4285 u16 devid;
4286
4287 if (!pdev)
4288 return -EINVAL;
4289
4290 cfg = irq_get_chip_data(irq);
4291 if (!cfg)
4292 return -EINVAL;
4293
4294 devid = get_device_id(&pdev->dev);
4295 index = alloc_irq_index(cfg, devid, nvec);
4296
4297 return index < 0 ? MAX_IRQS_PER_TABLE : index;
4298 }
4299
4300 static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
4301 int index, int offset)
4302 {
4303 struct irq_2_irte *irte_info;
4304 struct irq_cfg *cfg;
4305 u16 devid;
4306
4307 if (!pdev)
4308 return -EINVAL;
4309
4310 cfg = irq_get_chip_data(irq);
4311 if (!cfg)
4312 return -EINVAL;
4313
4314 if (index >= MAX_IRQS_PER_TABLE)
4315 return 0;
4316
4317 devid = get_device_id(&pdev->dev);
4318 irte_info = &cfg->irq_2_irte;
4319
4320 cfg->remapped = 1;
4321 irte_info->devid = devid;
4322 irte_info->index = index + offset;
4323
4324 return 0;
4325 }
4326
4327 static int setup_hpet_msi(unsigned int irq, unsigned int id)
4328 {
4329 struct irq_2_irte *irte_info;
4330 struct irq_cfg *cfg;
4331 int index, devid;
4332
4333 cfg = irq_get_chip_data(irq);
4334 if (!cfg)
4335 return -EINVAL;
4336
4337 irte_info = &cfg->irq_2_irte;
4338 devid = get_hpet_devid(id);
4339 if (devid < 0)
4340 return devid;
4341
4342 index = alloc_irq_index(cfg, devid, 1);
4343 if (index < 0)
4344 return index;
4345
4346 cfg->remapped = 1;
4347 irte_info->devid = devid;
4348 irte_info->index = index;
4349
4350 return 0;
4351 }
4352
4353 struct irq_remap_ops amd_iommu_irq_ops = {
4354 .supported = amd_iommu_supported,
4355 .prepare = amd_iommu_prepare,
4356 .enable = amd_iommu_enable,
4357 .disable = amd_iommu_disable,
4358 .reenable = amd_iommu_reenable,
4359 .enable_faulting = amd_iommu_enable_faulting,
4360 .setup_ioapic_entry = setup_ioapic_entry,
4361 .set_affinity = set_affinity,
4362 .free_irq = free_irq,
4363 .compose_msi_msg = compose_msi_msg,
4364 .msi_alloc_irq = msi_alloc_irq,
4365 .msi_setup_irq = msi_setup_irq,
4366 .setup_hpet_msi = setup_hpet_msi,
4367 };
4368 #endif
Linux with added FPC-III support