drivers/media/i2c/tvp7002.c

   1 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
   2  * Digitizer with Horizontal PLL registers
   3  *
   4  * Copyright (C) 2009 Texas Instruments Inc
   5  * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
   6  *
   7  * This code is partially based upon the TVP5150 driver
   8  * written by Mauro Carvalho Chehab (mchehab@infradead.org),
   9  * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
  10  * and the TVP7002 driver in the TI LSP 2.10.00.14. Revisions by
  11  * Muralidharan Karicheri and Snehaprabha Narnakaje (TI).
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26  */
  27 #include <linux/delay.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/videodev2.h>
  31 #include <linux/module.h>
  32 #include <linux/v4l2-dv-timings.h>
  33 #include <media/tvp7002.h>
  34 #include <media/v4l2-async.h>
  35 #include <media/v4l2-device.h>
  36 #include <media/v4l2-common.h>
  37 #include <media/v4l2-ctrls.h>
  38 #include <media/v4l2-of.h>
  39
  40 #include "tvp7002_reg.h"
  41
  42 MODULE_DESCRIPTION("TI TVP7002 Video and Graphics Digitizer driver");
  43 MODULE_AUTHOR("Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>");
  44 MODULE_LICENSE("GPL");
  45
  46 /* I2C retry attempts */
  47 #define I2C_RETRY_COUNT         (5)
  48
  49 /* End of registers */
  50 #define TVP7002_EOR             0x5c
  51
  52 /* Read write definition for registers */
  53 #define TVP7002_READ            0
  54 #define TVP7002_WRITE           1
  55 #define TVP7002_RESERVED        2
  56
  57 /* Interlaced vs progressive mask and shift */
  58 #define TVP7002_IP_SHIFT        5
  59 #define TVP7002_INPR_MASK       (0x01 << TVP7002_IP_SHIFT)
  60
  61 /* Shift for CPL and LPF registers */
  62 #define TVP7002_CL_SHIFT        8
  63 #define TVP7002_CL_MASK         0x0f
  64
  65 /* Debug functions */
  66 static bool debug;
  67 module_param(debug, bool, 0644);
  68 MODULE_PARM_DESC(debug, "Debug level (0-2)");
  69
  70 /* Structure for register values */
  71 struct i2c_reg_value {
  72         u8 reg;
  73         u8 value;
  74         u8 type;
  75 };
  76
  77 /*
  78  * Register default values (according to tvp7002 datasheet)
  79  * In the case of read-only registers, the value (0xff) is
  80  * never written. R/W functionality is controlled by the
  81  * writable bit in the register struct definition.
  82  */
  83 static const struct i2c_reg_value tvp7002_init_default[] = {
  84         { TVP7002_CHIP_REV, 0xff, TVP7002_READ },
  85         { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
  86         { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
  87         { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
  88         { TVP7002_HPLL_PHASE_SEL, 0x80, TVP7002_WRITE },
  89         { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  90         { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  91         { TVP7002_HSYNC_OUT_W, 0x60, TVP7002_WRITE },
  92         { TVP7002_B_FINE_GAIN, 0x00, TVP7002_WRITE },
  93         { TVP7002_G_FINE_GAIN, 0x00, TVP7002_WRITE },
  94         { TVP7002_R_FINE_GAIN, 0x00, TVP7002_WRITE },
  95         { TVP7002_B_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  96         { TVP7002_G_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  97         { TVP7002_R_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  98         { TVP7002_SYNC_CTL_1, 0x20, TVP7002_WRITE },
  99         { TVP7002_HPLL_AND_CLAMP_CTL, 0x2e, TVP7002_WRITE },
 100         { TVP7002_SYNC_ON_G_THRS, 0x5d, TVP7002_WRITE },
 101         { TVP7002_SYNC_SEPARATOR_THRS, 0x47, TVP7002_WRITE },
 102         { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
 103         { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 104         { TVP7002_SYNC_DETECT_STAT, 0xff, TVP7002_READ },
 105         { TVP7002_OUT_FORMATTER, 0x47, TVP7002_WRITE },
 106         { TVP7002_MISC_CTL_1, 0x01, TVP7002_WRITE },
 107         { TVP7002_MISC_CTL_2, 0x00, TVP7002_WRITE },
 108         { TVP7002_MISC_CTL_3, 0x01, TVP7002_WRITE },
 109         { TVP7002_IN_MUX_SEL_1, 0x00, TVP7002_WRITE },
 110         { TVP7002_IN_MUX_SEL_2, 0x67, TVP7002_WRITE },
 111         { TVP7002_B_AND_G_COARSE_GAIN, 0x77, TVP7002_WRITE },
 112         { TVP7002_R_COARSE_GAIN, 0x07, TVP7002_WRITE },
 113         { TVP7002_FINE_OFF_LSBS, 0x00, TVP7002_WRITE },
 114         { TVP7002_B_COARSE_OFF, 0x10, TVP7002_WRITE },
 115         { TVP7002_G_COARSE_OFF, 0x10, TVP7002_WRITE },
 116         { TVP7002_R_COARSE_OFF, 0x10, TVP7002_WRITE },
 117         { TVP7002_HSOUT_OUT_START, 0x08, TVP7002_WRITE },
 118         { TVP7002_MISC_CTL_4, 0x00, TVP7002_WRITE },
 119         { TVP7002_B_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
 120         { TVP7002_G_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
 121         { TVP7002_R_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
 122         { TVP7002_AUTO_LVL_CTL_ENABLE, 0x80, TVP7002_WRITE },
 123         { TVP7002_DGTL_ALC_OUT_MSBS, 0xff, TVP7002_READ },
 124         { TVP7002_AUTO_LVL_CTL_FILTER, 0x53, TVP7002_WRITE },
 125         { 0x29, 0x08, TVP7002_RESERVED },
 126         { TVP7002_FINE_CLAMP_CTL, 0x07, TVP7002_WRITE },
 127         /* PWR_CTL is controlled only by the probe and reset functions */
 128         { TVP7002_PWR_CTL, 0x00, TVP7002_RESERVED },
 129         { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE },
 130         { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE },
 131         { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE },
 132         { TVP7002_RGB_COARSE_CLAMP_CTL, 0x8c, TVP7002_WRITE },
 133         { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE },
 134         { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 135         { 0x32, 0x18, TVP7002_RESERVED },
 136         { 0x33, 0x60, TVP7002_RESERVED },
 137         { TVP7002_MVIS_STRIPPER_W, 0xff, TVP7002_RESERVED },
 138         { TVP7002_VSYNC_ALGN, 0x10, TVP7002_WRITE },
 139         { TVP7002_SYNC_BYPASS, 0x00, TVP7002_WRITE },
 140         { TVP7002_L_FRAME_STAT_LSBS, 0xff, TVP7002_READ },
 141         { TVP7002_L_FRAME_STAT_MSBS, 0xff, TVP7002_READ },
 142         { TVP7002_CLK_L_STAT_LSBS, 0xff, TVP7002_READ },
 143         { TVP7002_CLK_L_STAT_MSBS, 0xff, TVP7002_READ },
 144         { TVP7002_HSYNC_W, 0xff, TVP7002_READ },
 145         { TVP7002_VSYNC_W, 0xff, TVP7002_READ },
 146         { TVP7002_L_LENGTH_TOL, 0x03, TVP7002_WRITE },
 147         { 0x3e, 0x60, TVP7002_RESERVED },
 148         { TVP7002_VIDEO_BWTH_CTL, 0x01, TVP7002_WRITE },
 149         { TVP7002_AVID_START_PIXEL_LSBS, 0x01, TVP7002_WRITE },
 150         { TVP7002_AVID_START_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
 151         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x06, TVP7002_WRITE },
 152         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
 153         { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
 154         { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
 155         { TVP7002_VBLK_F_0_DURATION, 0x1e, TVP7002_WRITE },
 156         { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
 157         { TVP7002_FBIT_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
 158         { TVP7002_FBIT_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
 159         { TVP7002_YUV_Y_G_COEF_LSBS, 0xe3, TVP7002_WRITE },
 160         { TVP7002_YUV_Y_G_COEF_MSBS, 0x16, TVP7002_WRITE },
 161         { TVP7002_YUV_Y_B_COEF_LSBS, 0x4f, TVP7002_WRITE },
 162         { TVP7002_YUV_Y_B_COEF_MSBS, 0x02, TVP7002_WRITE },
 163         { TVP7002_YUV_Y_R_COEF_LSBS, 0xce, TVP7002_WRITE },
 164         { TVP7002_YUV_Y_R_COEF_MSBS, 0x06, TVP7002_WRITE },
 165         { TVP7002_YUV_U_G_COEF_LSBS, 0xab, TVP7002_WRITE },
 166         { TVP7002_YUV_U_G_COEF_MSBS, 0xf3, TVP7002_WRITE },
 167         { TVP7002_YUV_U_B_COEF_LSBS, 0x00, TVP7002_WRITE },
 168         { TVP7002_YUV_U_B_COEF_MSBS, 0x10, TVP7002_WRITE },
 169         { TVP7002_YUV_U_R_COEF_LSBS, 0x55, TVP7002_WRITE },
 170         { TVP7002_YUV_U_R_COEF_MSBS, 0xfc, TVP7002_WRITE },
 171         { TVP7002_YUV_V_G_COEF_LSBS, 0x78, TVP7002_WRITE },
 172         { TVP7002_YUV_V_G_COEF_MSBS, 0xf1, TVP7002_WRITE },
 173         { TVP7002_YUV_V_B_COEF_LSBS, 0x88, TVP7002_WRITE },
 174         { TVP7002_YUV_V_B_COEF_MSBS, 0xfe, TVP7002_WRITE },
 175         { TVP7002_YUV_V_R_COEF_LSBS, 0x00, TVP7002_WRITE },
 176         { TVP7002_YUV_V_R_COEF_MSBS, 0x10, TVP7002_WRITE },
 177         /* This signals end of register values */
 178         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 179 };
 180
 181 /* Register parameters for 480P */
 182 static const struct i2c_reg_value tvp7002_parms_480P[] = {
 183         { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE },
 184         { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE },
 185         { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE },
 186         { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE },
 187         { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
 188         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE },
 189         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
 190         { TVP7002_VBLK_F_0_START_L_OFF, 0x03, TVP7002_WRITE },
 191         { TVP7002_VBLK_F_1_START_L_OFF, 0x01, TVP7002_WRITE },
 192         { TVP7002_VBLK_F_0_DURATION, 0x13, TVP7002_WRITE },
 193         { TVP7002_VBLK_F_1_DURATION, 0x13, TVP7002_WRITE },
 194         { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
 195         { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
 196         { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
 197         { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
 198         { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
 199         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 200 };
 201
 202 /* Register parameters for 576P */
 203 static const struct i2c_reg_value tvp7002_parms_576P[] = {
 204         { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE },
 205         { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
 206         { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE },
 207         { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE },
 208         { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
 209         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE },
 210         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
 211         { TVP7002_VBLK_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
 212         { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
 213         { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
 214         { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
 215         { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
 216         { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
 217         { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
 218         { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
 219         { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
 220         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 221 };
 222
 223 /* Register parameters for 1080I60 */
 224 static const struct i2c_reg_value tvp7002_parms_1080I60[] = {
 225         { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
 226         { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
 227         { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
 228         { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
 229         { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
 230         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
 231         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
 232         { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
 233         { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
 234         { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
 235         { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
 236         { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 237         { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
 238         { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
 239         { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
 240         { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 241         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 242 };
 243
 244 /* Register parameters for 1080P60 */
 245 static const struct i2c_reg_value tvp7002_parms_1080P60[] = {
 246         { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
 247         { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
 248         { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE },
 249         { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
 250         { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
 251         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
 252         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
 253         { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
 254         { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
 255         { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
 256         { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
 257         { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 258         { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
 259         { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
 260         { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
 261         { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 262         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 263 };
 264
 265 /* Register parameters for 1080I50 */
 266 static const struct i2c_reg_value tvp7002_parms_1080I50[] = {
 267         { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE },
 268         { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
 269         { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
 270         { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
 271         { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
 272         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
 273         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
 274         { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
 275         { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
 276         { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
 277         { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
 278         { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 279         { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
 280         { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
 281         { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
 282         { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 283         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 284 };
 285
 286 /* Register parameters for 720P60 */
 287 static const struct i2c_reg_value tvp7002_parms_720P60[] = {
 288         { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
 289         { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
 290         { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
 291         { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
 292         { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
 293         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
 294         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
 295         { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
 296         { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
 297         { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
 298         { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
 299         { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 300         { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
 301         { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
 302         { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
 303         { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 304         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 305 };
 306
 307 /* Register parameters for 720P50 */
 308 static const struct i2c_reg_value tvp7002_parms_720P50[] = {
 309         { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE },
 310         { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE },
 311         { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
 312         { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
 313         { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
 314         { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
 315         { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
 316         { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
 317         { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
 318         { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
 319         { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
 320         { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
 321         { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
 322         { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
 323         { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
 324         { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
 325         { TVP7002_EOR, 0xff, TVP7002_RESERVED }
 326 };
 327
 328 /* Timings definition for handling device operation */
 329 struct tvp7002_timings_definition {
 330         struct v4l2_dv_timings timings;
 331         const struct i2c_reg_value *p_settings;
 332         enum v4l2_colorspace color_space;
 333         enum v4l2_field scanmode;
 334         u16 progressive;
 335         u16 lines_per_frame;
 336         u16 cpl_min;
 337         u16 cpl_max;
 338 };
 339
 340 /* Struct list for digital video timings */
 341 static const struct tvp7002_timings_definition tvp7002_timings[] = {
 342         {
 343                 V4L2_DV_BT_CEA_1280X720P60,
 344                 tvp7002_parms_720P60,
 345                 V4L2_COLORSPACE_REC709,
 346                 V4L2_FIELD_NONE,
 347                 1,
 348                 0x2EE,
 349                 135,
 350                 153
 351         },
 352         {
 353                 V4L2_DV_BT_CEA_1920X1080I60,
 354                 tvp7002_parms_1080I60,
 355                 V4L2_COLORSPACE_REC709,
 356                 V4L2_FIELD_INTERLACED,
 357                 0,
 358                 0x465,
 359                 181,
 360                 205
 361         },
 362         {
 363                 V4L2_DV_BT_CEA_1920X1080I50,
 364                 tvp7002_parms_1080I50,
 365                 V4L2_COLORSPACE_REC709,
 366                 V4L2_FIELD_INTERLACED,
 367                 0,
 368                 0x465,
 369                 217,
 370                 245
 371         },
 372         {
 373                 V4L2_DV_BT_CEA_1280X720P50,
 374                 tvp7002_parms_720P50,
 375                 V4L2_COLORSPACE_REC709,
 376                 V4L2_FIELD_NONE,
 377                 1,
 378                 0x2EE,
 379                 163,
 380                 183
 381         },
 382         {
 383                 V4L2_DV_BT_CEA_1920X1080P60,
 384                 tvp7002_parms_1080P60,
 385                 V4L2_COLORSPACE_REC709,
 386                 V4L2_FIELD_NONE,
 387                 1,
 388                 0x465,
 389                 90,
 390                 102
 391         },
 392         {
 393                 V4L2_DV_BT_CEA_720X480P59_94,
 394                 tvp7002_parms_480P,
 395                 V4L2_COLORSPACE_SMPTE170M,
 396                 V4L2_FIELD_NONE,
 397                 1,
 398                 0x20D,
 399                 0xffff,
 400                 0xffff
 401         },
 402         {
 403                 V4L2_DV_BT_CEA_720X576P50,
 404                 tvp7002_parms_576P,
 405                 V4L2_COLORSPACE_SMPTE170M,
 406                 V4L2_FIELD_NONE,
 407                 1,
 408                 0x271,
 409                 0xffff,
 410                 0xffff
 411         }
 412 };
 413
 414 #define NUM_TIMINGS ARRAY_SIZE(tvp7002_timings)
 415
 416 /* Device definition */
 417 struct tvp7002 {
 418         struct v4l2_subdev sd;
 419         struct v4l2_ctrl_handler hdl;
 420         const struct tvp7002_config *pdata;
 421
 422         int ver;
 423         int streaming;
 424
 425         const struct tvp7002_timings_definition *current_timings;
 426         struct media_pad pad;
 427 };
 428
 429 /*
 430  * to_tvp7002 - Obtain device handler TVP7002
 431  * @sd: ptr to v4l2_subdev struct
 432  *
 433  * Returns device handler tvp7002.
 434  */
 435 static inline struct tvp7002 *to_tvp7002(struct v4l2_subdev *sd)
 436 {
 437         return container_of(sd, struct tvp7002, sd);
 438 }
 439
 440 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 441 {
 442         return &container_of(ctrl->handler, struct tvp7002, hdl)->sd;
 443 }
 444
 445 /*
 446  * tvp7002_read - Read a value from a register in an TVP7002
 447  * @sd: ptr to v4l2_subdev struct
 448  * @addr: TVP7002 register address
 449  * @dst: pointer to 8-bit destination
 450  *
 451  * Returns value read if successful, or non-zero (-1) otherwise.
 452  */
 453 static int tvp7002_read(struct v4l2_subdev *sd, u8 addr, u8 *dst)
 454 {
 455         struct i2c_client *c = v4l2_get_subdevdata(sd);
 456         int retry;
 457         int error;
 458
 459         for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
 460                 error = i2c_smbus_read_byte_data(c, addr);
 461
 462                 if (error >= 0) {
 463                         *dst = (u8)error;
 464                         return 0;
 465                 }
 466
 467                 msleep_interruptible(10);
 468         }
 469         v4l2_err(sd, "TVP7002 read error %d\n", error);
 470         return error;
 471 }
 472
 473 /*
 474  * tvp7002_read_err() - Read a register value with error code
 475  * @sd: pointer to standard V4L2 sub-device structure
 476  * @reg: destination register
 477  * @val: value to be read
 478  * @err: pointer to error value
 479  *
 480  * Read a value in a register and save error value in pointer.
 481  * Also update the register table if successful
 482  */
 483 static inline void tvp7002_read_err(struct v4l2_subdev *sd, u8 reg,
 484                                                         u8 *dst, int *err)
 485 {
 486         if (!*err)
 487                 *err = tvp7002_read(sd, reg, dst);
 488 }
 489
 490 /*
 491  * tvp7002_write() - Write a value to a register in TVP7002
 492  * @sd: ptr to v4l2_subdev struct
 493  * @addr: TVP7002 register address
 494  * @value: value to be written to the register
 495  *
 496  * Write a value to a register in an TVP7002 decoder device.
 497  * Returns zero if successful, or non-zero otherwise.
 498  */
 499 static int tvp7002_write(struct v4l2_subdev *sd, u8 addr, u8 value)
 500 {
 501         struct i2c_client *c;
 502         int retry;
 503         int error;
 504
 505         c = v4l2_get_subdevdata(sd);
 506
 507         for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
 508                 error = i2c_smbus_write_byte_data(c, addr, value);
 509
 510                 if (error >= 0)
 511                         return 0;
 512
 513                 v4l2_warn(sd, "Write: retry ... %d\n", retry);
 514                 msleep_interruptible(10);
 515         }
 516         v4l2_err(sd, "TVP7002 write error %d\n", error);
 517         return error;
 518 }
 519
 520 /*
 521  * tvp7002_write_err() - Write a register value with error code
 522  * @sd: pointer to standard V4L2 sub-device structure
 523  * @reg: destination register
 524  * @val: value to be written
 525  * @err: pointer to error value
 526  *
 527  * Write a value in a register and save error value in pointer.
 528  * Also update the register table if successful
 529  */
 530 static inline void tvp7002_write_err(struct v4l2_subdev *sd, u8 reg,
 531                                                         u8 val, int *err)
 532 {
 533         if (!*err)
 534                 *err = tvp7002_write(sd, reg, val);
 535 }
 536
 537 /*
 538  * tvp7002_write_inittab() - Write initialization values
 539  * @sd: ptr to v4l2_subdev struct
 540  * @regs: ptr to i2c_reg_value struct
 541  *
 542  * Write initialization values.
 543  * Returns zero or -EINVAL if read operation fails.
 544  */
 545 static int tvp7002_write_inittab(struct v4l2_subdev *sd,
 546                                         const struct i2c_reg_value *regs)
 547 {
 548         int error = 0;
 549
 550         /* Initialize the first (defined) registers */
 551         while (TVP7002_EOR != regs->reg) {
 552                 if (TVP7002_WRITE == regs->type)
 553                         tvp7002_write_err(sd, regs->reg, regs->value, &error);
 554                 regs++;
 555         }
 556
 557         return error;
 558 }
 559
 560 static int tvp7002_s_dv_timings(struct v4l2_subdev *sd,
 561                                         struct v4l2_dv_timings *dv_timings)
 562 {
 563         struct tvp7002 *device = to_tvp7002(sd);
 564         const struct v4l2_bt_timings *bt = &dv_timings->bt;
 565         int i;
 566
 567         if (dv_timings->type != V4L2_DV_BT_656_1120)
 568                 return -EINVAL;
 569         for (i = 0; i < NUM_TIMINGS; i++) {
 570                 const struct v4l2_bt_timings *t = &tvp7002_timings[i].timings.bt;
 571
 572                 if (!memcmp(bt, t, &bt->standards - &bt->width)) {
 573                         device->current_timings = &tvp7002_timings[i];
 574                         return tvp7002_write_inittab(sd, tvp7002_timings[i].p_settings);
 575                 }
 576         }
 577         return -EINVAL;
 578 }
 579
 580 static int tvp7002_g_dv_timings(struct v4l2_subdev *sd,
 581                                         struct v4l2_dv_timings *dv_timings)
 582 {
 583         struct tvp7002 *device = to_tvp7002(sd);
 584
 585         *dv_timings = device->current_timings->timings;
 586         return 0;
 587 }
 588
 589 /*
 590  * tvp7002_s_ctrl() - Set a control
 591  * @ctrl: ptr to v4l2_ctrl struct
 592  *
 593  * Set a control in TVP7002 decoder device.
 594  * Returns zero when successful or -EINVAL if register access fails.
 595  */
 596 static int tvp7002_s_ctrl(struct v4l2_ctrl *ctrl)
 597 {
 598         struct v4l2_subdev *sd = to_sd(ctrl);
 599         int error = 0;
 600
 601         switch (ctrl->id) {
 602         case V4L2_CID_GAIN:
 603                 tvp7002_write_err(sd, TVP7002_R_FINE_GAIN, ctrl->val, &error);
 604                 tvp7002_write_err(sd, TVP7002_G_FINE_GAIN, ctrl->val, &error);
 605                 tvp7002_write_err(sd, TVP7002_B_FINE_GAIN, ctrl->val, &error);
 606                 return error;
 607         }
 608         return -EINVAL;
 609 }
 610
 611 /*
 612  * tvp7002_mbus_fmt() - V4L2 decoder interface handler for try/s/g_mbus_fmt
 613  * @sd: pointer to standard V4L2 sub-device structure
 614  * @f: pointer to mediabus format structure
 615  *
 616  * Negotiate the image capture size and mediabus format.
 617  * There is only one possible format, so this single function works for
 618  * get, set and try.
 619  */
 620 static int tvp7002_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *f)
 621 {
 622         struct tvp7002 *device = to_tvp7002(sd);
 623         const struct v4l2_bt_timings *bt = &device->current_timings->timings.bt;
 624
 625         f->width = bt->width;
 626         f->height = bt->height;
 627         f->code = V4L2_MBUS_FMT_YUYV10_1X20;
 628         f->field = device->current_timings->scanmode;
 629         f->colorspace = device->current_timings->color_space;
 630
 631         v4l2_dbg(1, debug, sd, "MBUS_FMT: Width - %d, Height - %d",
 632                         f->width, f->height);
 633         return 0;
 634 }
 635
 636 /*
 637  * tvp7002_query_dv() - query DV timings
 638  * @sd: pointer to standard V4L2 sub-device structure
 639  * @index: index into the tvp7002_timings array
 640  *
 641  * Returns the current DV timings detected by TVP7002. If no active input is
 642  * detected, returns -EINVAL
 643  */
 644 static int tvp7002_query_dv(struct v4l2_subdev *sd, int *index)
 645 {
 646         const struct tvp7002_timings_definition *timings = tvp7002_timings;
 647         u8 progressive;
 648         u32 lpfr;
 649         u32 cpln;
 650         int error = 0;
 651         u8 lpf_lsb;
 652         u8 lpf_msb;
 653         u8 cpl_lsb;
 654         u8 cpl_msb;
 655
 656         /* Return invalid index if no active input is detected */
 657         *index = NUM_TIMINGS;
 658
 659         /* Read standards from device registers */
 660         tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_LSBS, &lpf_lsb, &error);
 661         tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_MSBS, &lpf_msb, &error);
 662
 663         if (error < 0)
 664                 return error;
 665
 666         tvp7002_read_err(sd, TVP7002_CLK_L_STAT_LSBS, &cpl_lsb, &error);
 667         tvp7002_read_err(sd, TVP7002_CLK_L_STAT_MSBS, &cpl_msb, &error);
 668
 669         if (error < 0)
 670                 return error;
 671
 672         /* Get lines per frame, clocks per line and interlaced/progresive */
 673         lpfr = lpf_lsb | ((TVP7002_CL_MASK & lpf_msb) << TVP7002_CL_SHIFT);
 674         cpln = cpl_lsb | ((TVP7002_CL_MASK & cpl_msb) << TVP7002_CL_SHIFT);
 675         progressive = (lpf_msb & TVP7002_INPR_MASK) >> TVP7002_IP_SHIFT;
 676
 677         /* Do checking of video modes */
 678         for (*index = 0; *index < NUM_TIMINGS; (*index)++, timings++)
 679                 if (lpfr == timings->lines_per_frame &&
 680                         progressive == timings->progressive) {
 681                         if (timings->cpl_min == 0xffff)
 682                                 break;
 683                         if (cpln >= timings->cpl_min && cpln <= timings->cpl_max)
 684                                 break;
 685                 }
 686
 687         if (*index == NUM_TIMINGS) {
 688                 v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n",
 689                                                                 lpfr, cpln);
 690                 return -ENOLINK;
 691         }
 692
 693         /* Update lines per frame and clocks per line info */
 694         v4l2_dbg(1, debug, sd, "detected timings: %d\n", *index);
 695         return 0;
 696 }
 697
 698 static int tvp7002_query_dv_timings(struct v4l2_subdev *sd,
 699                                         struct v4l2_dv_timings *timings)
 700 {
 701         int index;
 702         int err = tvp7002_query_dv(sd, &index);
 703
 704         if (err)
 705                 return err;
 706         *timings = tvp7002_timings[index].timings;
 707         return 0;
 708 }
 709
 710 #ifdef CONFIG_VIDEO_ADV_DEBUG
 711 /*
 712  * tvp7002_g_register() - Get the value of a register
 713  * @sd: ptr to v4l2_subdev struct
 714  * @reg: ptr to v4l2_dbg_register struct
 715  *
 716  * Get the value of a TVP7002 decoder device register.
 717  * Returns zero when successful, -EINVAL if register read fails or
 718  * access to I2C client fails.
 719  */
 720 static int tvp7002_g_register(struct v4l2_subdev *sd,
 721                                                 struct v4l2_dbg_register *reg)
 722 {
 723         u8 val;
 724         int ret;
 725
 726         ret = tvp7002_read(sd, reg->reg & 0xff, &val);
 727         reg->val = val;
 728         reg->size = 1;
 729         return ret;
 730 }
 731
 732 /*
 733  * tvp7002_s_register() - set a control
 734  * @sd: ptr to v4l2_subdev struct
 735  * @reg: ptr to v4l2_dbg_register struct
 736  *
 737  * Get the value of a TVP7002 decoder device register.
 738  * Returns zero when successful, -EINVAL if register read fails.
 739  */
 740 static int tvp7002_s_register(struct v4l2_subdev *sd,
 741                                                 const struct v4l2_dbg_register *reg)
 742 {
 743         return tvp7002_write(sd, reg->reg & 0xff, reg->val & 0xff);
 744 }
 745 #endif
 746
 747 /*
 748  * tvp7002_enum_mbus_fmt() - Enum supported mediabus formats
 749  * @sd: pointer to standard V4L2 sub-device structure
 750  * @index: format index
 751  * @code: pointer to mediabus format
 752  *
 753  * Enumerate supported mediabus formats.
 754  */
 755
 756 static int tvp7002_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
 757                                         enum v4l2_mbus_pixelcode *code)
 758 {
 759         /* Check requested format index is within range */
 760         if (index)
 761                 return -EINVAL;
 762         *code = V4L2_MBUS_FMT_YUYV10_1X20;
 763         return 0;
 764 }
 765
 766 /*
 767  * tvp7002_s_stream() - V4L2 decoder i/f handler for s_stream
 768  * @sd: pointer to standard V4L2 sub-device structure
 769  * @enable: streaming enable or disable
 770  *
 771  * Sets streaming to enable or disable, if possible.
 772  */
 773 static int tvp7002_s_stream(struct v4l2_subdev *sd, int enable)
 774 {
 775         struct tvp7002 *device = to_tvp7002(sd);
 776         int error = 0;
 777
 778         if (device->streaming == enable)
 779                 return 0;
 780
 781         if (enable) {
 782                 /* Set output state on (low impedance means stream on) */
 783                 error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x00);
 784                 device->streaming = enable;
 785         } else {
 786                 /* Set output state off (high impedance means stream off) */
 787                 error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x03);
 788                 if (error)
 789                         v4l2_dbg(1, debug, sd, "Unable to stop streaming\n");
 790
 791                 device->streaming = enable;
 792         }
 793
 794         return error;
 795 }
 796
 797 /*
 798  * tvp7002_log_status() - Print information about register settings
 799  * @sd: ptr to v4l2_subdev struct
 800  *
 801  * Log register values of a TVP7002 decoder device.
 802  * Returns zero or -EINVAL if read operation fails.
 803  */
 804 static int tvp7002_log_status(struct v4l2_subdev *sd)
 805 {
 806         struct tvp7002 *device = to_tvp7002(sd);
 807         const struct v4l2_bt_timings *bt;
 808         int detected;
 809
 810         /* Find my current timings */
 811         tvp7002_query_dv(sd, &detected);
 812
 813         bt = &device->current_timings->timings.bt;
 814         v4l2_info(sd, "Selected DV Timings: %ux%u\n", bt->width, bt->height);
 815         if (detected == NUM_TIMINGS) {
 816                 v4l2_info(sd, "Detected DV Timings: None\n");
 817         } else {
 818                 bt = &tvp7002_timings[detected].timings.bt;
 819                 v4l2_info(sd, "Detected DV Timings: %ux%u\n",
 820                                 bt->width, bt->height);
 821         }
 822         v4l2_info(sd, "Streaming enabled: %s\n",
 823                                         device->streaming ? "yes" : "no");
 824
 825         /* Print the current value of the gain control */
 826         v4l2_ctrl_handler_log_status(&device->hdl, sd->name);
 827
 828         return 0;
 829 }
 830
 831 static int tvp7002_enum_dv_timings(struct v4l2_subdev *sd,
 832                 struct v4l2_enum_dv_timings *timings)
 833 {
 834         /* Check requested format index is within range */
 835         if (timings->index >= NUM_TIMINGS)
 836                 return -EINVAL;
 837
 838         timings->timings = tvp7002_timings[timings->index].timings;
 839         return 0;
 840 }
 841
 842 static const struct v4l2_ctrl_ops tvp7002_ctrl_ops = {
 843         .s_ctrl = tvp7002_s_ctrl,
 844 };
 845
 846 /*
 847  * tvp7002_enum_mbus_code() - Enum supported digital video format on pad
 848  * @sd: pointer to standard V4L2 sub-device structure
 849  * @fh: file handle for the subdev
 850  * @code: pointer to subdev enum mbus code struct
 851  *
 852  * Enumerate supported digital video formats for pad.
 853  */
 854 static int
 855 tvp7002_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
 856                        struct v4l2_subdev_mbus_code_enum *code)
 857 {
 858         /* Check requested format index is within range */
 859         if (code->index != 0)
 860                 return -EINVAL;
 861
 862         code->code = V4L2_MBUS_FMT_YUYV10_1X20;
 863
 864         return 0;
 865 }
 866
 867 /*
 868  * tvp7002_get_pad_format() - get video format on pad
 869  * @sd: pointer to standard V4L2 sub-device structure
 870  * @fh: file handle for the subdev
 871  * @fmt: pointer to subdev format struct
 872  *
 873  * get video format for pad.
 874  */
 875 static int
 876 tvp7002_get_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
 877                        struct v4l2_subdev_format *fmt)
 878 {
 879         struct tvp7002 *tvp7002 = to_tvp7002(sd);
 880
 881         fmt->format.code = V4L2_MBUS_FMT_YUYV10_1X20;
 882         fmt->format.width = tvp7002->current_timings->timings.bt.width;
 883         fmt->format.height = tvp7002->current_timings->timings.bt.height;
 884         fmt->format.field = tvp7002->current_timings->scanmode;
 885         fmt->format.colorspace = tvp7002->current_timings->color_space;
 886
 887         return 0;
 888 }
 889
 890 /*
 891  * tvp7002_set_pad_format() - set video format on pad
 892  * @sd: pointer to standard V4L2 sub-device structure
 893  * @fh: file handle for the subdev
 894  * @fmt: pointer to subdev format struct
 895  *
 896  * set video format for pad.
 897  */
 898 static int
 899 tvp7002_set_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
 900                        struct v4l2_subdev_format *fmt)
 901 {
 902         return tvp7002_get_pad_format(sd, fh, fmt);
 903 }
 904
 905 /* V4L2 core operation handlers */
 906 static const struct v4l2_subdev_core_ops tvp7002_core_ops = {
 907         .log_status = tvp7002_log_status,
 908         .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
 909         .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
 910         .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
 911         .g_ctrl = v4l2_subdev_g_ctrl,
 912         .s_ctrl = v4l2_subdev_s_ctrl,
 913         .queryctrl = v4l2_subdev_queryctrl,
 914         .querymenu = v4l2_subdev_querymenu,
 915 #ifdef CONFIG_VIDEO_ADV_DEBUG
 916         .g_register = tvp7002_g_register,
 917         .s_register = tvp7002_s_register,
 918 #endif
 919 };
 920
 921 /* Specific video subsystem operation handlers */
 922 static const struct v4l2_subdev_video_ops tvp7002_video_ops = {
 923         .g_dv_timings = tvp7002_g_dv_timings,
 924         .s_dv_timings = tvp7002_s_dv_timings,
 925         .enum_dv_timings = tvp7002_enum_dv_timings,
 926         .query_dv_timings = tvp7002_query_dv_timings,
 927         .s_stream = tvp7002_s_stream,
 928         .g_mbus_fmt = tvp7002_mbus_fmt,
 929         .try_mbus_fmt = tvp7002_mbus_fmt,
 930         .s_mbus_fmt = tvp7002_mbus_fmt,
 931         .enum_mbus_fmt = tvp7002_enum_mbus_fmt,
 932 };
 933
 934 /* media pad related operation handlers */
 935 static const struct v4l2_subdev_pad_ops tvp7002_pad_ops = {
 936         .enum_mbus_code = tvp7002_enum_mbus_code,
 937         .get_fmt = tvp7002_get_pad_format,
 938         .set_fmt = tvp7002_set_pad_format,
 939 };
 940
 941 /* V4L2 top level operation handlers */
 942 static const struct v4l2_subdev_ops tvp7002_ops = {
 943         .core = &tvp7002_core_ops,
 944         .video = &tvp7002_video_ops,
 945         .pad = &tvp7002_pad_ops,
 946 };
 947
 948 static struct tvp7002_config *
 949 tvp7002_get_pdata(struct i2c_client *client)
 950 {
 951         struct v4l2_of_endpoint bus_cfg;
 952         struct tvp7002_config *pdata;
 953         struct device_node *endpoint;
 954         unsigned int flags;
 955
 956         if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
 957                 return client->dev.platform_data;
 958
 959         endpoint = v4l2_of_get_next_endpoint(client->dev.of_node, NULL);
 960         if (!endpoint)
 961                 return NULL;
 962
 963         pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
 964         if (!pdata)
 965                 goto done;
 966
 967         v4l2_of_parse_endpoint(endpoint, &bus_cfg);
 968         flags = bus_cfg.bus.parallel.flags;
 969
 970         if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
 971                 pdata->hs_polarity = 1;
 972
 973         if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
 974                 pdata->vs_polarity = 1;
 975
 976         if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
 977                 pdata->clk_polarity = 1;
 978
 979         if (flags & V4L2_MBUS_FIELD_EVEN_HIGH)
 980                 pdata->fid_polarity = 1;
 981
 982         if (flags & V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH)
 983                 pdata->sog_polarity = 1;
 984
 985 done:
 986         of_node_put(endpoint);
 987         return pdata;
 988 }
 989
 990 /*
 991  * tvp7002_probe - Probe a TVP7002 device
 992  * @c: ptr to i2c_client struct
 993  * @id: ptr to i2c_device_id struct
 994  *
 995  * Initialize the TVP7002 device
 996  * Returns zero when successful, -EINVAL if register read fails or
 997  * -EIO if i2c access is not available.
 998  */
 999 static int tvp7002_probe(struct i2c_client *c, const struct i2c_device_id *id)
1000 {
1001         struct tvp7002_config *pdata = tvp7002_get_pdata(c);
1002         struct v4l2_subdev *sd;
1003         struct tvp7002 *device;
1004         struct v4l2_dv_timings timings;
1005         int polarity_a;
1006         int polarity_b;
1007         u8 revision;
1008         int error;
1009
1010         if (pdata == NULL) {
1011                 dev_err(&c->dev, "No platform data\n");
1012                 return -EINVAL;
1013         }
1014
1015         /* Check if the adapter supports the needed features */
1016         if (!i2c_check_functionality(c->adapter,
1017                 I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
1018                 return -EIO;
1019
1020         device = devm_kzalloc(&c->dev, sizeof(struct tvp7002), GFP_KERNEL);
1021
1022         if (!device)
1023                 return -ENOMEM;
1024
1025         sd = &device->sd;
1026         device->pdata = pdata;
1027         device->current_timings = tvp7002_timings;
1028
1029         /* Tell v4l2 the device is ready */
1030         v4l2_i2c_subdev_init(sd, c, &tvp7002_ops);
1031         v4l_info(c, "tvp7002 found @ 0x%02x (%s)\n",
1032                                         c->addr, c->adapter->name);
1033
1034         error = tvp7002_read(sd, TVP7002_CHIP_REV, &revision);
1035         if (error < 0)
1036                 return error;
1037
1038         /* Get revision number */
1039         v4l2_info(sd, "Rev. %02x detected.\n", revision);
1040         if (revision != 0x02)
1041                 v4l2_info(sd, "Unknown revision detected.\n");
1042
1043         /* Initializes TVP7002 to its default values */
1044         error = tvp7002_write_inittab(sd, tvp7002_init_default);
1045
1046         if (error < 0)
1047                 return error;
1048
1049         /* Set polarity information after registers have been set */
1050         polarity_a = 0x20 | device->pdata->hs_polarity << 5
1051                         | device->pdata->vs_polarity << 2;
1052         error = tvp7002_write(sd, TVP7002_SYNC_CTL_1, polarity_a);
1053         if (error < 0)
1054                 return error;
1055
1056         polarity_b = 0x01  | device->pdata->fid_polarity << 2
1057                         | device->pdata->sog_polarity << 1
1058                         | device->pdata->clk_polarity;
1059         error = tvp7002_write(sd, TVP7002_MISC_CTL_3, polarity_b);
1060         if (error < 0)
1061                 return error;
1062
1063         /* Set registers according to default video mode */
1064         timings = device->current_timings->timings;
1065         error = tvp7002_s_dv_timings(sd, &timings);
1066
1067 #if defined(CONFIG_MEDIA_CONTROLLER)
1068         device->pad.flags = MEDIA_PAD_FL_SOURCE;
1069         device->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1070         device->sd.entity.flags |= MEDIA_ENT_T_V4L2_SUBDEV_DECODER;
1071
1072         error = media_entity_init(&device->sd.entity, 1, &device->pad, 0);
1073         if (error < 0)
1074                 return error;
1075 #endif
1076
1077         v4l2_ctrl_handler_init(&device->hdl, 1);
1078         v4l2_ctrl_new_std(&device->hdl, &tvp7002_ctrl_ops,
1079                         V4L2_CID_GAIN, 0, 255, 1, 0);
1080         sd->ctrl_handler = &device->hdl;
1081         if (device->hdl.error) {
1082                 error = device->hdl.error;
1083                 goto error;
1084         }
1085         v4l2_ctrl_handler_setup(&device->hdl);
1086
1087         error = v4l2_async_register_subdev(&device->sd);
1088         if (error)
1089                 goto error;
1090
1091         return 0;
1092
1093 error:
1094         v4l2_ctrl_handler_free(&device->hdl);
1095 #if defined(CONFIG_MEDIA_CONTROLLER)
1096         media_entity_cleanup(&device->sd.entity);
1097 #endif
1098         return error;
1099 }
1100
1101 /*
1102  * tvp7002_remove - Remove TVP7002 device support
1103  * @c: ptr to i2c_client struct
1104  *
1105  * Reset the TVP7002 device
1106  * Returns zero.
1107  */
1108 static int tvp7002_remove(struct i2c_client *c)
1109 {
1110         struct v4l2_subdev *sd = i2c_get_clientdata(c);
1111         struct tvp7002 *device = to_tvp7002(sd);
1112
1113         v4l2_dbg(1, debug, sd, "Removing tvp7002 adapter"
1114                                 "on address 0x%x\n", c->addr);
1115         v4l2_async_unregister_subdev(&device->sd);
1116 #if defined(CONFIG_MEDIA_CONTROLLER)
1117         media_entity_cleanup(&device->sd.entity);
1118 #endif
1119         v4l2_device_unregister_subdev(sd);
1120         v4l2_ctrl_handler_free(&device->hdl);
1121         return 0;
1122 }
1123
1124 /* I2C Device ID table */
1125 static const struct i2c_device_id tvp7002_id[] = {
1126         { "tvp7002", 0 },
1127         { }
1128 };
1129 MODULE_DEVICE_TABLE(i2c, tvp7002_id);
1130
1131 #if IS_ENABLED(CONFIG_OF)
1132 static const struct of_device_id tvp7002_of_match[] = {
1133         { .compatible = "ti,tvp7002", },
1134         { /* sentinel */ },
1135 };
1136 MODULE_DEVICE_TABLE(of, tvp7002_of_match);
1137 #endif
1138
1139 /* I2C driver data */
1140 static struct i2c_driver tvp7002_driver = {
1141         .driver = {
1142                 .of_match_table = of_match_ptr(tvp7002_of_match),
1143                 .owner = THIS_MODULE,
1144                 .name = TVP7002_MODULE_NAME,
1145         },
1146         .probe = tvp7002_probe,
1147         .remove = tvp7002_remove,
1148         .id_table = tvp7002_id,
1149 };
1150
1151 module_i2c_driver(tvp7002_driver);