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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / media / platform / exynos4-is / mipi-csis.c
blob0914230b42de55ea531d63cc10bce844d1282ed3
1 /*
2 * Samsung S5P/EXYNOS SoC series MIPI-CSI receiver driver
3 *
4 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
5 * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/irq.h>
19 #include <linux/kernel.h>
20 #include <linux/memory.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/platform_data/mipi-csis.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/slab.h>
28 #include <linux/spinlock.h>
29 #include <linux/videodev2.h>
30 #include <media/s5p_fimc.h>
31 #include <media/v4l2-of.h>
32 #include <media/v4l2-subdev.h>
33
34 #include "mipi-csis.h"
35
36 static int debug;
37 module_param(debug, int, 0644);
38 MODULE_PARM_DESC(debug, "Debug level (0-2)");
39
40 /* Register map definition */
41
42 /* CSIS global control */
43 #define S5PCSIS_CTRL 0x00
44 #define S5PCSIS_CTRL_DPDN_DEFAULT (0 << 31)
45 #define S5PCSIS_CTRL_DPDN_SWAP (1 << 31)
46 #define S5PCSIS_CTRL_ALIGN_32BIT (1 << 20)
47 #define S5PCSIS_CTRL_UPDATE_SHADOW (1 << 16)
48 #define S5PCSIS_CTRL_WCLK_EXTCLK (1 << 8)
49 #define S5PCSIS_CTRL_RESET (1 << 4)
50 #define S5PCSIS_CTRL_ENABLE (1 << 0)
51
52 /* D-PHY control */
53 #define S5PCSIS_DPHYCTRL 0x04
54 #define S5PCSIS_DPHYCTRL_HSS_MASK (0x1f << 27)
55 #define S5PCSIS_DPHYCTRL_ENABLE (0x1f << 0)
56
57 #define S5PCSIS_CONFIG 0x08
58 #define S5PCSIS_CFG_FMT_YCBCR422_8BIT (0x1e << 2)
59 #define S5PCSIS_CFG_FMT_RAW8 (0x2a << 2)
60 #define S5PCSIS_CFG_FMT_RAW10 (0x2b << 2)
61 #define S5PCSIS_CFG_FMT_RAW12 (0x2c << 2)
62 /* User defined formats, x = 1...4 */
63 #define S5PCSIS_CFG_FMT_USER(x) ((0x30 + x - 1) << 2)
64 #define S5PCSIS_CFG_FMT_MASK (0x3f << 2)
65 #define S5PCSIS_CFG_NR_LANE_MASK 3
66
67 /* Interrupt mask */
68 #define S5PCSIS_INTMSK 0x10
69 #define S5PCSIS_INTMSK_EVEN_BEFORE (1 << 31)
70 #define S5PCSIS_INTMSK_EVEN_AFTER (1 << 30)
71 #define S5PCSIS_INTMSK_ODD_BEFORE (1 << 29)
72 #define S5PCSIS_INTMSK_ODD_AFTER (1 << 28)
73 #define S5PCSIS_INTMSK_FRAME_START (1 << 27)
74 #define S5PCSIS_INTMSK_FRAME_END (1 << 26)
75 #define S5PCSIS_INTMSK_ERR_SOT_HS (1 << 12)
76 #define S5PCSIS_INTMSK_ERR_LOST_FS (1 << 5)
77 #define S5PCSIS_INTMSK_ERR_LOST_FE (1 << 4)
78 #define S5PCSIS_INTMSK_ERR_OVER (1 << 3)
79 #define S5PCSIS_INTMSK_ERR_ECC (1 << 2)
80 #define S5PCSIS_INTMSK_ERR_CRC (1 << 1)
81 #define S5PCSIS_INTMSK_ERR_UNKNOWN (1 << 0)
82 #define S5PCSIS_INTMSK_EXYNOS4_EN_ALL 0xf000103f
83 #define S5PCSIS_INTMSK_EXYNOS5_EN_ALL 0xfc00103f
84
85 /* Interrupt source */
86 #define S5PCSIS_INTSRC 0x14
87 #define S5PCSIS_INTSRC_EVEN_BEFORE (1 << 31)
88 #define S5PCSIS_INTSRC_EVEN_AFTER (1 << 30)
89 #define S5PCSIS_INTSRC_EVEN (0x3 << 30)
90 #define S5PCSIS_INTSRC_ODD_BEFORE (1 << 29)
91 #define S5PCSIS_INTSRC_ODD_AFTER (1 << 28)
92 #define S5PCSIS_INTSRC_ODD (0x3 << 28)
93 #define S5PCSIS_INTSRC_NON_IMAGE_DATA (0xff << 28)
94 #define S5PCSIS_INTSRC_FRAME_START (1 << 27)
95 #define S5PCSIS_INTSRC_FRAME_END (1 << 26)
96 #define S5PCSIS_INTSRC_ERR_SOT_HS (0xf << 12)
97 #define S5PCSIS_INTSRC_ERR_LOST_FS (1 << 5)
98 #define S5PCSIS_INTSRC_ERR_LOST_FE (1 << 4)
99 #define S5PCSIS_INTSRC_ERR_OVER (1 << 3)
100 #define S5PCSIS_INTSRC_ERR_ECC (1 << 2)
101 #define S5PCSIS_INTSRC_ERR_CRC (1 << 1)
102 #define S5PCSIS_INTSRC_ERR_UNKNOWN (1 << 0)
103 #define S5PCSIS_INTSRC_ERRORS 0xf03f
104
105 /* Pixel resolution */
106 #define S5PCSIS_RESOL 0x2c
107 #define CSIS_MAX_PIX_WIDTH 0xffff
108 #define CSIS_MAX_PIX_HEIGHT 0xffff
109
110 /* Non-image packet data buffers */
111 #define S5PCSIS_PKTDATA_ODD 0x2000
112 #define S5PCSIS_PKTDATA_EVEN 0x3000
113 #define S5PCSIS_PKTDATA_SIZE SZ_4K
114
115 enum {
116 CSIS_CLK_MUX,
117 CSIS_CLK_GATE,
118 };
119
120 static char *csi_clock_name[] = {
121 [CSIS_CLK_MUX] = "sclk_csis",
122 [CSIS_CLK_GATE] = "csis",
123 };
124 #define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name)
125 #define DEFAULT_SCLK_CSIS_FREQ 166000000UL
126
127 static const char * const csis_supply_name[] = {
128 "vddcore", /* CSIS Core (1.0V, 1.1V or 1.2V) suppply */
129 "vddio", /* CSIS I/O and PLL (1.8V) supply */
130 };
131 #define CSIS_NUM_SUPPLIES ARRAY_SIZE(csis_supply_name)
132
133 enum {
134 ST_POWERED = 1,
135 ST_STREAMING = 2,
136 ST_SUSPENDED = 4,
137 };
138
139 struct s5pcsis_event {
140 u32 mask;
141 const char * const name;
142 unsigned int counter;
143 };
144
145 static const struct s5pcsis_event s5pcsis_events[] = {
146 /* Errors */
147 { S5PCSIS_INTSRC_ERR_SOT_HS, "SOT Error" },
148 { S5PCSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error" },
149 { S5PCSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error" },
150 { S5PCSIS_INTSRC_ERR_OVER, "FIFO Overflow Error" },
151 { S5PCSIS_INTSRC_ERR_ECC, "ECC Error" },
152 { S5PCSIS_INTSRC_ERR_CRC, "CRC Error" },
153 { S5PCSIS_INTSRC_ERR_UNKNOWN, "Unknown Error" },
154 /* Non-image data receive events */
155 { S5PCSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame" },
156 { S5PCSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame" },
157 { S5PCSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame" },
158 { S5PCSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame" },
159 /* Frame start/end */
160 { S5PCSIS_INTSRC_FRAME_START, "Frame Start" },
161 { S5PCSIS_INTSRC_FRAME_END, "Frame End" },
162 };
163 #define S5PCSIS_NUM_EVENTS ARRAY_SIZE(s5pcsis_events)
164
165 struct csis_pktbuf {
166 u32 *data;
167 unsigned int len;
168 };
169
170 struct csis_drvdata {
171 /* Mask of all used interrupts in S5PCSIS_INTMSK register */
172 u32 interrupt_mask;
173 };
174
175 /**
176 * struct csis_state - the driver's internal state data structure
177 * @lock: mutex serializing the subdev and power management operations,
178 * protecting @format and @flags members
179 * @pads: CSIS pads array
180 * @sd: v4l2_subdev associated with CSIS device instance
181 * @index: the hardware instance index
182 * @pdev: CSIS platform device
183 * @regs: mmaped I/O registers memory
184 * @supplies: CSIS regulator supplies
185 * @clock: CSIS clocks
186 * @irq: requested s5p-mipi-csis irq number
187 * @interrupt_mask: interrupt mask of the all used interrupts
188 * @flags: the state variable for power and streaming control
189 * @clock_frequency: device bus clock frequency
190 * @hs_settle: HS-RX settle time
191 * @num_lanes: number of MIPI-CSI data lanes used
192 * @max_num_lanes: maximum number of MIPI-CSI data lanes supported
193 * @wclk_ext: CSI wrapper clock: 0 - bus clock, 1 - external SCLK_CAM
194 * @csis_fmt: current CSIS pixel format
195 * @format: common media bus format for the source and sink pad
196 * @slock: spinlock protecting structure members below
197 * @pkt_buf: the frame embedded (non-image) data buffer
198 * @events: MIPI-CSIS event (error) counters
199 */
200 struct csis_state {
201 struct mutex lock;
202 struct media_pad pads[CSIS_PADS_NUM];
203 struct v4l2_subdev sd;
204 u8 index;
205 struct platform_device *pdev;
206 void __iomem *regs;
207 struct regulator_bulk_data supplies[CSIS_NUM_SUPPLIES];
208 struct clk *clock[NUM_CSIS_CLOCKS];
209 int irq;
210 u32 interrupt_mask;
211 u32 flags;
212
213 u32 clk_frequency;
214 u32 hs_settle;
215 u32 num_lanes;
216 u32 max_num_lanes;
217 u8 wclk_ext;
218
219 const struct csis_pix_format *csis_fmt;
220 struct v4l2_mbus_framefmt format;
221
222 spinlock_t slock;
223 struct csis_pktbuf pkt_buf;
224 struct s5pcsis_event events[S5PCSIS_NUM_EVENTS];
225 };
226
227 /**
228 * struct csis_pix_format - CSIS pixel format description
229 * @pix_width_alignment: horizontal pixel alignment, width will be
230 * multiple of 2^pix_width_alignment
231 * @code: corresponding media bus code
232 * @fmt_reg: S5PCSIS_CONFIG register value
233 * @data_alignment: MIPI-CSI data alignment in bits
234 */
235 struct csis_pix_format {
236 unsigned int pix_width_alignment;
237 enum v4l2_mbus_pixelcode code;
238 u32 fmt_reg;
239 u8 data_alignment;
240 };
241
242 static const struct csis_pix_format s5pcsis_formats[] = {
243 {
244 .code = V4L2_MBUS_FMT_VYUY8_2X8,
245 .fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT,
246 .data_alignment = 32,
247 }, {
248 .code = V4L2_MBUS_FMT_JPEG_1X8,
249 .fmt_reg = S5PCSIS_CFG_FMT_USER(1),
250 .data_alignment = 32,
251 }, {
252 .code = V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8,
253 .fmt_reg = S5PCSIS_CFG_FMT_USER(1),
254 .data_alignment = 32,
255 }, {
256 .code = V4L2_MBUS_FMT_SGRBG8_1X8,
257 .fmt_reg = S5PCSIS_CFG_FMT_RAW8,
258 .data_alignment = 24,
259 }, {
260 .code = V4L2_MBUS_FMT_SGRBG10_1X10,
261 .fmt_reg = S5PCSIS_CFG_FMT_RAW10,
262 .data_alignment = 24,
263 }, {
264 .code = V4L2_MBUS_FMT_SGRBG12_1X12,
265 .fmt_reg = S5PCSIS_CFG_FMT_RAW12,
266 .data_alignment = 24,
267 }
268 };
269
270 #define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r)
271 #define s5pcsis_read(__csis, __r) readl(__csis->regs + __r)
272
273 static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev)
274 {
275 return container_of(sdev, struct csis_state, sd);
276 }
277
278 static const struct csis_pix_format *find_csis_format(
279 struct v4l2_mbus_framefmt *mf)
280 {
281 int i;
282
283 for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++)
284 if (mf->code == s5pcsis_formats[i].code)
285 return &s5pcsis_formats[i];
286 return NULL;
287 }
288
289 static void s5pcsis_enable_interrupts(struct csis_state *state, bool on)
290 {
291 u32 val = s5pcsis_read(state, S5PCSIS_INTMSK);
292 if (on)
293 val |= state->interrupt_mask;
294 else
295 val &= ~state->interrupt_mask;
296 s5pcsis_write(state, S5PCSIS_INTMSK, val);
297 }
298
299 static void s5pcsis_reset(struct csis_state *state)
300 {
301 u32 val = s5pcsis_read(state, S5PCSIS_CTRL);
302
303 s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET);
304 udelay(10);
305 }
306
307 static void s5pcsis_system_enable(struct csis_state *state, int on)
308 {
309 u32 val, mask;
310
311 val = s5pcsis_read(state, S5PCSIS_CTRL);
312 if (on)
313 val |= S5PCSIS_CTRL_ENABLE;
314 else
315 val &= ~S5PCSIS_CTRL_ENABLE;
316 s5pcsis_write(state, S5PCSIS_CTRL, val);
317
318 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
319 val &= ~S5PCSIS_DPHYCTRL_ENABLE;
320 if (on) {
321 mask = (1 << (state->num_lanes + 1)) - 1;
322 val |= (mask & S5PCSIS_DPHYCTRL_ENABLE);
323 }
324 s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
325 }
326
327 /* Called with the state.lock mutex held */
328 static void __s5pcsis_set_format(struct csis_state *state)
329 {
330 struct v4l2_mbus_framefmt *mf = &state->format;
331 u32 val;
332
333 v4l2_dbg(1, debug, &state->sd, "fmt: %#x, %d x %d\n",
334 mf->code, mf->width, mf->height);
335
336 /* Color format */
337 val = s5pcsis_read(state, S5PCSIS_CONFIG);
338 val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg;
339 s5pcsis_write(state, S5PCSIS_CONFIG, val);
340
341 /* Pixel resolution */
342 val = (mf->width << 16) | mf->height;
343 s5pcsis_write(state, S5PCSIS_RESOL, val);
344 }
345
346 static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle)
347 {
348 u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
349
350 val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27);
351 s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
352 }
353
354 static void s5pcsis_set_params(struct csis_state *state)
355 {
356 u32 val;
357
358 val = s5pcsis_read(state, S5PCSIS_CONFIG);
359 val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (state->num_lanes - 1);
360 s5pcsis_write(state, S5PCSIS_CONFIG, val);
361
362 __s5pcsis_set_format(state);
363 s5pcsis_set_hsync_settle(state, state->hs_settle);
364
365 val = s5pcsis_read(state, S5PCSIS_CTRL);
366 if (state->csis_fmt->data_alignment == 32)
367 val |= S5PCSIS_CTRL_ALIGN_32BIT;
368 else /* 24-bits */
369 val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
370
371 val &= ~S5PCSIS_CTRL_WCLK_EXTCLK;
372 if (state->wclk_ext)
373 val |= S5PCSIS_CTRL_WCLK_EXTCLK;
374 s5pcsis_write(state, S5PCSIS_CTRL, val);
375
376 /* Update the shadow register. */
377 val = s5pcsis_read(state, S5PCSIS_CTRL);
378 s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW);
379 }
380
381 static void s5pcsis_clk_put(struct csis_state *state)
382 {
383 int i;
384
385 for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
386 if (IS_ERR(state->clock[i]))
387 continue;
388 clk_unprepare(state->clock[i]);
389 clk_put(state->clock[i]);
390 state->clock[i] = ERR_PTR(-EINVAL);
391 }
392 }
393
394 static int s5pcsis_clk_get(struct csis_state *state)
395 {
396 struct device *dev = &state->pdev->dev;
397 int i, ret;
398
399 for (i = 0; i < NUM_CSIS_CLOCKS; i++)
400 state->clock[i] = ERR_PTR(-EINVAL);
401
402 for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
403 state->clock[i] = clk_get(dev, csi_clock_name[i]);
404 if (IS_ERR(state->clock[i])) {
405 ret = PTR_ERR(state->clock[i]);
406 goto err;
407 }
408 ret = clk_prepare(state->clock[i]);
409 if (ret < 0) {
410 clk_put(state->clock[i]);
411 state->clock[i] = ERR_PTR(-EINVAL);
412 goto err;
413 }
414 }
415 return 0;
416 err:
417 s5pcsis_clk_put(state);
418 dev_err(dev, "failed to get clock: %s\n", csi_clock_name[i]);
419 return ret;
420 }
421
422 static void dump_regs(struct csis_state *state, const char *label)
423 {
424 struct {
425 u32 offset;
426 const char * const name;
427 } registers[] = {
428 { 0x00, "CTRL" },
429 { 0x04, "DPHYCTRL" },
430 { 0x08, "CONFIG" },
431 { 0x0c, "DPHYSTS" },
432 { 0x10, "INTMSK" },
433 { 0x2c, "RESOL" },
434 { 0x38, "SDW_CONFIG" },
435 };
436 u32 i;
437
438 v4l2_info(&state->sd, "--- %s ---\n", label);
439
440 for (i = 0; i < ARRAY_SIZE(registers); i++) {
441 u32 cfg = s5pcsis_read(state, registers[i].offset);
442 v4l2_info(&state->sd, "%10s: 0x%08x\n", registers[i].name, cfg);
443 }
444 }
445
446 static void s5pcsis_start_stream(struct csis_state *state)
447 {
448 s5pcsis_reset(state);
449 s5pcsis_set_params(state);
450 s5pcsis_system_enable(state, true);
451 s5pcsis_enable_interrupts(state, true);
452 }
453
454 static void s5pcsis_stop_stream(struct csis_state *state)
455 {
456 s5pcsis_enable_interrupts(state, false);
457 s5pcsis_system_enable(state, false);
458 }
459
460 static void s5pcsis_clear_counters(struct csis_state *state)
461 {
462 unsigned long flags;
463 int i;
464
465 spin_lock_irqsave(&state->slock, flags);
466 for (i = 0; i < S5PCSIS_NUM_EVENTS; i++)
467 state->events[i].counter = 0;
468 spin_unlock_irqrestore(&state->slock, flags);
469 }
470
471 static void s5pcsis_log_counters(struct csis_state *state, bool non_errors)
472 {
473 int i = non_errors ? S5PCSIS_NUM_EVENTS : S5PCSIS_NUM_EVENTS - 4;
474 unsigned long flags;
475
476 spin_lock_irqsave(&state->slock, flags);
477
478 for (i--; i >= 0; i--) {
479 if (state->events[i].counter > 0 || debug)
480 v4l2_info(&state->sd, "%s events: %d\n",
481 state->events[i].name,
482 state->events[i].counter);
483 }
484 spin_unlock_irqrestore(&state->slock, flags);
485 }
486
487 /*
488 * V4L2 subdev operations
489 */
490 static int s5pcsis_s_power(struct v4l2_subdev *sd, int on)
491 {
492 struct csis_state *state = sd_to_csis_state(sd);
493 struct device *dev = &state->pdev->dev;
494
495 if (on)
496 return pm_runtime_get_sync(dev);
497
498 return pm_runtime_put_sync(dev);
499 }
500
501 static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable)
502 {
503 struct csis_state *state = sd_to_csis_state(sd);
504 int ret = 0;
505
506 v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n",
507 __func__, enable, state->flags);
508
509 if (enable) {
510 s5pcsis_clear_counters(state);
511 ret = pm_runtime_get_sync(&state->pdev->dev);
512 if (ret && ret != 1)
513 return ret;
514 }
515
516 mutex_lock(&state->lock);
517 if (enable) {
518 if (state->flags & ST_SUSPENDED) {
519 ret = -EBUSY;
520 goto unlock;
521 }
522 s5pcsis_start_stream(state);
523 state->flags |= ST_STREAMING;
524 } else {
525 s5pcsis_stop_stream(state);
526 state->flags &= ~ST_STREAMING;
527 if (debug > 0)
528 s5pcsis_log_counters(state, true);
529 }
530 unlock:
531 mutex_unlock(&state->lock);
532 if (!enable)
533 pm_runtime_put(&state->pdev->dev);
534
535 return ret == 1 ? 0 : ret;
536 }
537
538 static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd,
539 struct v4l2_subdev_fh *fh,
540 struct v4l2_subdev_mbus_code_enum *code)
541 {
542 if (code->index >= ARRAY_SIZE(s5pcsis_formats))
543 return -EINVAL;
544
545 code->code = s5pcsis_formats[code->index].code;
546 return 0;
547 }
548
549 static struct csis_pix_format const *s5pcsis_try_format(
550 struct v4l2_mbus_framefmt *mf)
551 {
552 struct csis_pix_format const *csis_fmt;
553
554 csis_fmt = find_csis_format(mf);
555 if (csis_fmt == NULL)
556 csis_fmt = &s5pcsis_formats[0];
557
558 mf->code = csis_fmt->code;
559 v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH,
560 csis_fmt->pix_width_alignment,
561 &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1,
562 0);
563 return csis_fmt;
564 }
565
566 static struct v4l2_mbus_framefmt *__s5pcsis_get_format(
567 struct csis_state *state, struct v4l2_subdev_fh *fh,
568 enum v4l2_subdev_format_whence which)
569 {
570 if (which == V4L2_SUBDEV_FORMAT_TRY)
571 return fh ? v4l2_subdev_get_try_format(fh, 0) : NULL;
572
573 return &state->format;
574 }
575
576 static int s5pcsis_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
577 struct v4l2_subdev_format *fmt)
578 {
579 struct csis_state *state = sd_to_csis_state(sd);
580 struct csis_pix_format const *csis_fmt;
581 struct v4l2_mbus_framefmt *mf;
582
583 mf = __s5pcsis_get_format(state, fh, fmt->which);
584
585 if (fmt->pad == CSIS_PAD_SOURCE) {
586 if (mf) {
587 mutex_lock(&state->lock);
588 fmt->format = *mf;
589 mutex_unlock(&state->lock);
590 }
591 return 0;
592 }
593 csis_fmt = s5pcsis_try_format(&fmt->format);
594 if (mf) {
595 mutex_lock(&state->lock);
596 *mf = fmt->format;
597 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
598 state->csis_fmt = csis_fmt;
599 mutex_unlock(&state->lock);
600 }
601 return 0;
602 }
603
604 static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
605 struct v4l2_subdev_format *fmt)
606 {
607 struct csis_state *state = sd_to_csis_state(sd);
608 struct v4l2_mbus_framefmt *mf;
609
610 mf = __s5pcsis_get_format(state, fh, fmt->which);
611 if (!mf)
612 return -EINVAL;
613
614 mutex_lock(&state->lock);
615 fmt->format = *mf;
616 mutex_unlock(&state->lock);
617 return 0;
618 }
619
620 static int s5pcsis_s_rx_buffer(struct v4l2_subdev *sd, void *buf,
621 unsigned int *size)
622 {
623 struct csis_state *state = sd_to_csis_state(sd);
624 unsigned long flags;
625
626 *size = min_t(unsigned int, *size, S5PCSIS_PKTDATA_SIZE);
627
628 spin_lock_irqsave(&state->slock, flags);
629 state->pkt_buf.data = buf;
630 state->pkt_buf.len = *size;
631 spin_unlock_irqrestore(&state->slock, flags);
632
633 return 0;
634 }
635
636 static int s5pcsis_log_status(struct v4l2_subdev *sd)
637 {
638 struct csis_state *state = sd_to_csis_state(sd);
639
640 mutex_lock(&state->lock);
641 s5pcsis_log_counters(state, true);
642 if (debug && (state->flags & ST_POWERED))
643 dump_regs(state, __func__);
644 mutex_unlock(&state->lock);
645 return 0;
646 }
647
648 static int s5pcsis_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
649 {
650 struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(fh, 0);
651
652 format->colorspace = V4L2_COLORSPACE_JPEG;
653 format->code = s5pcsis_formats[0].code;
654 format->width = S5PCSIS_DEF_PIX_WIDTH;
655 format->height = S5PCSIS_DEF_PIX_HEIGHT;
656 format->field = V4L2_FIELD_NONE;
657
658 return 0;
659 }
660
661 static const struct v4l2_subdev_internal_ops s5pcsis_sd_internal_ops = {
662 .open = s5pcsis_open,
663 };
664
665 static struct v4l2_subdev_core_ops s5pcsis_core_ops = {
666 .s_power = s5pcsis_s_power,
667 .log_status = s5pcsis_log_status,
668 };
669
670 static struct v4l2_subdev_pad_ops s5pcsis_pad_ops = {
671 .enum_mbus_code = s5pcsis_enum_mbus_code,
672 .get_fmt = s5pcsis_get_fmt,
673 .set_fmt = s5pcsis_set_fmt,
674 };
675
676 static struct v4l2_subdev_video_ops s5pcsis_video_ops = {
677 .s_rx_buffer = s5pcsis_s_rx_buffer,
678 .s_stream = s5pcsis_s_stream,
679 };
680
681 static struct v4l2_subdev_ops s5pcsis_subdev_ops = {
682 .core = &s5pcsis_core_ops,
683 .pad = &s5pcsis_pad_ops,
684 .video = &s5pcsis_video_ops,
685 };
686
687 static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id)
688 {
689 struct csis_state *state = dev_id;
690 struct csis_pktbuf *pktbuf = &state->pkt_buf;
691 unsigned long flags;
692 u32 status;
693
694 status = s5pcsis_read(state, S5PCSIS_INTSRC);
695 spin_lock_irqsave(&state->slock, flags);
696
697 if ((status & S5PCSIS_INTSRC_NON_IMAGE_DATA) && pktbuf->data) {
698 u32 offset;
699
700 if (status & S5PCSIS_INTSRC_EVEN)
701 offset = S5PCSIS_PKTDATA_EVEN;
702 else
703 offset = S5PCSIS_PKTDATA_ODD;
704
705 memcpy(pktbuf->data, state->regs + offset, pktbuf->len);
706 pktbuf->data = NULL;
707 rmb();
708 }
709
710 /* Update the event/error counters */
711 if ((status & S5PCSIS_INTSRC_ERRORS) || debug) {
712 int i;
713 for (i = 0; i < S5PCSIS_NUM_EVENTS; i++) {
714 if (!(status & state->events[i].mask))
715 continue;
716 state->events[i].counter++;
717 v4l2_dbg(2, debug, &state->sd, "%s: %d\n",
718 state->events[i].name,
719 state->events[i].counter);
720 }
721 v4l2_dbg(2, debug, &state->sd, "status: %08x\n", status);
722 }
723 spin_unlock_irqrestore(&state->slock, flags);
724
725 s5pcsis_write(state, S5PCSIS_INTSRC, status);
726 return IRQ_HANDLED;
727 }
728
729 static int s5pcsis_get_platform_data(struct platform_device *pdev,
730 struct csis_state *state)
731 {
732 struct s5p_platform_mipi_csis *pdata = pdev->dev.platform_data;
733
734 if (pdata == NULL) {
735 dev_err(&pdev->dev, "Platform data not specified\n");
736 return -EINVAL;
737 }
738
739 state->clk_frequency = pdata->clk_rate;
740 state->num_lanes = pdata->lanes;
741 state->hs_settle = pdata->hs_settle;
742 state->index = max(0, pdev->id);
743 state->max_num_lanes = state->index ? CSIS1_MAX_LANES :
744 CSIS0_MAX_LANES;
745 return 0;
746 }
747
748 #ifdef CONFIG_OF
749 static int s5pcsis_parse_dt(struct platform_device *pdev,
750 struct csis_state *state)
751 {
752 struct device_node *node = pdev->dev.of_node;
753 struct v4l2_of_endpoint endpoint;
754
755 if (of_property_read_u32(node, "clock-frequency",
756 &state->clk_frequency))
757 state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
758 if (of_property_read_u32(node, "bus-width",
759 &state->max_num_lanes))
760 return -EINVAL;
761
762 node = v4l2_of_get_next_endpoint(node, NULL);
763 if (!node) {
764 dev_err(&pdev->dev, "No port node at %s\n",
765 pdev->dev.of_node->full_name);
766 return -EINVAL;
767 }
768 /* Get port node and validate MIPI-CSI channel id. */
769 v4l2_of_parse_endpoint(node, &endpoint);
770
771 state->index = endpoint.port - FIMC_INPUT_MIPI_CSI2_0;
772 if (state->index < 0 || state->index >= CSIS_MAX_ENTITIES)
773 return -ENXIO;
774
775 /* Get MIPI CSI-2 bus configration from the endpoint node. */
776 of_property_read_u32(node, "samsung,csis-hs-settle",
777 &state->hs_settle);
778 state->wclk_ext = of_property_read_bool(node,
779 "samsung,csis-wclk");
780
781 state->num_lanes = endpoint.bus.mipi_csi2.num_data_lanes;
782
783 of_node_put(node);
784 return 0;
785 }
786 #else
787 #define s5pcsis_parse_dt(pdev, state) (-ENOSYS)
788 #endif
789
790 static const struct of_device_id s5pcsis_of_match[];
791
792 static int s5pcsis_probe(struct platform_device *pdev)
793 {
794 const struct of_device_id *of_id;
795 const struct csis_drvdata *drv_data;
796 struct device *dev = &pdev->dev;
797 struct resource *mem_res;
798 struct csis_state *state;
799 int ret = -ENOMEM;
800 int i;
801
802 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
803 if (!state)
804 return -ENOMEM;
805
806 mutex_init(&state->lock);
807 spin_lock_init(&state->slock);
808 state->pdev = pdev;
809
810 if (dev->of_node) {
811 of_id = of_match_node(s5pcsis_of_match, dev->of_node);
812 if (WARN_ON(of_id == NULL))
813 return -EINVAL;
814
815 drv_data = of_id->data;
816 state->interrupt_mask = drv_data->interrupt_mask;
817
818 ret = s5pcsis_parse_dt(pdev, state);
819 } else {
820 ret = s5pcsis_get_platform_data(pdev, state);
821 }
822
823 if (ret < 0)
824 return ret;
825
826 if (state->num_lanes == 0 || state->num_lanes > state->max_num_lanes) {
827 dev_err(dev, "Unsupported number of data lanes: %d (max. %d)\n",
828 state->num_lanes, state->max_num_lanes);
829 return -EINVAL;
830 }
831
832 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
833 state->regs = devm_ioremap_resource(dev, mem_res);
834 if (IS_ERR(state->regs))
835 return PTR_ERR(state->regs);
836
837 state->irq = platform_get_irq(pdev, 0);
838 if (state->irq < 0) {
839 dev_err(dev, "Failed to get irq\n");
840 return state->irq;
841 }
842
843 for (i = 0; i < CSIS_NUM_SUPPLIES; i++)
844 state->supplies[i].supply = csis_supply_name[i];
845
846 ret = devm_regulator_bulk_get(dev, CSIS_NUM_SUPPLIES,
847 state->supplies);
848 if (ret)
849 return ret;
850
851 ret = s5pcsis_clk_get(state);
852 if (ret < 0)
853 return ret;
854
855 if (state->clk_frequency)
856 ret = clk_set_rate(state->clock[CSIS_CLK_MUX],
857 state->clk_frequency);
858 else
859 dev_WARN(dev, "No clock frequency specified!\n");
860 if (ret < 0)
861 goto e_clkput;
862
863 ret = clk_enable(state->clock[CSIS_CLK_MUX]);
864 if (ret < 0)
865 goto e_clkput;
866
867 ret = devm_request_irq(dev, state->irq, s5pcsis_irq_handler,
868 0, dev_name(dev), state);
869 if (ret) {
870 dev_err(dev, "Interrupt request failed\n");
871 goto e_clkdis;
872 }
873
874 v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops);
875 state->sd.owner = THIS_MODULE;
876 snprintf(state->sd.name, sizeof(state->sd.name), "%s.%d",
877 CSIS_SUBDEV_NAME, state->index);
878 state->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
879 state->csis_fmt = &s5pcsis_formats[0];
880
881 state->format.code = s5pcsis_formats[0].code;
882 state->format.width = S5PCSIS_DEF_PIX_WIDTH;
883 state->format.height = S5PCSIS_DEF_PIX_HEIGHT;
884
885 state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
886 state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
887 ret = media_entity_init(&state->sd.entity,
888 CSIS_PADS_NUM, state->pads, 0);
889 if (ret < 0)
890 goto e_clkdis;
891
892 /* This allows to retrieve the platform device id by the host driver */
893 v4l2_set_subdevdata(&state->sd, pdev);
894
895 /* .. and a pointer to the subdev. */
896 platform_set_drvdata(pdev, &state->sd);
897 memcpy(state->events, s5pcsis_events, sizeof(state->events));
898 pm_runtime_enable(dev);
899
900 dev_info(&pdev->dev, "lanes: %d, hs_settle: %d, wclk: %d, freq: %u\n",
901 state->num_lanes, state->hs_settle, state->wclk_ext,
902 state->clk_frequency);
903 return 0;
904
905 e_clkdis:
906 clk_disable(state->clock[CSIS_CLK_MUX]);
907 e_clkput:
908 s5pcsis_clk_put(state);
909 return ret;
910 }
911
912 static int s5pcsis_pm_suspend(struct device *dev, bool runtime)
913 {
914 struct platform_device *pdev = to_platform_device(dev);
915 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
916 struct csis_state *state = sd_to_csis_state(sd);
917 int ret = 0;
918
919 v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
920 __func__, state->flags);
921
922 mutex_lock(&state->lock);
923 if (state->flags & ST_POWERED) {
924 s5pcsis_stop_stream(state);
925 ret = s5p_csis_phy_enable(state->index, false);
926 if (ret)
927 goto unlock;
928 ret = regulator_bulk_disable(CSIS_NUM_SUPPLIES,
929 state->supplies);
930 if (ret)
931 goto unlock;
932 clk_disable(state->clock[CSIS_CLK_GATE]);
933 state->flags &= ~ST_POWERED;
934 if (!runtime)
935 state->flags |= ST_SUSPENDED;
936 }
937 unlock:
938 mutex_unlock(&state->lock);
939 return ret ? -EAGAIN : 0;
940 }
941
942 static int s5pcsis_pm_resume(struct device *dev, bool runtime)
943 {
944 struct platform_device *pdev = to_platform_device(dev);
945 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
946 struct csis_state *state = sd_to_csis_state(sd);
947 int ret = 0;
948
949 v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
950 __func__, state->flags);
951
952 mutex_lock(&state->lock);
953 if (!runtime && !(state->flags & ST_SUSPENDED))
954 goto unlock;
955
956 if (!(state->flags & ST_POWERED)) {
957 ret = regulator_bulk_enable(CSIS_NUM_SUPPLIES,
958 state->supplies);
959 if (ret)
960 goto unlock;
961 ret = s5p_csis_phy_enable(state->index, true);
962 if (!ret) {
963 state->flags |= ST_POWERED;
964 } else {
965 regulator_bulk_disable(CSIS_NUM_SUPPLIES,
966 state->supplies);
967 goto unlock;
968 }
969 clk_enable(state->clock[CSIS_CLK_GATE]);
970 }
971 if (state->flags & ST_STREAMING)
972 s5pcsis_start_stream(state);
973
974 state->flags &= ~ST_SUSPENDED;
975 unlock:
976 mutex_unlock(&state->lock);
977 return ret ? -EAGAIN : 0;
978 }
979
980 #ifdef CONFIG_PM_SLEEP
981 static int s5pcsis_suspend(struct device *dev)
982 {
983 return s5pcsis_pm_suspend(dev, false);
984 }
985
986 static int s5pcsis_resume(struct device *dev)
987 {
988 return s5pcsis_pm_resume(dev, false);
989 }
990 #endif
991
992 #ifdef CONFIG_PM_RUNTIME
993 static int s5pcsis_runtime_suspend(struct device *dev)
994 {
995 return s5pcsis_pm_suspend(dev, true);
996 }
997
998 static int s5pcsis_runtime_resume(struct device *dev)
999 {
1000 return s5pcsis_pm_resume(dev, true);
1001 }
1002 #endif
1003
1004 static int s5pcsis_remove(struct platform_device *pdev)
1005 {
1006 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
1007 struct csis_state *state = sd_to_csis_state(sd);
1008
1009 pm_runtime_disable(&pdev->dev);
1010 s5pcsis_pm_suspend(&pdev->dev, false);
1011 clk_disable(state->clock[CSIS_CLK_MUX]);
1012 pm_runtime_set_suspended(&pdev->dev);
1013 s5pcsis_clk_put(state);
1014
1015 media_entity_cleanup(&state->sd.entity);
1016
1017 return 0;
1018 }
1019
1020 static const struct dev_pm_ops s5pcsis_pm_ops = {
1021 SET_RUNTIME_PM_OPS(s5pcsis_runtime_suspend, s5pcsis_runtime_resume,
1022 NULL)
1023 SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_suspend, s5pcsis_resume)
1024 };
1025
1026 static const struct csis_drvdata exynos4_csis_drvdata = {
1027 .interrupt_mask = S5PCSIS_INTMSK_EXYNOS4_EN_ALL,
1028 };
1029
1030 static const struct csis_drvdata exynos5_csis_drvdata = {
1031 .interrupt_mask = S5PCSIS_INTMSK_EXYNOS5_EN_ALL,
1032 };
1033
1034 static const struct of_device_id s5pcsis_of_match[] = {
1035 {
1036 .compatible = "samsung,s5pv210-csis",
1037 .data = &exynos4_csis_drvdata,
1038 }, {
1039 .compatible = "samsung,exynos4210-csis",
1040 .data = &exynos4_csis_drvdata,
1041 }, {
1042 .compatible = "samsung,exynos5250-csis",
1043 .data = &exynos5_csis_drvdata,
1044 },
1045 { /* sentinel */ },
1046 };
1047 MODULE_DEVICE_TABLE(of, s5pcsis_of_match);
1048
1049 static struct platform_driver s5pcsis_driver = {
1050 .probe = s5pcsis_probe,
1051 .remove = s5pcsis_remove,
1052 .driver = {
1053 .of_match_table = s5pcsis_of_match,
1054 .name = CSIS_DRIVER_NAME,
1055 .owner = THIS_MODULE,
1056 .pm = &s5pcsis_pm_ops,
1057 },
1058 };
1059
1060 module_platform_driver(s5pcsis_driver);
1061
1062 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1063 MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI-CSI2 receiver driver");
1064 MODULE_LICENSE("GPL");
Linux with added FPC-III support