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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / media / platform / s5p-mfc / s5p_mfc.c
blobbb0c1e6016e2ec571df6d98c8d1061aa6f61f15f
1 /*
2 * Samsung S5P Multi Format Codec v 5.1
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
24 #include <linux/of.h>
25 #include <media/videobuf2-core.h>
26 #include "s5p_mfc_common.h"
27 #include "s5p_mfc_ctrl.h"
28 #include "s5p_mfc_debug.h"
29 #include "s5p_mfc_dec.h"
30 #include "s5p_mfc_enc.h"
31 #include "s5p_mfc_intr.h"
32 #include "s5p_mfc_opr.h"
33 #include "s5p_mfc_cmd.h"
34 #include "s5p_mfc_pm.h"
35
36 #define S5P_MFC_NAME "s5p-mfc"
37 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
38 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
39
40 int debug;
41 module_param(debug, int, S_IRUGO | S_IWUSR);
42 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
43
44 /* Helper functions for interrupt processing */
45
46 /* Remove from hw execution round robin */
47 void clear_work_bit(struct s5p_mfc_ctx *ctx)
48 {
49 struct s5p_mfc_dev *dev = ctx->dev;
50
51 spin_lock(&dev->condlock);
52 __clear_bit(ctx->num, &dev->ctx_work_bits);
53 spin_unlock(&dev->condlock);
54 }
55
56 /* Add to hw execution round robin */
57 void set_work_bit(struct s5p_mfc_ctx *ctx)
58 {
59 struct s5p_mfc_dev *dev = ctx->dev;
60
61 spin_lock(&dev->condlock);
62 __set_bit(ctx->num, &dev->ctx_work_bits);
63 spin_unlock(&dev->condlock);
64 }
65
66 /* Remove from hw execution round robin */
67 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
68 {
69 struct s5p_mfc_dev *dev = ctx->dev;
70 unsigned long flags;
71
72 spin_lock_irqsave(&dev->condlock, flags);
73 __clear_bit(ctx->num, &dev->ctx_work_bits);
74 spin_unlock_irqrestore(&dev->condlock, flags);
75 }
76
77 /* Add to hw execution round robin */
78 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
79 {
80 struct s5p_mfc_dev *dev = ctx->dev;
81 unsigned long flags;
82
83 spin_lock_irqsave(&dev->condlock, flags);
84 __set_bit(ctx->num, &dev->ctx_work_bits);
85 spin_unlock_irqrestore(&dev->condlock, flags);
86 }
87
88 /* Wake up context wait_queue */
89 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
90 unsigned int err)
91 {
92 ctx->int_cond = 1;
93 ctx->int_type = reason;
94 ctx->int_err = err;
95 wake_up(&ctx->queue);
96 }
97
98 /* Wake up device wait_queue */
99 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
100 unsigned int err)
101 {
102 dev->int_cond = 1;
103 dev->int_type = reason;
104 dev->int_err = err;
105 wake_up(&dev->queue);
106 }
107
108 static void s5p_mfc_watchdog(unsigned long arg)
109 {
110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
111
112 if (test_bit(0, &dev->hw_lock))
113 atomic_inc(&dev->watchdog_cnt);
114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
115 /* This means that hw is busy and no interrupts were
116 * generated by hw for the Nth time of running this
117 * watchdog timer. This usually means a serious hw
118 * error. Now it is time to kill all instances and
119 * reset the MFC. */
120 mfc_err("Time out during waiting for HW\n");
121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
122 }
123 dev->watchdog_timer.expires = jiffies +
124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
125 add_timer(&dev->watchdog_timer);
126 }
127
128 static void s5p_mfc_watchdog_worker(struct work_struct *work)
129 {
130 struct s5p_mfc_dev *dev;
131 struct s5p_mfc_ctx *ctx;
132 unsigned long flags;
133 int mutex_locked;
134 int i, ret;
135
136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
137
138 mfc_err("Driver timeout error handling\n");
139 /* Lock the mutex that protects open and release.
140 * This is necessary as they may load and unload firmware. */
141 mutex_locked = mutex_trylock(&dev->mfc_mutex);
142 if (!mutex_locked)
143 mfc_err("Error: some instance may be closing/opening\n");
144 spin_lock_irqsave(&dev->irqlock, flags);
145
146 s5p_mfc_clock_off();
147
148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
149 ctx = dev->ctx[i];
150 if (!ctx)
151 continue;
152 ctx->state = MFCINST_ERROR;
153 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
154 &ctx->vq_dst);
155 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
156 &ctx->vq_src);
157 clear_work_bit(ctx);
158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
159 }
160 clear_bit(0, &dev->hw_lock);
161 spin_unlock_irqrestore(&dev->irqlock, flags);
162 /* Double check if there is at least one instance running.
163 * If no instance is in memory than no firmware should be present */
164 if (dev->num_inst > 0) {
165 ret = s5p_mfc_reload_firmware(dev);
166 if (ret) {
167 mfc_err("Failed to reload FW\n");
168 goto unlock;
169 }
170 s5p_mfc_clock_on();
171 ret = s5p_mfc_init_hw(dev);
172 if (ret)
173 mfc_err("Failed to reinit FW\n");
174 }
175 unlock:
176 if (mutex_locked)
177 mutex_unlock(&dev->mfc_mutex);
178 }
179
180 static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev)
181 {
182 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
183 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
184 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
185 }
186
187 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
188 {
189 struct s5p_mfc_buf *dst_buf;
190 struct s5p_mfc_dev *dev = ctx->dev;
191
192 ctx->state = MFCINST_FINISHED;
193 ctx->sequence++;
194 while (!list_empty(&ctx->dst_queue)) {
195 dst_buf = list_entry(ctx->dst_queue.next,
196 struct s5p_mfc_buf, list);
197 mfc_debug(2, "Cleaning up buffer: %d\n",
198 dst_buf->b->v4l2_buf.index);
199 vb2_set_plane_payload(dst_buf->b, 0, 0);
200 vb2_set_plane_payload(dst_buf->b, 1, 0);
201 list_del(&dst_buf->list);
202 ctx->dst_queue_cnt--;
203 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
204
205 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
206 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
207 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
208 else
209 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
210
211 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index);
212 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE);
213 }
214 }
215
216 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
217 {
218 struct s5p_mfc_dev *dev = ctx->dev;
219 struct s5p_mfc_buf *dst_buf, *src_buf;
220 size_t dec_y_addr;
221 unsigned int frame_type;
222
223 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
224 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
225
226 /* Copy timestamp / timecode from decoded src to dst and set
227 appropraite flags */
228 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
229 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
230 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
231 dst_buf->b->v4l2_buf.timecode =
232 src_buf->b->v4l2_buf.timecode;
233 dst_buf->b->v4l2_buf.timestamp =
234 src_buf->b->v4l2_buf.timestamp;
235 switch (frame_type) {
236 case S5P_FIMV_DECODE_FRAME_I_FRAME:
237 dst_buf->b->v4l2_buf.flags |=
238 V4L2_BUF_FLAG_KEYFRAME;
239 break;
240 case S5P_FIMV_DECODE_FRAME_P_FRAME:
241 dst_buf->b->v4l2_buf.flags |=
242 V4L2_BUF_FLAG_PFRAME;
243 break;
244 case S5P_FIMV_DECODE_FRAME_B_FRAME:
245 dst_buf->b->v4l2_buf.flags |=
246 V4L2_BUF_FLAG_BFRAME;
247 break;
248 }
249 break;
250 }
251 }
252 }
253
254 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
255 {
256 struct s5p_mfc_dev *dev = ctx->dev;
257 struct s5p_mfc_buf *dst_buf;
258 size_t dspl_y_addr;
259 unsigned int frame_type;
260
261 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
262 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_disp_frame_type, ctx);
263
264 /* If frame is same as previous then skip and do not dequeue */
265 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
266 if (!ctx->after_packed_pb)
267 ctx->sequence++;
268 ctx->after_packed_pb = 0;
269 return;
270 }
271 ctx->sequence++;
272 /* The MFC returns address of the buffer, now we have to
273 * check which videobuf does it correspond to */
274 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
275 /* Check if this is the buffer we're looking for */
276 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) {
277 list_del(&dst_buf->list);
278 ctx->dst_queue_cnt--;
279 dst_buf->b->v4l2_buf.sequence = ctx->sequence;
280 if (s5p_mfc_hw_call(dev->mfc_ops,
281 get_pic_type_top, ctx) ==
282 s5p_mfc_hw_call(dev->mfc_ops,
283 get_pic_type_bot, ctx))
284 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
285 else
286 dst_buf->b->v4l2_buf.field =
287 V4L2_FIELD_INTERLACED;
288 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size);
289 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size);
290 clear_bit(dst_buf->b->v4l2_buf.index,
291 &ctx->dec_dst_flag);
292
293 vb2_buffer_done(dst_buf->b,
294 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
295
296 break;
297 }
298 }
299 }
300
301 /* Handle frame decoding interrupt */
302 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
303 unsigned int reason, unsigned int err)
304 {
305 struct s5p_mfc_dev *dev = ctx->dev;
306 unsigned int dst_frame_status;
307 struct s5p_mfc_buf *src_buf;
308 unsigned long flags;
309 unsigned int res_change;
310
311 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
312 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
313 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
314 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
315 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
316 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
317 if (ctx->state == MFCINST_RES_CHANGE_INIT)
318 ctx->state = MFCINST_RES_CHANGE_FLUSH;
319 if (res_change == S5P_FIMV_RES_INCREASE ||
320 res_change == S5P_FIMV_RES_DECREASE) {
321 ctx->state = MFCINST_RES_CHANGE_INIT;
322 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
323 wake_up_ctx(ctx, reason, err);
324 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
325 BUG();
326 s5p_mfc_clock_off();
327 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
328 return;
329 }
330 if (ctx->dpb_flush_flag)
331 ctx->dpb_flush_flag = 0;
332
333 spin_lock_irqsave(&dev->irqlock, flags);
334 /* All frames remaining in the buffer have been extracted */
335 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
336 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
337 s5p_mfc_handle_frame_all_extracted(ctx);
338 ctx->state = MFCINST_RES_CHANGE_END;
339 goto leave_handle_frame;
340 } else {
341 s5p_mfc_handle_frame_all_extracted(ctx);
342 }
343 }
344
345 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY ||
346 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY)
347 s5p_mfc_handle_frame_copy_time(ctx);
348
349 /* A frame has been decoded and is in the buffer */
350 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
351 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
352 s5p_mfc_handle_frame_new(ctx, err);
353 } else {
354 mfc_debug(2, "No frame decode\n");
355 }
356 /* Mark source buffer as complete */
357 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
358 && !list_empty(&ctx->src_queue)) {
359 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
360 list);
361 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
362 get_consumed_stream, dev);
363 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
364 ctx->consumed_stream + STUFF_BYTE <
365 src_buf->b->v4l2_planes[0].bytesused) {
366 /* Run MFC again on the same buffer */
367 mfc_debug(2, "Running again the same buffer\n");
368 ctx->after_packed_pb = 1;
369 } else {
370 mfc_debug(2, "MFC needs next buffer\n");
371 ctx->consumed_stream = 0;
372 if (src_buf->flags & MFC_BUF_FLAG_EOS)
373 ctx->state = MFCINST_FINISHING;
374 list_del(&src_buf->list);
375 ctx->src_queue_cnt--;
376 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
377 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR);
378 else
379 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE);
380 }
381 }
382 leave_handle_frame:
383 spin_unlock_irqrestore(&dev->irqlock, flags);
384 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
385 || ctx->dst_queue_cnt < ctx->pb_count)
386 clear_work_bit(ctx);
387 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
388 wake_up_ctx(ctx, reason, err);
389 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
390 BUG();
391 s5p_mfc_clock_off();
392 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
393 }
394
395 /* Error handling for interrupt */
396 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
397 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
398 {
399 unsigned long flags;
400
401 mfc_err("Interrupt Error: %08x\n", err);
402
403 if (ctx != NULL) {
404 /* Error recovery is dependent on the state of context */
405 switch (ctx->state) {
406 case MFCINST_RES_CHANGE_INIT:
407 case MFCINST_RES_CHANGE_FLUSH:
408 case MFCINST_RES_CHANGE_END:
409 case MFCINST_FINISHING:
410 case MFCINST_FINISHED:
411 case MFCINST_RUNNING:
412 /* It is higly probable that an error occured
413 * while decoding a frame */
414 clear_work_bit(ctx);
415 ctx->state = MFCINST_ERROR;
416 /* Mark all dst buffers as having an error */
417 spin_lock_irqsave(&dev->irqlock, flags);
418 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue,
419 &ctx->dst_queue, &ctx->vq_dst);
420 /* Mark all src buffers as having an error */
421 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue,
422 &ctx->src_queue, &ctx->vq_src);
423 spin_unlock_irqrestore(&dev->irqlock, flags);
424 wake_up_ctx(ctx, reason, err);
425 break;
426 default:
427 clear_work_bit(ctx);
428 ctx->state = MFCINST_ERROR;
429 wake_up_ctx(ctx, reason, err);
430 break;
431 }
432 }
433 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
434 BUG();
435 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
436 s5p_mfc_clock_off();
437 wake_up_dev(dev, reason, err);
438 return;
439 }
440
441 /* Header parsing interrupt handling */
442 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
443 unsigned int reason, unsigned int err)
444 {
445 struct s5p_mfc_dev *dev;
446
447 if (ctx == NULL)
448 return;
449 dev = ctx->dev;
450 if (ctx->c_ops->post_seq_start) {
451 if (ctx->c_ops->post_seq_start(ctx))
452 mfc_err("post_seq_start() failed\n");
453 } else {
454 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
455 dev);
456 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
457 dev);
458
459 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
460
461 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
462 dev);
463 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
464 dev);
465 if (ctx->img_width == 0 || ctx->img_height == 0)
466 ctx->state = MFCINST_ERROR;
467 else
468 ctx->state = MFCINST_HEAD_PARSED;
469
470 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
471 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
472 !list_empty(&ctx->src_queue)) {
473 struct s5p_mfc_buf *src_buf;
474 src_buf = list_entry(ctx->src_queue.next,
475 struct s5p_mfc_buf, list);
476 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
477 dev) <
478 src_buf->b->v4l2_planes[0].bytesused)
479 ctx->head_processed = 0;
480 else
481 ctx->head_processed = 1;
482 } else {
483 ctx->head_processed = 1;
484 }
485 }
486 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
487 clear_work_bit(ctx);
488 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
489 BUG();
490 s5p_mfc_clock_off();
491 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
492 wake_up_ctx(ctx, reason, err);
493 }
494
495 /* Header parsing interrupt handling */
496 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
497 unsigned int reason, unsigned int err)
498 {
499 struct s5p_mfc_buf *src_buf;
500 struct s5p_mfc_dev *dev;
501 unsigned long flags;
502
503 if (ctx == NULL)
504 return;
505 dev = ctx->dev;
506 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
507 ctx->int_type = reason;
508 ctx->int_err = err;
509 ctx->int_cond = 1;
510 clear_work_bit(ctx);
511 if (err == 0) {
512 ctx->state = MFCINST_RUNNING;
513 if (!ctx->dpb_flush_flag && ctx->head_processed) {
514 spin_lock_irqsave(&dev->irqlock, flags);
515 if (!list_empty(&ctx->src_queue)) {
516 src_buf = list_entry(ctx->src_queue.next,
517 struct s5p_mfc_buf, list);
518 list_del(&src_buf->list);
519 ctx->src_queue_cnt--;
520 vb2_buffer_done(src_buf->b,
521 VB2_BUF_STATE_DONE);
522 }
523 spin_unlock_irqrestore(&dev->irqlock, flags);
524 } else {
525 ctx->dpb_flush_flag = 0;
526 }
527 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
528 BUG();
529
530 s5p_mfc_clock_off();
531
532 wake_up(&ctx->queue);
533 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
534 } else {
535 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
536 BUG();
537
538 s5p_mfc_clock_off();
539
540 wake_up(&ctx->queue);
541 }
542 }
543
544 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx,
545 unsigned int reason, unsigned int err)
546 {
547 struct s5p_mfc_dev *dev = ctx->dev;
548 struct s5p_mfc_buf *mb_entry;
549
550 mfc_debug(2, "Stream completed\n");
551
552 s5p_mfc_clear_int_flags(dev);
553 ctx->int_type = reason;
554 ctx->int_err = err;
555 ctx->state = MFCINST_FINISHED;
556
557 spin_lock(&dev->irqlock);
558 if (!list_empty(&ctx->dst_queue)) {
559 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
560 list);
561 list_del(&mb_entry->list);
562 ctx->dst_queue_cnt--;
563 vb2_set_plane_payload(mb_entry->b, 0, 0);
564 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
565 }
566 spin_unlock(&dev->irqlock);
567
568 clear_work_bit(ctx);
569
570 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
571
572 s5p_mfc_clock_off();
573 wake_up(&ctx->queue);
574 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
575 }
576
577 /* Interrupt processing */
578 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
579 {
580 struct s5p_mfc_dev *dev = priv;
581 struct s5p_mfc_ctx *ctx;
582 unsigned int reason;
583 unsigned int err;
584
585 mfc_debug_enter();
586 /* Reset the timeout watchdog */
587 atomic_set(&dev->watchdog_cnt, 0);
588 ctx = dev->ctx[dev->curr_ctx];
589 /* Get the reason of interrupt and the error code */
590 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
591 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
592 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
593 switch (reason) {
594 case S5P_MFC_R2H_CMD_ERR_RET:
595 /* An error has occured */
596 if (ctx->state == MFCINST_RUNNING &&
597 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
598 dev->warn_start)
599 s5p_mfc_handle_frame(ctx, reason, err);
600 else
601 s5p_mfc_handle_error(dev, ctx, reason, err);
602 clear_bit(0, &dev->enter_suspend);
603 break;
604
605 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
606 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
607 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
608 if (ctx->c_ops->post_frame_start) {
609 if (ctx->c_ops->post_frame_start(ctx))
610 mfc_err("post_frame_start() failed\n");
611 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
612 wake_up_ctx(ctx, reason, err);
613 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
614 BUG();
615 s5p_mfc_clock_off();
616 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
617 } else {
618 s5p_mfc_handle_frame(ctx, reason, err);
619 }
620 break;
621
622 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
623 s5p_mfc_handle_seq_done(ctx, reason, err);
624 break;
625
626 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
627 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
628 ctx->state = MFCINST_GOT_INST;
629 clear_work_bit(ctx);
630 wake_up(&ctx->queue);
631 goto irq_cleanup_hw;
632
633 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
634 clear_work_bit(ctx);
635 ctx->state = MFCINST_FREE;
636 wake_up(&ctx->queue);
637 goto irq_cleanup_hw;
638
639 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
640 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
641 case S5P_MFC_R2H_CMD_SLEEP_RET:
642 case S5P_MFC_R2H_CMD_WAKEUP_RET:
643 if (ctx)
644 clear_work_bit(ctx);
645 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
646 wake_up_dev(dev, reason, err);
647 clear_bit(0, &dev->hw_lock);
648 clear_bit(0, &dev->enter_suspend);
649 break;
650
651 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
652 s5p_mfc_handle_init_buffers(ctx, reason, err);
653 break;
654
655 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
656 s5p_mfc_handle_stream_complete(ctx, reason, err);
657 break;
658
659 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
660 clear_work_bit(ctx);
661 ctx->state = MFCINST_RUNNING;
662 wake_up(&ctx->queue);
663 goto irq_cleanup_hw;
664
665 default:
666 mfc_debug(2, "Unknown int reason\n");
667 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
668 }
669 mfc_debug_leave();
670 return IRQ_HANDLED;
671 irq_cleanup_hw:
672 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
673 ctx->int_type = reason;
674 ctx->int_err = err;
675 ctx->int_cond = 1;
676 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
677 mfc_err("Failed to unlock hw\n");
678
679 s5p_mfc_clock_off();
680
681 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
682 mfc_debug(2, "Exit via irq_cleanup_hw\n");
683 return IRQ_HANDLED;
684 }
685
686 /* Open an MFC node */
687 static int s5p_mfc_open(struct file *file)
688 {
689 struct video_device *vdev = video_devdata(file);
690 struct s5p_mfc_dev *dev = video_drvdata(file);
691 struct s5p_mfc_ctx *ctx = NULL;
692 struct vb2_queue *q;
693 int ret = 0;
694
695 mfc_debug_enter();
696 if (mutex_lock_interruptible(&dev->mfc_mutex))
697 return -ERESTARTSYS;
698 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
699 /* Allocate memory for context */
700 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
701 if (!ctx) {
702 mfc_err("Not enough memory\n");
703 ret = -ENOMEM;
704 goto err_alloc;
705 }
706 v4l2_fh_init(&ctx->fh, video_devdata(file));
707 file->private_data = &ctx->fh;
708 v4l2_fh_add(&ctx->fh);
709 ctx->dev = dev;
710 INIT_LIST_HEAD(&ctx->src_queue);
711 INIT_LIST_HEAD(&ctx->dst_queue);
712 ctx->src_queue_cnt = 0;
713 ctx->dst_queue_cnt = 0;
714 /* Get context number */
715 ctx->num = 0;
716 while (dev->ctx[ctx->num]) {
717 ctx->num++;
718 if (ctx->num >= MFC_NUM_CONTEXTS) {
719 mfc_err("Too many open contexts\n");
720 ret = -EBUSY;
721 goto err_no_ctx;
722 }
723 }
724 /* Mark context as idle */
725 clear_work_bit_irqsave(ctx);
726 dev->ctx[ctx->num] = ctx;
727 if (vdev == dev->vfd_dec) {
728 ctx->type = MFCINST_DECODER;
729 ctx->c_ops = get_dec_codec_ops();
730 s5p_mfc_dec_init(ctx);
731 /* Setup ctrl handler */
732 ret = s5p_mfc_dec_ctrls_setup(ctx);
733 if (ret) {
734 mfc_err("Failed to setup mfc controls\n");
735 goto err_ctrls_setup;
736 }
737 } else if (vdev == dev->vfd_enc) {
738 ctx->type = MFCINST_ENCODER;
739 ctx->c_ops = get_enc_codec_ops();
740 /* only for encoder */
741 INIT_LIST_HEAD(&ctx->ref_queue);
742 ctx->ref_queue_cnt = 0;
743 s5p_mfc_enc_init(ctx);
744 /* Setup ctrl handler */
745 ret = s5p_mfc_enc_ctrls_setup(ctx);
746 if (ret) {
747 mfc_err("Failed to setup mfc controls\n");
748 goto err_ctrls_setup;
749 }
750 } else {
751 ret = -ENOENT;
752 goto err_bad_node;
753 }
754 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
755 ctx->inst_no = -1;
756 /* Load firmware if this is the first instance */
757 if (dev->num_inst == 1) {
758 dev->watchdog_timer.expires = jiffies +
759 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
760 add_timer(&dev->watchdog_timer);
761 ret = s5p_mfc_power_on();
762 if (ret < 0) {
763 mfc_err("power on failed\n");
764 goto err_pwr_enable;
765 }
766 s5p_mfc_clock_on();
767 ret = s5p_mfc_load_firmware(dev);
768 if (ret) {
769 s5p_mfc_clock_off();
770 goto err_load_fw;
771 }
772 /* Init the FW */
773 ret = s5p_mfc_init_hw(dev);
774 s5p_mfc_clock_off();
775 if (ret)
776 goto err_init_hw;
777 }
778 /* Init videobuf2 queue for CAPTURE */
779 q = &ctx->vq_dst;
780 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
781 q->drv_priv = &ctx->fh;
782 if (vdev == dev->vfd_dec) {
783 q->io_modes = VB2_MMAP;
784 q->ops = get_dec_queue_ops();
785 } else if (vdev == dev->vfd_enc) {
786 q->io_modes = VB2_MMAP | VB2_USERPTR;
787 q->ops = get_enc_queue_ops();
788 } else {
789 ret = -ENOENT;
790 goto err_queue_init;
791 }
792 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
793 q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
794 ret = vb2_queue_init(q);
795 if (ret) {
796 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
797 goto err_queue_init;
798 }
799 /* Init videobuf2 queue for OUTPUT */
800 q = &ctx->vq_src;
801 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
802 q->io_modes = VB2_MMAP;
803 q->drv_priv = &ctx->fh;
804 if (vdev == dev->vfd_dec) {
805 q->io_modes = VB2_MMAP;
806 q->ops = get_dec_queue_ops();
807 } else if (vdev == dev->vfd_enc) {
808 q->io_modes = VB2_MMAP | VB2_USERPTR;
809 q->ops = get_enc_queue_ops();
810 } else {
811 ret = -ENOENT;
812 goto err_queue_init;
813 }
814 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
815 q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
816 ret = vb2_queue_init(q);
817 if (ret) {
818 mfc_err("Failed to initialize videobuf2 queue(output)\n");
819 goto err_queue_init;
820 }
821 init_waitqueue_head(&ctx->queue);
822 mutex_unlock(&dev->mfc_mutex);
823 mfc_debug_leave();
824 return ret;
825 /* Deinit when failure occured */
826 err_queue_init:
827 if (dev->num_inst == 1)
828 s5p_mfc_deinit_hw(dev);
829 err_init_hw:
830 err_load_fw:
831 err_pwr_enable:
832 if (dev->num_inst == 1) {
833 if (s5p_mfc_power_off() < 0)
834 mfc_err("power off failed\n");
835 del_timer_sync(&dev->watchdog_timer);
836 }
837 err_ctrls_setup:
838 s5p_mfc_dec_ctrls_delete(ctx);
839 err_bad_node:
840 dev->ctx[ctx->num] = NULL;
841 err_no_ctx:
842 v4l2_fh_del(&ctx->fh);
843 v4l2_fh_exit(&ctx->fh);
844 kfree(ctx);
845 err_alloc:
846 dev->num_inst--;
847 mutex_unlock(&dev->mfc_mutex);
848 mfc_debug_leave();
849 return ret;
850 }
851
852 /* Release MFC context */
853 static int s5p_mfc_release(struct file *file)
854 {
855 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
856 struct s5p_mfc_dev *dev = ctx->dev;
857
858 mfc_debug_enter();
859 mutex_lock(&dev->mfc_mutex);
860 s5p_mfc_clock_on();
861 vb2_queue_release(&ctx->vq_src);
862 vb2_queue_release(&ctx->vq_dst);
863 /* Mark context as idle */
864 clear_work_bit_irqsave(ctx);
865 /* If instance was initialised then
866 * return instance and free reosurces */
867 if (ctx->inst_no != MFC_NO_INSTANCE_SET) {
868 mfc_debug(2, "Has to free instance\n");
869 ctx->state = MFCINST_RETURN_INST;
870 set_work_bit_irqsave(ctx);
871 s5p_mfc_clean_ctx_int_flags(ctx);
872 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
873 /* Wait until instance is returned or timeout occured */
874 if (s5p_mfc_wait_for_done_ctx
875 (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) {
876 s5p_mfc_clock_off();
877 mfc_err("Err returning instance\n");
878 }
879 mfc_debug(2, "After free instance\n");
880 /* Free resources */
881 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx);
882 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
883 if (ctx->type == MFCINST_DECODER)
884 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer,
885 ctx);
886
887 ctx->inst_no = MFC_NO_INSTANCE_SET;
888 }
889 /* hardware locking scheme */
890 if (dev->curr_ctx == ctx->num)
891 clear_bit(0, &dev->hw_lock);
892 dev->num_inst--;
893 if (dev->num_inst == 0) {
894 mfc_debug(2, "Last instance\n");
895 s5p_mfc_deinit_hw(dev);
896 del_timer_sync(&dev->watchdog_timer);
897 if (s5p_mfc_power_off() < 0)
898 mfc_err("Power off failed\n");
899 }
900 mfc_debug(2, "Shutting down clock\n");
901 s5p_mfc_clock_off();
902 dev->ctx[ctx->num] = NULL;
903 s5p_mfc_dec_ctrls_delete(ctx);
904 v4l2_fh_del(&ctx->fh);
905 v4l2_fh_exit(&ctx->fh);
906 kfree(ctx);
907 mfc_debug_leave();
908 mutex_unlock(&dev->mfc_mutex);
909 return 0;
910 }
911
912 /* Poll */
913 static unsigned int s5p_mfc_poll(struct file *file,
914 struct poll_table_struct *wait)
915 {
916 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
917 struct s5p_mfc_dev *dev = ctx->dev;
918 struct vb2_queue *src_q, *dst_q;
919 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
920 unsigned int rc = 0;
921 unsigned long flags;
922
923 mutex_lock(&dev->mfc_mutex);
924 src_q = &ctx->vq_src;
925 dst_q = &ctx->vq_dst;
926 /*
927 * There has to be at least one buffer queued on each queued_list, which
928 * means either in driver already or waiting for driver to claim it
929 * and start processing.
930 */
931 if ((!src_q->streaming || list_empty(&src_q->queued_list))
932 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
933 rc = POLLERR;
934 goto end;
935 }
936 mutex_unlock(&dev->mfc_mutex);
937 poll_wait(file, &ctx->fh.wait, wait);
938 poll_wait(file, &src_q->done_wq, wait);
939 poll_wait(file, &dst_q->done_wq, wait);
940 mutex_lock(&dev->mfc_mutex);
941 if (v4l2_event_pending(&ctx->fh))
942 rc |= POLLPRI;
943 spin_lock_irqsave(&src_q->done_lock, flags);
944 if (!list_empty(&src_q->done_list))
945 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
946 done_entry);
947 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
948 || src_vb->state == VB2_BUF_STATE_ERROR))
949 rc |= POLLOUT | POLLWRNORM;
950 spin_unlock_irqrestore(&src_q->done_lock, flags);
951 spin_lock_irqsave(&dst_q->done_lock, flags);
952 if (!list_empty(&dst_q->done_list))
953 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
954 done_entry);
955 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
956 || dst_vb->state == VB2_BUF_STATE_ERROR))
957 rc |= POLLIN | POLLRDNORM;
958 spin_unlock_irqrestore(&dst_q->done_lock, flags);
959 end:
960 mutex_unlock(&dev->mfc_mutex);
961 return rc;
962 }
963
964 /* Mmap */
965 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
966 {
967 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
968 struct s5p_mfc_dev *dev = ctx->dev;
969 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
970 int ret;
971
972 if (mutex_lock_interruptible(&dev->mfc_mutex))
973 return -ERESTARTSYS;
974 if (offset < DST_QUEUE_OFF_BASE) {
975 mfc_debug(2, "mmaping source\n");
976 ret = vb2_mmap(&ctx->vq_src, vma);
977 } else { /* capture */
978 mfc_debug(2, "mmaping destination\n");
979 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
980 ret = vb2_mmap(&ctx->vq_dst, vma);
981 }
982 mutex_unlock(&dev->mfc_mutex);
983 return ret;
984 }
985
986 /* v4l2 ops */
987 static const struct v4l2_file_operations s5p_mfc_fops = {
988 .owner = THIS_MODULE,
989 .open = s5p_mfc_open,
990 .release = s5p_mfc_release,
991 .poll = s5p_mfc_poll,
992 .unlocked_ioctl = video_ioctl2,
993 .mmap = s5p_mfc_mmap,
994 };
995
996 static int match_child(struct device *dev, void *data)
997 {
998 if (!dev_name(dev))
999 return 0;
1000 return !strcmp(dev_name(dev), (char *)data);
1001 }
1002
1003 static void s5p_mfc_memdev_release(struct device *dev)
1004 {
1005 dma_release_declared_memory(dev);
1006 }
1007
1008 static void *mfc_get_drv_data(struct platform_device *pdev);
1009
1010 static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev)
1011 {
1012 unsigned int mem_info[2] = { };
1013
1014 dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev,
1015 sizeof(struct device), GFP_KERNEL);
1016 if (!dev->mem_dev_l) {
1017 mfc_err("Not enough memory\n");
1018 return -ENOMEM;
1019 }
1020
1021 dev_set_name(dev->mem_dev_l, "%s", "s5p-mfc-l");
1022 dev->mem_dev_l->release = s5p_mfc_memdev_release;
1023 device_initialize(dev->mem_dev_l);
1024 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1025 "samsung,mfc-l", mem_info, 2);
1026 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0],
1027 mem_info[0], mem_info[1],
1028 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1029 mfc_err("Failed to declare coherent memory for\n"
1030 "MFC device\n");
1031 return -ENOMEM;
1032 }
1033
1034 dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev,
1035 sizeof(struct device), GFP_KERNEL);
1036 if (!dev->mem_dev_r) {
1037 mfc_err("Not enough memory\n");
1038 return -ENOMEM;
1039 }
1040
1041 dev_set_name(dev->mem_dev_r, "%s", "s5p-mfc-r");
1042 dev->mem_dev_r->release = s5p_mfc_memdev_release;
1043 device_initialize(dev->mem_dev_r);
1044 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1045 "samsung,mfc-r", mem_info, 2);
1046 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0],
1047 mem_info[0], mem_info[1],
1048 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1049 pr_err("Failed to declare coherent memory for\n"
1050 "MFC device\n");
1051 return -ENOMEM;
1052 }
1053 return 0;
1054 }
1055
1056 /* MFC probe function */
1057 static int s5p_mfc_probe(struct platform_device *pdev)
1058 {
1059 struct s5p_mfc_dev *dev;
1060 struct video_device *vfd;
1061 struct resource *res;
1062 int ret;
1063
1064 pr_debug("%s++\n", __func__);
1065 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1066 if (!dev) {
1067 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1068 return -ENOMEM;
1069 }
1070
1071 spin_lock_init(&dev->irqlock);
1072 spin_lock_init(&dev->condlock);
1073 dev->plat_dev = pdev;
1074 if (!dev->plat_dev) {
1075 dev_err(&pdev->dev, "No platform data specified\n");
1076 return -ENODEV;
1077 }
1078
1079 dev->variant = mfc_get_drv_data(pdev);
1080
1081 ret = s5p_mfc_init_pm(dev);
1082 if (ret < 0) {
1083 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1084 return ret;
1085 }
1086
1087 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1088
1089 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1090 if (IS_ERR(dev->regs_base))
1091 return PTR_ERR(dev->regs_base);
1092
1093 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1094 if (res == NULL) {
1095 dev_err(&pdev->dev, "failed to get irq resource\n");
1096 ret = -ENOENT;
1097 goto err_res;
1098 }
1099 dev->irq = res->start;
1100 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1101 IRQF_DISABLED, pdev->name, dev);
1102 if (ret) {
1103 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1104 goto err_res;
1105 }
1106
1107 if (pdev->dev.of_node) {
1108 ret = s5p_mfc_alloc_memdevs(dev);
1109 if (ret < 0)
1110 goto err_res;
1111 } else {
1112 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev,
1113 "s5p-mfc-l", match_child);
1114 if (!dev->mem_dev_l) {
1115 mfc_err("Mem child (L) device get failed\n");
1116 ret = -ENODEV;
1117 goto err_res;
1118 }
1119 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev,
1120 "s5p-mfc-r", match_child);
1121 if (!dev->mem_dev_r) {
1122 mfc_err("Mem child (R) device get failed\n");
1123 ret = -ENODEV;
1124 goto err_res;
1125 }
1126 }
1127
1128 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
1129 if (IS_ERR(dev->alloc_ctx[0])) {
1130 ret = PTR_ERR(dev->alloc_ctx[0]);
1131 goto err_res;
1132 }
1133 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
1134 if (IS_ERR(dev->alloc_ctx[1])) {
1135 ret = PTR_ERR(dev->alloc_ctx[1]);
1136 goto err_mem_init_ctx_1;
1137 }
1138
1139 mutex_init(&dev->mfc_mutex);
1140
1141 ret = s5p_mfc_alloc_firmware(dev);
1142 if (ret)
1143 goto err_alloc_fw;
1144
1145 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1146 if (ret)
1147 goto err_v4l2_dev_reg;
1148 init_waitqueue_head(&dev->queue);
1149
1150 /* decoder */
1151 vfd = video_device_alloc();
1152 if (!vfd) {
1153 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1154 ret = -ENOMEM;
1155 goto err_dec_alloc;
1156 }
1157 vfd->fops = &s5p_mfc_fops,
1158 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1159 vfd->release = video_device_release,
1160 vfd->lock = &dev->mfc_mutex;
1161 vfd->v4l2_dev = &dev->v4l2_dev;
1162 vfd->vfl_dir = VFL_DIR_M2M;
1163 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1164 dev->vfd_dec = vfd;
1165 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1166 if (ret) {
1167 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1168 video_device_release(vfd);
1169 goto err_dec_reg;
1170 }
1171 v4l2_info(&dev->v4l2_dev,
1172 "decoder registered as /dev/video%d\n", vfd->num);
1173 video_set_drvdata(vfd, dev);
1174
1175 /* encoder */
1176 vfd = video_device_alloc();
1177 if (!vfd) {
1178 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1179 ret = -ENOMEM;
1180 goto err_enc_alloc;
1181 }
1182 vfd->fops = &s5p_mfc_fops,
1183 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1184 vfd->release = video_device_release,
1185 vfd->lock = &dev->mfc_mutex;
1186 vfd->v4l2_dev = &dev->v4l2_dev;
1187 vfd->vfl_dir = VFL_DIR_M2M;
1188 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1189 dev->vfd_enc = vfd;
1190 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1191 if (ret) {
1192 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1193 video_device_release(vfd);
1194 goto err_enc_reg;
1195 }
1196 v4l2_info(&dev->v4l2_dev,
1197 "encoder registered as /dev/video%d\n", vfd->num);
1198 video_set_drvdata(vfd, dev);
1199 platform_set_drvdata(pdev, dev);
1200
1201 dev->hw_lock = 0;
1202 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1203 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1204 atomic_set(&dev->watchdog_cnt, 0);
1205 init_timer(&dev->watchdog_timer);
1206 dev->watchdog_timer.data = (unsigned long)dev;
1207 dev->watchdog_timer.function = s5p_mfc_watchdog;
1208
1209 /* Initialize HW ops and commands based on MFC version */
1210 s5p_mfc_init_hw_ops(dev);
1211 s5p_mfc_init_hw_cmds(dev);
1212
1213 pr_debug("%s--\n", __func__);
1214 return 0;
1215
1216 /* Deinit MFC if probe had failed */
1217 err_enc_reg:
1218 video_device_release(dev->vfd_enc);
1219 err_enc_alloc:
1220 video_unregister_device(dev->vfd_dec);
1221 err_dec_reg:
1222 video_device_release(dev->vfd_dec);
1223 err_dec_alloc:
1224 v4l2_device_unregister(&dev->v4l2_dev);
1225 err_v4l2_dev_reg:
1226 s5p_mfc_release_firmware(dev);
1227 err_alloc_fw:
1228 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1229 err_mem_init_ctx_1:
1230 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1231 err_res:
1232 s5p_mfc_final_pm(dev);
1233
1234 pr_debug("%s-- with error\n", __func__);
1235 return ret;
1236
1237 }
1238
1239 /* Remove the driver */
1240 static int s5p_mfc_remove(struct platform_device *pdev)
1241 {
1242 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1243
1244 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1245
1246 del_timer_sync(&dev->watchdog_timer);
1247 flush_workqueue(dev->watchdog_workqueue);
1248 destroy_workqueue(dev->watchdog_workqueue);
1249
1250 video_unregister_device(dev->vfd_enc);
1251 video_unregister_device(dev->vfd_dec);
1252 v4l2_device_unregister(&dev->v4l2_dev);
1253 s5p_mfc_release_firmware(dev);
1254 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1255 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1256 if (pdev->dev.of_node) {
1257 put_device(dev->mem_dev_l);
1258 put_device(dev->mem_dev_r);
1259 }
1260
1261 s5p_mfc_final_pm(dev);
1262 return 0;
1263 }
1264
1265 #ifdef CONFIG_PM_SLEEP
1266
1267 static int s5p_mfc_suspend(struct device *dev)
1268 {
1269 struct platform_device *pdev = to_platform_device(dev);
1270 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1271 int ret;
1272
1273 if (m_dev->num_inst == 0)
1274 return 0;
1275
1276 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1277 mfc_err("Error: going to suspend for a second time\n");
1278 return -EIO;
1279 }
1280
1281 /* Check if we're processing then wait if it necessary. */
1282 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1283 /* Try and lock the HW */
1284 /* Wait on the interrupt waitqueue */
1285 ret = wait_event_interruptible_timeout(m_dev->queue,
1286 m_dev->int_cond || m_dev->ctx[m_dev->curr_ctx]->int_cond,
1287 msecs_to_jiffies(MFC_INT_TIMEOUT));
1288
1289 if (ret == 0) {
1290 mfc_err("Waiting for hardware to finish timed out\n");
1291 return -EIO;
1292 }
1293 }
1294
1295 return s5p_mfc_sleep(m_dev);
1296 }
1297
1298 static int s5p_mfc_resume(struct device *dev)
1299 {
1300 struct platform_device *pdev = to_platform_device(dev);
1301 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1302
1303 if (m_dev->num_inst == 0)
1304 return 0;
1305 return s5p_mfc_wakeup(m_dev);
1306 }
1307 #endif
1308
1309 #ifdef CONFIG_PM_RUNTIME
1310 static int s5p_mfc_runtime_suspend(struct device *dev)
1311 {
1312 struct platform_device *pdev = to_platform_device(dev);
1313 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1314
1315 atomic_set(&m_dev->pm.power, 0);
1316 return 0;
1317 }
1318
1319 static int s5p_mfc_runtime_resume(struct device *dev)
1320 {
1321 struct platform_device *pdev = to_platform_device(dev);
1322 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1323 int pre_power;
1324
1325 if (!m_dev->alloc_ctx)
1326 return 0;
1327 pre_power = atomic_read(&m_dev->pm.power);
1328 atomic_set(&m_dev->pm.power, 1);
1329 return 0;
1330 }
1331 #endif
1332
1333 /* Power management */
1334 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1335 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1336 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1337 NULL)
1338 };
1339
1340 struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1341 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1342 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1343 .dsc = DESC_BUF_SIZE,
1344 .shm = SHARED_BUF_SIZE,
1345 };
1346
1347 struct s5p_mfc_buf_size buf_size_v5 = {
1348 .fw = MAX_FW_SIZE,
1349 .cpb = MAX_CPB_SIZE,
1350 .priv = &mfc_buf_size_v5,
1351 };
1352
1353 struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1354 .base = MFC_BASE_ALIGN_ORDER,
1355 };
1356
1357 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1358 .version = MFC_VERSION,
1359 .port_num = MFC_NUM_PORTS,
1360 .buf_size = &buf_size_v5,
1361 .buf_align = &mfc_buf_align_v5,
1362 .fw_name = "s5p-mfc.fw",
1363 };
1364
1365 struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1366 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1367 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1368 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1369 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1370 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1371 };
1372
1373 struct s5p_mfc_buf_size buf_size_v6 = {
1374 .fw = MAX_FW_SIZE_V6,
1375 .cpb = MAX_CPB_SIZE_V6,
1376 .priv = &mfc_buf_size_v6,
1377 };
1378
1379 struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1380 .base = 0,
1381 };
1382
1383 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1384 .version = MFC_VERSION_V6,
1385 .port_num = MFC_NUM_PORTS_V6,
1386 .buf_size = &buf_size_v6,
1387 .buf_align = &mfc_buf_align_v6,
1388 .fw_name = "s5p-mfc-v6.fw",
1389 };
1390
1391 struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1392 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1393 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1394 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1395 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1396 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1397 };
1398
1399 struct s5p_mfc_buf_size buf_size_v7 = {
1400 .fw = MAX_FW_SIZE_V7,
1401 .cpb = MAX_CPB_SIZE_V7,
1402 .priv = &mfc_buf_size_v7,
1403 };
1404
1405 struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1406 .base = 0,
1407 };
1408
1409 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1410 .version = MFC_VERSION_V7,
1411 .port_num = MFC_NUM_PORTS_V7,
1412 .buf_size = &buf_size_v7,
1413 .buf_align = &mfc_buf_align_v7,
1414 .fw_name = "s5p-mfc-v7.fw",
1415 };
1416
1417 static struct platform_device_id mfc_driver_ids[] = {
1418 {
1419 .name = "s5p-mfc",
1420 .driver_data = (unsigned long)&mfc_drvdata_v5,
1421 }, {
1422 .name = "s5p-mfc-v5",
1423 .driver_data = (unsigned long)&mfc_drvdata_v5,
1424 }, {
1425 .name = "s5p-mfc-v6",
1426 .driver_data = (unsigned long)&mfc_drvdata_v6,
1427 }, {
1428 .name = "s5p-mfc-v7",
1429 .driver_data = (unsigned long)&mfc_drvdata_v7,
1430 },
1431 {},
1432 };
1433 MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1434
1435 static const struct of_device_id exynos_mfc_match[] = {
1436 {
1437 .compatible = "samsung,mfc-v5",
1438 .data = &mfc_drvdata_v5,
1439 }, {
1440 .compatible = "samsung,mfc-v6",
1441 .data = &mfc_drvdata_v6,
1442 }, {
1443 .compatible = "samsung,mfc-v7",
1444 .data = &mfc_drvdata_v7,
1445 },
1446 {},
1447 };
1448 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1449
1450 static void *mfc_get_drv_data(struct platform_device *pdev)
1451 {
1452 struct s5p_mfc_variant *driver_data = NULL;
1453
1454 if (pdev->dev.of_node) {
1455 const struct of_device_id *match;
1456 match = of_match_node(exynos_mfc_match,
1457 pdev->dev.of_node);
1458 if (match)
1459 driver_data = (struct s5p_mfc_variant *)match->data;
1460 } else {
1461 driver_data = (struct s5p_mfc_variant *)
1462 platform_get_device_id(pdev)->driver_data;
1463 }
1464 return driver_data;
1465 }
1466
1467 static struct platform_driver s5p_mfc_driver = {
1468 .probe = s5p_mfc_probe,
1469 .remove = s5p_mfc_remove,
1470 .id_table = mfc_driver_ids,
1471 .driver = {
1472 .name = S5P_MFC_NAME,
1473 .owner = THIS_MODULE,
1474 .pm = &s5p_mfc_pm_ops,
1475 .of_match_table = exynos_mfc_match,
1476 },
1477 };
1478
1479 module_platform_driver(s5p_mfc_driver);
1480
1481 MODULE_LICENSE("GPL");
1482 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1483 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1484
Linux with added FPC-III support