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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / media / platform / s5p-mfc / s5p_mfc_opr_v6.c
blob461358c4a7908fa71a3b360ffb61ef2c78ce8853
1 /*
2 * drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
3 *
4 * Samsung MFC (Multi Function Codec - FIMV) driver
5 * This file contains hw related functions.
6 *
7 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
8 * http://www.samsung.com/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #undef DEBUG
16
17 #include <linux/delay.h>
18 #include <linux/mm.h>
19 #include <linux/io.h>
20 #include <linux/jiffies.h>
21 #include <linux/firmware.h>
22 #include <linux/err.h>
23 #include <linux/sched.h>
24 #include <linux/dma-mapping.h>
25
26 #include <asm/cacheflush.h>
27
28 #include "s5p_mfc_common.h"
29 #include "s5p_mfc_cmd.h"
30 #include "s5p_mfc_intr.h"
31 #include "s5p_mfc_pm.h"
32 #include "s5p_mfc_debug.h"
33 #include "s5p_mfc_opr.h"
34 #include "s5p_mfc_opr_v6.h"
35
36 /* #define S5P_MFC_DEBUG_REGWRITE */
37 #ifdef S5P_MFC_DEBUG_REGWRITE
38 #undef writel
39 #define writel(v, r) \
40 do { \
41 pr_err("MFCWRITE(%p): %08x\n", r, (unsigned int)v); \
42 __raw_writel(v, r); \
43 } while (0)
44 #endif /* S5P_MFC_DEBUG_REGWRITE */
45
46 #define READL(offset) readl(dev->regs_base + (offset))
47 #define WRITEL(data, offset) writel((data), dev->regs_base + (offset))
48 #define OFFSETA(x) (((x) - dev->port_a) >> S5P_FIMV_MEM_OFFSET)
49 #define OFFSETB(x) (((x) - dev->port_b) >> S5P_FIMV_MEM_OFFSET)
50
51 /* Allocate temporary buffers for decoding */
52 static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
53 {
54 /* NOP */
55
56 return 0;
57 }
58
59 /* Release temproary buffers for decoding */
60 static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx)
61 {
62 /* NOP */
63 }
64
65 /* Allocate codec buffers */
66 static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
67 {
68 struct s5p_mfc_dev *dev = ctx->dev;
69 unsigned int mb_width, mb_height;
70 int ret;
71
72 mb_width = MB_WIDTH(ctx->img_width);
73 mb_height = MB_HEIGHT(ctx->img_height);
74
75 if (ctx->type == MFCINST_DECODER) {
76 mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",
77 ctx->luma_size, ctx->chroma_size, ctx->mv_size);
78 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
79 } else if (ctx->type == MFCINST_ENCODER) {
80 ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
81 ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),
82 S5P_FIMV_TMV_BUFFER_ALIGN_V6);
83
84 ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
85 S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
86 S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
87 ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
88 S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
89 S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
90 ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V6(
91 ctx->img_width, ctx->img_height,
92 mb_width, mb_height),
93 S5P_FIMV_ME_BUFFER_ALIGN_V6);
94
95 mfc_debug(2, "recon luma size: %d chroma size: %d\n",
96 ctx->luma_dpb_size, ctx->chroma_dpb_size);
97 } else {
98 return -EINVAL;
99 }
100
101 /* Codecs have different memory requirements */
102 switch (ctx->codec_mode) {
103 case S5P_MFC_CODEC_H264_DEC:
104 case S5P_MFC_CODEC_H264_MVC_DEC:
105 ctx->scratch_buf_size =
106 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6(
107 mb_width,
108 mb_height);
109 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
110 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
111 ctx->bank1.size =
112 ctx->scratch_buf_size +
113 (ctx->mv_count * ctx->mv_size);
114 break;
115 case S5P_MFC_CODEC_MPEG4_DEC:
116 if (IS_MFCV7(dev)) {
117 ctx->scratch_buf_size =
118 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7(
119 mb_width,
120 mb_height);
121 } else {
122 ctx->scratch_buf_size =
123 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(
124 mb_width,
125 mb_height);
126 }
127
128 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
129 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
130 ctx->bank1.size = ctx->scratch_buf_size;
131 break;
132 case S5P_MFC_CODEC_VC1RCV_DEC:
133 case S5P_MFC_CODEC_VC1_DEC:
134 ctx->scratch_buf_size =
135 S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(
136 mb_width,
137 mb_height);
138 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
139 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
140 ctx->bank1.size = ctx->scratch_buf_size;
141 break;
142 case S5P_MFC_CODEC_MPEG2_DEC:
143 ctx->bank1.size = 0;
144 ctx->bank2.size = 0;
145 break;
146 case S5P_MFC_CODEC_H263_DEC:
147 ctx->scratch_buf_size =
148 S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(
149 mb_width,
150 mb_height);
151 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
152 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
153 ctx->bank1.size = ctx->scratch_buf_size;
154 break;
155 case S5P_MFC_CODEC_VP8_DEC:
156 ctx->scratch_buf_size =
157 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6(
158 mb_width,
159 mb_height);
160 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
161 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
162 ctx->bank1.size = ctx->scratch_buf_size;
163 break;
164 case S5P_MFC_CODEC_H264_ENC:
165 ctx->scratch_buf_size =
166 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6(
167 mb_width,
168 mb_height);
169 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
170 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
171 ctx->bank1.size =
172 ctx->scratch_buf_size + ctx->tmv_buffer_size +
173 (ctx->pb_count * (ctx->luma_dpb_size +
174 ctx->chroma_dpb_size + ctx->me_buffer_size));
175 ctx->bank2.size = 0;
176 break;
177 case S5P_MFC_CODEC_MPEG4_ENC:
178 case S5P_MFC_CODEC_H263_ENC:
179 ctx->scratch_buf_size =
180 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(
181 mb_width,
182 mb_height);
183 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
184 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
185 ctx->bank1.size =
186 ctx->scratch_buf_size + ctx->tmv_buffer_size +
187 (ctx->pb_count * (ctx->luma_dpb_size +
188 ctx->chroma_dpb_size + ctx->me_buffer_size));
189 ctx->bank2.size = 0;
190 break;
191 case S5P_MFC_CODEC_VP8_ENC:
192 ctx->scratch_buf_size =
193 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V7(
194 mb_width,
195 mb_height);
196 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
197 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
198 ctx->bank1.size =
199 ctx->scratch_buf_size + ctx->tmv_buffer_size +
200 (ctx->pb_count * (ctx->luma_dpb_size +
201 ctx->chroma_dpb_size + ctx->me_buffer_size));
202 ctx->bank2.size = 0;
203 break;
204 default:
205 break;
206 }
207
208 /* Allocate only if memory from bank 1 is necessary */
209 if (ctx->bank1.size > 0) {
210 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->bank1);
211 if (ret) {
212 mfc_err("Failed to allocate Bank1 memory\n");
213 return ret;
214 }
215 BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
216 }
217 return 0;
218 }
219
220 /* Release buffers allocated for codec */
221 static void s5p_mfc_release_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
222 {
223 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1);
224 }
225
226 /* Allocate memory for instance data buffer */
227 static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
228 {
229 struct s5p_mfc_dev *dev = ctx->dev;
230 struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
231 int ret;
232
233 mfc_debug_enter();
234
235 switch (ctx->codec_mode) {
236 case S5P_MFC_CODEC_H264_DEC:
237 case S5P_MFC_CODEC_H264_MVC_DEC:
238 ctx->ctx.size = buf_size->h264_dec_ctx;
239 break;
240 case S5P_MFC_CODEC_MPEG4_DEC:
241 case S5P_MFC_CODEC_H263_DEC:
242 case S5P_MFC_CODEC_VC1RCV_DEC:
243 case S5P_MFC_CODEC_VC1_DEC:
244 case S5P_MFC_CODEC_MPEG2_DEC:
245 case S5P_MFC_CODEC_VP8_DEC:
246 ctx->ctx.size = buf_size->other_dec_ctx;
247 break;
248 case S5P_MFC_CODEC_H264_ENC:
249 ctx->ctx.size = buf_size->h264_enc_ctx;
250 break;
251 case S5P_MFC_CODEC_MPEG4_ENC:
252 case S5P_MFC_CODEC_H263_ENC:
253 case S5P_MFC_CODEC_VP8_ENC:
254 ctx->ctx.size = buf_size->other_enc_ctx;
255 break;
256 default:
257 ctx->ctx.size = 0;
258 mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode);
259 break;
260 }
261
262 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->ctx);
263 if (ret) {
264 mfc_err("Failed to allocate instance buffer\n");
265 return ret;
266 }
267
268 memset(ctx->ctx.virt, 0, ctx->ctx.size);
269 wmb();
270
271 mfc_debug_leave();
272
273 return 0;
274 }
275
276 /* Release instance buffer */
277 static void s5p_mfc_release_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
278 {
279 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->ctx);
280 }
281
282 /* Allocate context buffers for SYS_INIT */
283 static int s5p_mfc_alloc_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
284 {
285 struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
286 int ret;
287
288 mfc_debug_enter();
289
290 dev->ctx_buf.size = buf_size->dev_ctx;
291 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &dev->ctx_buf);
292 if (ret) {
293 mfc_err("Failed to allocate device context buffer\n");
294 return ret;
295 }
296
297 memset(dev->ctx_buf.virt, 0, buf_size->dev_ctx);
298 wmb();
299
300 mfc_debug_leave();
301
302 return 0;
303 }
304
305 /* Release context buffers for SYS_INIT */
306 static void s5p_mfc_release_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
307 {
308 s5p_mfc_release_priv_buf(dev->mem_dev_l, &dev->ctx_buf);
309 }
310
311 static int calc_plane(int width, int height)
312 {
313 int mbX, mbY;
314
315 mbX = DIV_ROUND_UP(width, S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
316 mbY = DIV_ROUND_UP(height, S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6);
317
318 if (width * height < S5P_FIMV_MAX_FRAME_SIZE_V6)
319 mbY = (mbY + 1) / 2 * 2;
320
321 return (mbX * S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6) *
322 (mbY * S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
323 }
324
325 static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
326 {
327 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
328 ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
329 mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"
330 "buffer dimensions: %dx%d\n", ctx->img_width,
331 ctx->img_height, ctx->buf_width, ctx->buf_height);
332
333 ctx->luma_size = calc_plane(ctx->img_width, ctx->img_height);
334 ctx->chroma_size = calc_plane(ctx->img_width, (ctx->img_height >> 1));
335 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
336 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
337 ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
338 ctx->img_height);
339 ctx->mv_size = ALIGN(ctx->mv_size, 16);
340 } else {
341 ctx->mv_size = 0;
342 }
343 }
344
345 static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx)
346 {
347 unsigned int mb_width, mb_height;
348
349 mb_width = MB_WIDTH(ctx->img_width);
350 mb_height = MB_HEIGHT(ctx->img_height);
351
352 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
353 ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256);
354 ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);
355
356 /* MFCv7 needs pad bytes for Luma and Chroma */
357 if (IS_MFCV7(ctx->dev)) {
358 ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;
359 ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V7;
360 }
361 }
362
363 /* Set registers for decoding stream buffer */
364 static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
365 int buf_addr, unsigned int start_num_byte,
366 unsigned int strm_size)
367 {
368 struct s5p_mfc_dev *dev = ctx->dev;
369 struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size;
370
371 mfc_debug_enter();
372 mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n"
373 "buf_size: 0x%08x (%d)\n",
374 ctx->inst_no, buf_addr, strm_size, strm_size);
375 WRITEL(strm_size, S5P_FIMV_D_STREAM_DATA_SIZE_V6);
376 WRITEL(buf_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V6);
377 WRITEL(buf_size->cpb, S5P_FIMV_D_CPB_BUFFER_SIZE_V6);
378 WRITEL(start_num_byte, S5P_FIMV_D_CPB_BUFFER_OFFSET_V6);
379
380 mfc_debug_leave();
381 return 0;
382 }
383
384 /* Set decoding frame buffer */
385 static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
386 {
387 unsigned int frame_size, i;
388 unsigned int frame_size_ch, frame_size_mv;
389 struct s5p_mfc_dev *dev = ctx->dev;
390 size_t buf_addr1;
391 int buf_size1;
392 int align_gap;
393
394 buf_addr1 = ctx->bank1.dma;
395 buf_size1 = ctx->bank1.size;
396
397 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
398 mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count);
399 mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay);
400
401 WRITEL(ctx->total_dpb_count, S5P_FIMV_D_NUM_DPB_V6);
402 WRITEL(ctx->luma_size, S5P_FIMV_D_LUMA_DPB_SIZE_V6);
403 WRITEL(ctx->chroma_size, S5P_FIMV_D_CHROMA_DPB_SIZE_V6);
404
405 WRITEL(buf_addr1, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6);
406 WRITEL(ctx->scratch_buf_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6);
407 buf_addr1 += ctx->scratch_buf_size;
408 buf_size1 -= ctx->scratch_buf_size;
409
410 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
411 ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC){
412 WRITEL(ctx->mv_size, S5P_FIMV_D_MV_BUFFER_SIZE_V6);
413 WRITEL(ctx->mv_count, S5P_FIMV_D_NUM_MV_V6);
414 }
415
416 frame_size = ctx->luma_size;
417 frame_size_ch = ctx->chroma_size;
418 frame_size_mv = ctx->mv_size;
419 mfc_debug(2, "Frame size: %d ch: %d mv: %d\n",
420 frame_size, frame_size_ch, frame_size_mv);
421
422 for (i = 0; i < ctx->total_dpb_count; i++) {
423 /* Bank2 */
424 mfc_debug(2, "Luma %d: %x\n", i,
425 ctx->dst_bufs[i].cookie.raw.luma);
426 WRITEL(ctx->dst_bufs[i].cookie.raw.luma,
427 S5P_FIMV_D_LUMA_DPB_V6 + i * 4);
428 mfc_debug(2, "\tChroma %d: %x\n", i,
429 ctx->dst_bufs[i].cookie.raw.chroma);
430 WRITEL(ctx->dst_bufs[i].cookie.raw.chroma,
431 S5P_FIMV_D_CHROMA_DPB_V6 + i * 4);
432 }
433 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
434 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
435 for (i = 0; i < ctx->mv_count; i++) {
436 /* To test alignment */
437 align_gap = buf_addr1;
438 buf_addr1 = ALIGN(buf_addr1, 16);
439 align_gap = buf_addr1 - align_gap;
440 buf_size1 -= align_gap;
441
442 mfc_debug(2, "\tBuf1: %x, size: %d\n",
443 buf_addr1, buf_size1);
444 WRITEL(buf_addr1, S5P_FIMV_D_MV_BUFFER_V6 + i * 4);
445 buf_addr1 += frame_size_mv;
446 buf_size1 -= frame_size_mv;
447 }
448 }
449
450 mfc_debug(2, "Buf1: %u, buf_size1: %d (frames %d)\n",
451 buf_addr1, buf_size1, ctx->total_dpb_count);
452 if (buf_size1 < 0) {
453 mfc_debug(2, "Not enough memory has been allocated.\n");
454 return -ENOMEM;
455 }
456
457 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
458 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
459 S5P_FIMV_CH_INIT_BUFS_V6, NULL);
460
461 mfc_debug(2, "After setting buffers.\n");
462 return 0;
463 }
464
465 /* Set registers for encoding stream buffer */
466 static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
467 unsigned long addr, unsigned int size)
468 {
469 struct s5p_mfc_dev *dev = ctx->dev;
470
471 WRITEL(addr, S5P_FIMV_E_STREAM_BUFFER_ADDR_V6); /* 16B align */
472 WRITEL(size, S5P_FIMV_E_STREAM_BUFFER_SIZE_V6);
473
474 mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%d\n",
475 addr, size);
476
477 return 0;
478 }
479
480 static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
481 unsigned long y_addr, unsigned long c_addr)
482 {
483 struct s5p_mfc_dev *dev = ctx->dev;
484
485 if (IS_MFCV7(dev)) {
486 WRITEL(y_addr, S5P_FIMV_E_SOURCE_FIRST_ADDR_V7);
487 WRITEL(c_addr, S5P_FIMV_E_SOURCE_SECOND_ADDR_V7);
488 } else {
489 WRITEL(y_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR_V6);
490 WRITEL(c_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6);
491 }
492
493 mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr);
494 mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr);
495 }
496
497 static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
498 unsigned long *y_addr, unsigned long *c_addr)
499 {
500 struct s5p_mfc_dev *dev = ctx->dev;
501 unsigned long enc_recon_y_addr, enc_recon_c_addr;
502
503 if (IS_MFCV7(dev)) {
504 *y_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7);
505 *c_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7);
506 } else {
507 *y_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6);
508 *c_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6);
509 }
510
511 enc_recon_y_addr = READL(S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6);
512 enc_recon_c_addr = READL(S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6);
513
514 mfc_debug(2, "recon y addr: 0x%08lx\n", enc_recon_y_addr);
515 mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr);
516 }
517
518 /* Set encoding ref & codec buffer */
519 static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
520 {
521 struct s5p_mfc_dev *dev = ctx->dev;
522 size_t buf_addr1;
523 int i, buf_size1;
524
525 mfc_debug_enter();
526
527 buf_addr1 = ctx->bank1.dma;
528 buf_size1 = ctx->bank1.size;
529
530 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
531
532 for (i = 0; i < ctx->pb_count; i++) {
533 WRITEL(buf_addr1, S5P_FIMV_E_LUMA_DPB_V6 + (4 * i));
534 buf_addr1 += ctx->luma_dpb_size;
535 WRITEL(buf_addr1, S5P_FIMV_E_CHROMA_DPB_V6 + (4 * i));
536 buf_addr1 += ctx->chroma_dpb_size;
537 WRITEL(buf_addr1, S5P_FIMV_E_ME_BUFFER_V6 + (4 * i));
538 buf_addr1 += ctx->me_buffer_size;
539 buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size +
540 ctx->me_buffer_size);
541 }
542
543 WRITEL(buf_addr1, S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6);
544 WRITEL(ctx->scratch_buf_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6);
545 buf_addr1 += ctx->scratch_buf_size;
546 buf_size1 -= ctx->scratch_buf_size;
547
548 WRITEL(buf_addr1, S5P_FIMV_E_TMV_BUFFER0_V6);
549 buf_addr1 += ctx->tmv_buffer_size >> 1;
550 WRITEL(buf_addr1, S5P_FIMV_E_TMV_BUFFER1_V6);
551 buf_addr1 += ctx->tmv_buffer_size >> 1;
552 buf_size1 -= ctx->tmv_buffer_size;
553
554 mfc_debug(2, "Buf1: %u, buf_size1: %d (ref frames %d)\n",
555 buf_addr1, buf_size1, ctx->pb_count);
556 if (buf_size1 < 0) {
557 mfc_debug(2, "Not enough memory has been allocated.\n");
558 return -ENOMEM;
559 }
560
561 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
562 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
563 S5P_FIMV_CH_INIT_BUFS_V6, NULL);
564
565 mfc_debug_leave();
566
567 return 0;
568 }
569
570 static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)
571 {
572 struct s5p_mfc_dev *dev = ctx->dev;
573
574 /* multi-slice control */
575 /* multi-slice MB number or bit size */
576 WRITEL(ctx->slice_mode, S5P_FIMV_E_MSLICE_MODE_V6);
577 if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
578 WRITEL(ctx->slice_size.mb, S5P_FIMV_E_MSLICE_SIZE_MB_V6);
579 } else if (ctx->slice_mode ==
580 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
581 WRITEL(ctx->slice_size.bits, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);
582 } else {
583 WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_MB_V6);
584 WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);
585 }
586
587 return 0;
588 }
589
590 static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
591 {
592 struct s5p_mfc_dev *dev = ctx->dev;
593 struct s5p_mfc_enc_params *p = &ctx->enc_params;
594 unsigned int reg = 0;
595
596 mfc_debug_enter();
597
598 /* width */
599 WRITEL(ctx->img_width, S5P_FIMV_E_FRAME_WIDTH_V6); /* 16 align */
600 /* height */
601 WRITEL(ctx->img_height, S5P_FIMV_E_FRAME_HEIGHT_V6); /* 16 align */
602
603 /* cropped width */
604 WRITEL(ctx->img_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6);
605 /* cropped height */
606 WRITEL(ctx->img_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);
607 /* cropped offset */
608 WRITEL(0x0, S5P_FIMV_E_FRAME_CROP_OFFSET_V6);
609
610 /* pictype : IDR period */
611 reg = 0;
612 reg |= p->gop_size & 0xFFFF;
613 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6);
614
615 /* multi-slice control */
616 /* multi-slice MB number or bit size */
617 ctx->slice_mode = p->slice_mode;
618 reg = 0;
619 if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
620 reg |= (0x1 << 3);
621 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
622 ctx->slice_size.mb = p->slice_mb;
623 } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
624 reg |= (0x1 << 3);
625 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
626 ctx->slice_size.bits = p->slice_bit;
627 } else {
628 reg &= ~(0x1 << 3);
629 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
630 }
631
632 s5p_mfc_set_slice_mode(ctx);
633
634 /* cyclic intra refresh */
635 WRITEL(p->intra_refresh_mb, S5P_FIMV_E_IR_SIZE_V6);
636 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
637 if (p->intra_refresh_mb == 0)
638 reg &= ~(0x1 << 4);
639 else
640 reg |= (0x1 << 4);
641 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
642
643 /* 'NON_REFERENCE_STORE_ENABLE' for debugging */
644 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
645 reg &= ~(0x1 << 9);
646 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
647
648 /* memory structure cur. frame */
649 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
650 /* 0: Linear, 1: 2D tiled*/
651 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
652 reg &= ~(0x1 << 7);
653 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
654 /* 0: NV12(CbCr), 1: NV21(CrCb) */
655 WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6);
656 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) {
657 /* 0: Linear, 1: 2D tiled*/
658 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
659 reg &= ~(0x1 << 7);
660 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
661 /* 0: NV12(CbCr), 1: NV21(CrCb) */
662 WRITEL(0x1, S5P_FIMV_PIXEL_FORMAT_V6);
663 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
664 /* 0: Linear, 1: 2D tiled*/
665 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
666 reg |= (0x1 << 7);
667 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
668 /* 0: NV12(CbCr), 1: NV21(CrCb) */
669 WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6);
670 }
671
672 /* memory structure recon. frame */
673 /* 0: Linear, 1: 2D tiled */
674 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
675 reg |= (0x1 << 8);
676 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
677
678 /* padding control & value */
679 WRITEL(0x0, S5P_FIMV_E_PADDING_CTRL_V6);
680 if (p->pad) {
681 reg = 0;
682 /** enable */
683 reg |= (1 << 31);
684 /** cr value */
685 reg |= ((p->pad_cr & 0xFF) << 16);
686 /** cb value */
687 reg |= ((p->pad_cb & 0xFF) << 8);
688 /** y value */
689 reg |= p->pad_luma & 0xFF;
690 WRITEL(reg, S5P_FIMV_E_PADDING_CTRL_V6);
691 }
692
693 /* rate control config. */
694 reg = 0;
695 /* frame-level rate control */
696 reg |= ((p->rc_frame & 0x1) << 9);
697 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
698
699 /* bit rate */
700 if (p->rc_frame)
701 WRITEL(p->rc_bitrate,
702 S5P_FIMV_E_RC_BIT_RATE_V6);
703 else
704 WRITEL(1, S5P_FIMV_E_RC_BIT_RATE_V6);
705
706 /* reaction coefficient */
707 if (p->rc_frame) {
708 if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */
709 WRITEL(1, S5P_FIMV_E_RC_RPARAM_V6);
710 else /* loose CBR */
711 WRITEL(2, S5P_FIMV_E_RC_RPARAM_V6);
712 }
713
714 /* seq header ctrl */
715 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
716 reg &= ~(0x1 << 2);
717 reg |= ((p->seq_hdr_mode & 0x1) << 2);
718
719 /* frame skip mode */
720 reg &= ~(0x3);
721 reg |= (p->frame_skip_mode & 0x3);
722 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
723
724 /* 'DROP_CONTROL_ENABLE', disable */
725 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
726 reg &= ~(0x1 << 10);
727 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
728
729 /* setting for MV range [16, 256] */
730 reg = 0;
731 reg &= ~(0x3FFF);
732 reg = 256;
733 WRITEL(reg, S5P_FIMV_E_MV_HOR_RANGE_V6);
734
735 reg = 0;
736 reg &= ~(0x3FFF);
737 reg = 256;
738 WRITEL(reg, S5P_FIMV_E_MV_VER_RANGE_V6);
739
740 WRITEL(0x0, S5P_FIMV_E_FRAME_INSERTION_V6);
741 WRITEL(0x0, S5P_FIMV_E_ROI_BUFFER_ADDR_V6);
742 WRITEL(0x0, S5P_FIMV_E_PARAM_CHANGE_V6);
743 WRITEL(0x0, S5P_FIMV_E_RC_ROI_CTRL_V6);
744 WRITEL(0x0, S5P_FIMV_E_PICTURE_TAG_V6);
745
746 WRITEL(0x0, S5P_FIMV_E_BIT_COUNT_ENABLE_V6);
747 WRITEL(0x0, S5P_FIMV_E_MAX_BIT_COUNT_V6);
748 WRITEL(0x0, S5P_FIMV_E_MIN_BIT_COUNT_V6);
749
750 WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_ADDR_V6);
751 WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_SIZE_V6);
752
753 mfc_debug_leave();
754
755 return 0;
756 }
757
758 static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
759 {
760 struct s5p_mfc_dev *dev = ctx->dev;
761 struct s5p_mfc_enc_params *p = &ctx->enc_params;
762 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
763 unsigned int reg = 0;
764 int i;
765
766 mfc_debug_enter();
767
768 s5p_mfc_set_enc_params(ctx);
769
770 /* pictype : number of B */
771 reg = READL(S5P_FIMV_E_GOP_CONFIG_V6);
772 reg &= ~(0x3 << 16);
773 reg |= ((p->num_b_frame & 0x3) << 16);
774 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6);
775
776 /* profile & level */
777 reg = 0;
778 /** level */
779 reg |= ((p_h264->level & 0xFF) << 8);
780 /** profile - 0 ~ 3 */
781 reg |= p_h264->profile & 0x3F;
782 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6);
783
784 /* rate control config. */
785 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
786 /** macroblock level rate control */
787 reg &= ~(0x1 << 8);
788 reg |= ((p->rc_mb & 0x1) << 8);
789 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
790 /** frame QP */
791 reg &= ~(0x3F);
792 reg |= p_h264->rc_frame_qp & 0x3F;
793 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
794
795 /* max & min value of QP */
796 reg = 0;
797 /** max QP */
798 reg |= ((p_h264->rc_max_qp & 0x3F) << 8);
799 /** min QP */
800 reg |= p_h264->rc_min_qp & 0x3F;
801 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6);
802
803 /* other QPs */
804 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
805 if (!p->rc_frame && !p->rc_mb) {
806 reg = 0;
807 reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16);
808 reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8);
809 reg |= p_h264->rc_frame_qp & 0x3F;
810 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
811 }
812
813 /* frame rate */
814 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
815 reg = 0;
816 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
817 reg |= p->rc_framerate_denom & 0xFFFF;
818 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6);
819 }
820
821 /* vbv buffer size */
822 if (p->frame_skip_mode ==
823 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
824 WRITEL(p_h264->cpb_size & 0xFFFF,
825 S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
826
827 if (p->rc_frame)
828 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
829 }
830
831 /* interlace */
832 reg = 0;
833 reg |= ((p_h264->interlace & 0x1) << 3);
834 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
835
836 /* height */
837 if (p_h264->interlace) {
838 WRITEL(ctx->img_height >> 1,
839 S5P_FIMV_E_FRAME_HEIGHT_V6); /* 32 align */
840 /* cropped height */
841 WRITEL(ctx->img_height >> 1,
842 S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);
843 }
844
845 /* loop filter ctrl */
846 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
847 reg &= ~(0x3 << 1);
848 reg |= ((p_h264->loop_filter_mode & 0x3) << 1);
849 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
850
851 /* loopfilter alpha offset */
852 if (p_h264->loop_filter_alpha < 0) {
853 reg = 0x10;
854 reg |= (0xFF - p_h264->loop_filter_alpha) + 1;
855 } else {
856 reg = 0x00;
857 reg |= (p_h264->loop_filter_alpha & 0xF);
858 }
859 WRITEL(reg, S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6);
860
861 /* loopfilter beta offset */
862 if (p_h264->loop_filter_beta < 0) {
863 reg = 0x10;
864 reg |= (0xFF - p_h264->loop_filter_beta) + 1;
865 } else {
866 reg = 0x00;
867 reg |= (p_h264->loop_filter_beta & 0xF);
868 }
869 WRITEL(reg, S5P_FIMV_E_H264_LF_BETA_OFFSET_V6);
870
871 /* entropy coding mode */
872 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
873 reg &= ~(0x1);
874 reg |= p_h264->entropy_mode & 0x1;
875 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
876
877 /* number of ref. picture */
878 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
879 reg &= ~(0x1 << 7);
880 reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7);
881 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
882
883 /* 8x8 transform enable */
884 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
885 reg &= ~(0x3 << 12);
886 reg |= ((p_h264->_8x8_transform & 0x3) << 12);
887 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
888
889 /* macroblock adaptive scaling features */
890 WRITEL(0x0, S5P_FIMV_E_MB_RC_CONFIG_V6);
891 if (p->rc_mb) {
892 reg = 0;
893 /** dark region */
894 reg |= ((p_h264->rc_mb_dark & 0x1) << 3);
895 /** smooth region */
896 reg |= ((p_h264->rc_mb_smooth & 0x1) << 2);
897 /** static region */
898 reg |= ((p_h264->rc_mb_static & 0x1) << 1);
899 /** high activity region */
900 reg |= p_h264->rc_mb_activity & 0x1;
901 WRITEL(reg, S5P_FIMV_E_MB_RC_CONFIG_V6);
902 }
903
904 /* aspect ratio VUI */
905 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
906 reg &= ~(0x1 << 5);
907 reg |= ((p_h264->vui_sar & 0x1) << 5);
908 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
909
910 WRITEL(0x0, S5P_FIMV_E_ASPECT_RATIO_V6);
911 WRITEL(0x0, S5P_FIMV_E_EXTENDED_SAR_V6);
912 if (p_h264->vui_sar) {
913 /* aspect ration IDC */
914 reg = 0;
915 reg |= p_h264->vui_sar_idc & 0xFF;
916 WRITEL(reg, S5P_FIMV_E_ASPECT_RATIO_V6);
917 if (p_h264->vui_sar_idc == 0xFF) {
918 /* extended SAR */
919 reg = 0;
920 reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16;
921 reg |= p_h264->vui_ext_sar_height & 0xFFFF;
922 WRITEL(reg, S5P_FIMV_E_EXTENDED_SAR_V6);
923 }
924 }
925
926 /* intra picture period for H.264 open GOP */
927 /* control */
928 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
929 reg &= ~(0x1 << 4);
930 reg |= ((p_h264->open_gop & 0x1) << 4);
931 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
932 /* value */
933 WRITEL(0x0, S5P_FIMV_E_H264_I_PERIOD_V6);
934 if (p_h264->open_gop) {
935 reg = 0;
936 reg |= p_h264->open_gop_size & 0xFFFF;
937 WRITEL(reg, S5P_FIMV_E_H264_I_PERIOD_V6);
938 }
939
940 /* 'WEIGHTED_BI_PREDICTION' for B is disable */
941 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
942 reg &= ~(0x3 << 9);
943 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
944
945 /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */
946 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
947 reg &= ~(0x1 << 14);
948 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
949
950 /* ASO */
951 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
952 reg &= ~(0x1 << 6);
953 reg |= ((p_h264->aso & 0x1) << 6);
954 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
955
956 /* hier qp enable */
957 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
958 reg &= ~(0x1 << 8);
959 reg |= ((p_h264->open_gop & 0x1) << 8);
960 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
961 reg = 0;
962 if (p_h264->hier_qp && p_h264->hier_qp_layer) {
963 reg |= (p_h264->hier_qp_type & 0x1) << 0x3;
964 reg |= p_h264->hier_qp_layer & 0x7;
965 WRITEL(reg, S5P_FIMV_E_H264_NUM_T_LAYER_V6);
966 /* QP value for each layer */
967 for (i = 0; i < (p_h264->hier_qp_layer & 0x7); i++)
968 WRITEL(p_h264->hier_qp_layer_qp[i],
969 S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6 +
970 i * 4);
971 }
972 /* number of coding layer should be zero when hierarchical is disable */
973 WRITEL(reg, S5P_FIMV_E_H264_NUM_T_LAYER_V6);
974
975 /* frame packing SEI generation */
976 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
977 reg &= ~(0x1 << 25);
978 reg |= ((p_h264->sei_frame_packing & 0x1) << 25);
979 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
980 if (p_h264->sei_frame_packing) {
981 reg = 0;
982 /** current frame0 flag */
983 reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2);
984 /** arrangement type */
985 reg |= p_h264->sei_fp_arrangement_type & 0x3;
986 WRITEL(reg, S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6);
987 }
988
989 if (p_h264->fmo) {
990 switch (p_h264->fmo_map_type) {
991 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES:
992 if (p_h264->fmo_slice_grp > 4)
993 p_h264->fmo_slice_grp = 4;
994 for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++)
995 WRITEL(p_h264->fmo_run_len[i] - 1,
996 S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6 +
997 i * 4);
998 break;
999 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES:
1000 if (p_h264->fmo_slice_grp > 4)
1001 p_h264->fmo_slice_grp = 4;
1002 break;
1003 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN:
1004 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN:
1005 if (p_h264->fmo_slice_grp > 2)
1006 p_h264->fmo_slice_grp = 2;
1007 WRITEL(p_h264->fmo_chg_dir & 0x1,
1008 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6);
1009 /* the valid range is 0 ~ number of macroblocks -1 */
1010 WRITEL(p_h264->fmo_chg_rate,
1011 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6);
1012 break;
1013 default:
1014 mfc_err("Unsupported map type for FMO: %d\n",
1015 p_h264->fmo_map_type);
1016 p_h264->fmo_map_type = 0;
1017 p_h264->fmo_slice_grp = 1;
1018 break;
1019 }
1020
1021 WRITEL(p_h264->fmo_map_type,
1022 S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6);
1023 WRITEL(p_h264->fmo_slice_grp - 1,
1024 S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);
1025 } else {
1026 WRITEL(0, S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);
1027 }
1028
1029 mfc_debug_leave();
1030
1031 return 0;
1032 }
1033
1034 static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1035 {
1036 struct s5p_mfc_dev *dev = ctx->dev;
1037 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1038 struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
1039 unsigned int reg = 0;
1040
1041 mfc_debug_enter();
1042
1043 s5p_mfc_set_enc_params(ctx);
1044
1045 /* pictype : number of B */
1046 reg = READL(S5P_FIMV_E_GOP_CONFIG_V6);
1047 reg &= ~(0x3 << 16);
1048 reg |= ((p->num_b_frame & 0x3) << 16);
1049 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6);
1050
1051 /* profile & level */
1052 reg = 0;
1053 /** level */
1054 reg |= ((p_mpeg4->level & 0xFF) << 8);
1055 /** profile - 0 ~ 1 */
1056 reg |= p_mpeg4->profile & 0x3F;
1057 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6);
1058
1059 /* rate control config. */
1060 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
1061 /** macroblock level rate control */
1062 reg &= ~(0x1 << 8);
1063 reg |= ((p->rc_mb & 0x1) << 8);
1064 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1065 /** frame QP */
1066 reg &= ~(0x3F);
1067 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1068 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1069
1070 /* max & min value of QP */
1071 reg = 0;
1072 /** max QP */
1073 reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8);
1074 /** min QP */
1075 reg |= p_mpeg4->rc_min_qp & 0x3F;
1076 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6);
1077
1078 /* other QPs */
1079 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1080 if (!p->rc_frame && !p->rc_mb) {
1081 reg = 0;
1082 reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16);
1083 reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8);
1084 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1085 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1086 }
1087
1088 /* frame rate */
1089 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1090 reg = 0;
1091 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1092 reg |= p->rc_framerate_denom & 0xFFFF;
1093 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6);
1094 }
1095
1096 /* vbv buffer size */
1097 if (p->frame_skip_mode ==
1098 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1099 WRITEL(p->vbv_size & 0xFFFF, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
1100
1101 if (p->rc_frame)
1102 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
1103 }
1104
1105 /* Disable HEC */
1106 WRITEL(0x0, S5P_FIMV_E_MPEG4_OPTIONS_V6);
1107 WRITEL(0x0, S5P_FIMV_E_MPEG4_HEC_PERIOD_V6);
1108
1109 mfc_debug_leave();
1110
1111 return 0;
1112 }
1113
1114 static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1115 {
1116 struct s5p_mfc_dev *dev = ctx->dev;
1117 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1118 struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4;
1119 unsigned int reg = 0;
1120
1121 mfc_debug_enter();
1122
1123 s5p_mfc_set_enc_params(ctx);
1124
1125 /* profile & level */
1126 reg = 0;
1127 /** profile */
1128 reg |= (0x1 << 4);
1129 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6);
1130
1131 /* rate control config. */
1132 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
1133 /** macroblock level rate control */
1134 reg &= ~(0x1 << 8);
1135 reg |= ((p->rc_mb & 0x1) << 8);
1136 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1137 /** frame QP */
1138 reg &= ~(0x3F);
1139 reg |= p_h263->rc_frame_qp & 0x3F;
1140 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1141
1142 /* max & min value of QP */
1143 reg = 0;
1144 /** max QP */
1145 reg |= ((p_h263->rc_max_qp & 0x3F) << 8);
1146 /** min QP */
1147 reg |= p_h263->rc_min_qp & 0x3F;
1148 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6);
1149
1150 /* other QPs */
1151 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1152 if (!p->rc_frame && !p->rc_mb) {
1153 reg = 0;
1154 reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16);
1155 reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8);
1156 reg |= p_h263->rc_frame_qp & 0x3F;
1157 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1158 }
1159
1160 /* frame rate */
1161 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1162 reg = 0;
1163 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1164 reg |= p->rc_framerate_denom & 0xFFFF;
1165 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6);
1166 }
1167
1168 /* vbv buffer size */
1169 if (p->frame_skip_mode ==
1170 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1171 WRITEL(p->vbv_size & 0xFFFF, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
1172
1173 if (p->rc_frame)
1174 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
1175 }
1176
1177 mfc_debug_leave();
1178
1179 return 0;
1180 }
1181
1182 static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
1183 {
1184 struct s5p_mfc_dev *dev = ctx->dev;
1185 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1186 struct s5p_mfc_vp8_enc_params *p_vp8 = &p->codec.vp8;
1187 unsigned int reg = 0;
1188 unsigned int val = 0;
1189
1190 mfc_debug_enter();
1191
1192 s5p_mfc_set_enc_params(ctx);
1193
1194 /* pictype : number of B */
1195 reg = READL(S5P_FIMV_E_GOP_CONFIG_V6);
1196 reg &= ~(0x3 << 16);
1197 reg |= ((p->num_b_frame & 0x3) << 16);
1198 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6);
1199
1200 /* profile & level */
1201 reg = 0;
1202 /** profile */
1203 reg |= (0x1 << 4);
1204 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6);
1205
1206 /* rate control config. */
1207 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
1208 /** macroblock level rate control */
1209 reg &= ~(0x1 << 8);
1210 reg |= ((p->rc_mb & 0x1) << 8);
1211 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1212
1213 /* frame rate */
1214 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1215 reg = 0;
1216 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1217 reg |= p->rc_framerate_denom & 0xFFFF;
1218 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6);
1219 }
1220
1221 /* vbv buffer size */
1222 if (p->frame_skip_mode ==
1223 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1224 WRITEL(p->vbv_size & 0xFFFF, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
1225
1226 if (p->rc_frame)
1227 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
1228 }
1229
1230 /* VP8 specific params */
1231 reg = 0;
1232 reg |= (p_vp8->imd_4x4 & 0x1) << 10;
1233 switch (p_vp8->num_partitions) {
1234 case V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION:
1235 val = 0;
1236 break;
1237 case V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS:
1238 val = 2;
1239 break;
1240 case V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS:
1241 val = 4;
1242 break;
1243 case V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS:
1244 val = 8;
1245 break;
1246 }
1247 reg |= (val & 0xF) << 3;
1248 reg |= (p_vp8->num_ref & 0x2);
1249 WRITEL(reg, S5P_FIMV_E_VP8_OPTIONS_V7);
1250
1251 mfc_debug_leave();
1252
1253 return 0;
1254 }
1255
1256 /* Initialize decoding */
1257 static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1258 {
1259 struct s5p_mfc_dev *dev = ctx->dev;
1260 unsigned int reg = 0;
1261 int fmo_aso_ctrl = 0;
1262
1263 mfc_debug_enter();
1264 mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no,
1265 S5P_FIMV_CH_SEQ_HEADER_V6);
1266 mfc_debug(2, "BUFs: %08x %08x %08x\n",
1267 READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6),
1268 READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6),
1269 READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6));
1270
1271 /* FMO_ASO_CTRL - 0: Enable, 1: Disable */
1272 reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6);
1273
1274 /* When user sets desplay_delay to 0,
1275 * It works as "display_delay enable" and delay set to 0.
1276 * If user wants display_delay disable, It should be
1277 * set to negative value. */
1278 if (ctx->display_delay >= 0) {
1279 reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6);
1280 WRITEL(ctx->display_delay, S5P_FIMV_D_DISPLAY_DELAY_V6);
1281 }
1282
1283 if (IS_MFCV7(dev)) {
1284 WRITEL(reg, S5P_FIMV_D_DEC_OPTIONS_V6);
1285 reg = 0;
1286 }
1287
1288 /* Setup loop filter, for decoding this is only valid for MPEG4 */
1289 if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) {
1290 mfc_debug(2, "Set loop filter to: %d\n",
1291 ctx->loop_filter_mpeg4);
1292 reg |= (ctx->loop_filter_mpeg4 <<
1293 S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6);
1294 }
1295 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)
1296 reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6);
1297
1298 if (IS_MFCV7(dev))
1299 WRITEL(reg, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V7);
1300 else
1301 WRITEL(reg, S5P_FIMV_D_DEC_OPTIONS_V6);
1302
1303 /* 0: NV12(CbCr), 1: NV21(CrCb) */
1304 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
1305 WRITEL(0x1, S5P_FIMV_PIXEL_FORMAT_V6);
1306 else
1307 WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6);
1308
1309
1310 /* sei parse */
1311 WRITEL(ctx->sei_fp_parse & 0x1, S5P_FIMV_D_SEI_ENABLE_V6);
1312
1313 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1314 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1315 S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1316
1317 mfc_debug_leave();
1318 return 0;
1319 }
1320
1321 static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1322 {
1323 struct s5p_mfc_dev *dev = ctx->dev;
1324
1325 if (flush) {
1326 dev->curr_ctx = ctx->num;
1327 s5p_mfc_clean_ctx_int_flags(ctx);
1328 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1329 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1330 S5P_FIMV_H2R_CMD_FLUSH_V6, NULL);
1331 }
1332 }
1333
1334 /* Decode a single frame */
1335 static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx,
1336 enum s5p_mfc_decode_arg last_frame)
1337 {
1338 struct s5p_mfc_dev *dev = ctx->dev;
1339
1340 WRITEL(ctx->dec_dst_flag, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6);
1341 WRITEL(ctx->slice_interface & 0x1, S5P_FIMV_D_SLICE_IF_ENABLE_V6);
1342
1343 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1344 /* Issue different commands to instance basing on whether it
1345 * is the last frame or not. */
1346 switch (last_frame) {
1347 case 0:
1348 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1349 S5P_FIMV_CH_FRAME_START_V6, NULL);
1350 break;
1351 case 1:
1352 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1353 S5P_FIMV_CH_LAST_FRAME_V6, NULL);
1354 break;
1355 default:
1356 mfc_err("Unsupported last frame arg.\n");
1357 return -EINVAL;
1358 }
1359
1360 mfc_debug(2, "Decoding a usual frame.\n");
1361 return 0;
1362 }
1363
1364 static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
1365 {
1366 struct s5p_mfc_dev *dev = ctx->dev;
1367
1368 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1369 s5p_mfc_set_enc_params_h264(ctx);
1370 else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC)
1371 s5p_mfc_set_enc_params_mpeg4(ctx);
1372 else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC)
1373 s5p_mfc_set_enc_params_h263(ctx);
1374 else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC)
1375 s5p_mfc_set_enc_params_vp8(ctx);
1376 else {
1377 mfc_err("Unknown codec for encoding (%x).\n",
1378 ctx->codec_mode);
1379 return -EINVAL;
1380 }
1381
1382 /* Set stride lengths */
1383 if (IS_MFCV7(dev)) {
1384 WRITEL(ctx->img_width, S5P_FIMV_E_SOURCE_FIRST_STRIDE_V7);
1385 WRITEL(ctx->img_width, S5P_FIMV_E_SOURCE_SECOND_STRIDE_V7);
1386 }
1387
1388 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1389 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1390 S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1391
1392 return 0;
1393 }
1394
1395 static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx)
1396 {
1397 struct s5p_mfc_dev *dev = ctx->dev;
1398 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1399 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
1400 int i;
1401
1402 if (p_h264->aso) {
1403 for (i = 0; i < 8; i++)
1404 WRITEL(p_h264->aso_slice_order[i],
1405 S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6 + i * 4);
1406 }
1407 return 0;
1408 }
1409
1410 /* Encode a single frame */
1411 static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx)
1412 {
1413 struct s5p_mfc_dev *dev = ctx->dev;
1414
1415 mfc_debug(2, "++\n");
1416
1417 /* memory structure cur. frame */
1418
1419 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1420 s5p_mfc_h264_set_aso_slice_order_v6(ctx);
1421
1422 s5p_mfc_set_slice_mode(ctx);
1423
1424 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1425 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1426 S5P_FIMV_CH_FRAME_START_V6, NULL);
1427
1428 mfc_debug(2, "--\n");
1429
1430 return 0;
1431 }
1432
1433 static inline int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
1434 {
1435 unsigned long flags;
1436 int new_ctx;
1437 int cnt;
1438
1439 spin_lock_irqsave(&dev->condlock, flags);
1440 mfc_debug(2, "Previous context: %d (bits %08lx)\n", dev->curr_ctx,
1441 dev->ctx_work_bits);
1442 new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS;
1443 cnt = 0;
1444 while (!test_bit(new_ctx, &dev->ctx_work_bits)) {
1445 new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS;
1446 cnt++;
1447 if (cnt > MFC_NUM_CONTEXTS) {
1448 /* No contexts to run */
1449 spin_unlock_irqrestore(&dev->condlock, flags);
1450 return -EAGAIN;
1451 }
1452 }
1453 spin_unlock_irqrestore(&dev->condlock, flags);
1454 return new_ctx;
1455 }
1456
1457 static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx)
1458 {
1459 struct s5p_mfc_dev *dev = ctx->dev;
1460 struct s5p_mfc_buf *temp_vb;
1461 unsigned long flags;
1462
1463 spin_lock_irqsave(&dev->irqlock, flags);
1464
1465 /* Frames are being decoded */
1466 if (list_empty(&ctx->src_queue)) {
1467 mfc_debug(2, "No src buffers.\n");
1468 spin_unlock_irqrestore(&dev->irqlock, flags);
1469 return;
1470 }
1471 /* Get the next source buffer */
1472 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1473 temp_vb->flags |= MFC_BUF_FLAG_USED;
1474 s5p_mfc_set_dec_stream_buffer_v6(ctx,
1475 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0, 0);
1476 spin_unlock_irqrestore(&dev->irqlock, flags);
1477
1478 dev->curr_ctx = ctx->num;
1479 s5p_mfc_clean_ctx_int_flags(ctx);
1480 s5p_mfc_decode_one_frame_v6(ctx, 1);
1481 }
1482
1483 static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx)
1484 {
1485 struct s5p_mfc_dev *dev = ctx->dev;
1486 struct s5p_mfc_buf *temp_vb;
1487 unsigned long flags;
1488 int last_frame = 0;
1489
1490 if (ctx->state == MFCINST_FINISHING) {
1491 last_frame = MFC_DEC_LAST_FRAME;
1492 s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1493 dev->curr_ctx = ctx->num;
1494 s5p_mfc_clean_ctx_int_flags(ctx);
1495 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1496 return 0;
1497 }
1498
1499 spin_lock_irqsave(&dev->irqlock, flags);
1500 /* Frames are being decoded */
1501 if (list_empty(&ctx->src_queue)) {
1502 mfc_debug(2, "No src buffers.\n");
1503 spin_unlock_irqrestore(&dev->irqlock, flags);
1504 return -EAGAIN;
1505 }
1506 /* Get the next source buffer */
1507 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1508 temp_vb->flags |= MFC_BUF_FLAG_USED;
1509 s5p_mfc_set_dec_stream_buffer_v6(ctx,
1510 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0),
1511 ctx->consumed_stream,
1512 temp_vb->b->v4l2_planes[0].bytesused);
1513 spin_unlock_irqrestore(&dev->irqlock, flags);
1514
1515 dev->curr_ctx = ctx->num;
1516 s5p_mfc_clean_ctx_int_flags(ctx);
1517 if (temp_vb->b->v4l2_planes[0].bytesused == 0) {
1518 last_frame = 1;
1519 mfc_debug(2, "Setting ctx->state to FINISHING\n");
1520 ctx->state = MFCINST_FINISHING;
1521 }
1522 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1523
1524 return 0;
1525 }
1526
1527 static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
1528 {
1529 struct s5p_mfc_dev *dev = ctx->dev;
1530 unsigned long flags;
1531 struct s5p_mfc_buf *dst_mb;
1532 struct s5p_mfc_buf *src_mb;
1533 unsigned long src_y_addr, src_c_addr, dst_addr;
1534 /*
1535 unsigned int src_y_size, src_c_size;
1536 */
1537 unsigned int dst_size;
1538
1539 spin_lock_irqsave(&dev->irqlock, flags);
1540
1541 if (list_empty(&ctx->src_queue)) {
1542 mfc_debug(2, "no src buffers.\n");
1543 spin_unlock_irqrestore(&dev->irqlock, flags);
1544 return -EAGAIN;
1545 }
1546
1547 if (list_empty(&ctx->dst_queue)) {
1548 mfc_debug(2, "no dst buffers.\n");
1549 spin_unlock_irqrestore(&dev->irqlock, flags);
1550 return -EAGAIN;
1551 }
1552
1553 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1554 src_mb->flags |= MFC_BUF_FLAG_USED;
1555 src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 0);
1556 src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1);
1557
1558 mfc_debug(2, "enc src y addr: 0x%08lx\n", src_y_addr);
1559 mfc_debug(2, "enc src c addr: 0x%08lx\n", src_c_addr);
1560
1561 s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr);
1562
1563 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1564 dst_mb->flags |= MFC_BUF_FLAG_USED;
1565 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
1566 dst_size = vb2_plane_size(dst_mb->b, 0);
1567
1568 s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1569
1570 spin_unlock_irqrestore(&dev->irqlock, flags);
1571
1572 dev->curr_ctx = ctx->num;
1573 s5p_mfc_clean_ctx_int_flags(ctx);
1574 s5p_mfc_encode_one_frame_v6(ctx);
1575
1576 return 0;
1577 }
1578
1579 static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
1580 {
1581 struct s5p_mfc_dev *dev = ctx->dev;
1582 unsigned long flags;
1583 struct s5p_mfc_buf *temp_vb;
1584
1585 /* Initializing decoding - parsing header */
1586 spin_lock_irqsave(&dev->irqlock, flags);
1587 mfc_debug(2, "Preparing to init decoding.\n");
1588 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1589 mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused);
1590 s5p_mfc_set_dec_stream_buffer_v6(ctx,
1591 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0,
1592 temp_vb->b->v4l2_planes[0].bytesused);
1593 spin_unlock_irqrestore(&dev->irqlock, flags);
1594 dev->curr_ctx = ctx->num;
1595 s5p_mfc_clean_ctx_int_flags(ctx);
1596 s5p_mfc_init_decode_v6(ctx);
1597 }
1598
1599 static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
1600 {
1601 struct s5p_mfc_dev *dev = ctx->dev;
1602 unsigned long flags;
1603 struct s5p_mfc_buf *dst_mb;
1604 unsigned long dst_addr;
1605 unsigned int dst_size;
1606
1607 spin_lock_irqsave(&dev->irqlock, flags);
1608
1609 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1610 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
1611 dst_size = vb2_plane_size(dst_mb->b, 0);
1612 s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1613 spin_unlock_irqrestore(&dev->irqlock, flags);
1614 dev->curr_ctx = ctx->num;
1615 s5p_mfc_clean_ctx_int_flags(ctx);
1616 s5p_mfc_init_encode_v6(ctx);
1617 }
1618
1619 static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
1620 {
1621 struct s5p_mfc_dev *dev = ctx->dev;
1622 int ret;
1623 /* Header was parsed now start processing
1624 * First set the output frame buffers
1625 * s5p_mfc_alloc_dec_buffers(ctx); */
1626
1627 if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
1628 mfc_err("It seems that not all destionation buffers were\n"
1629 "mmaped.MFC requires that all destination are mmaped\n"
1630 "before starting processing.\n");
1631 return -EAGAIN;
1632 }
1633
1634 dev->curr_ctx = ctx->num;
1635 s5p_mfc_clean_ctx_int_flags(ctx);
1636 ret = s5p_mfc_set_dec_frame_buffer_v6(ctx);
1637 if (ret) {
1638 mfc_err("Failed to alloc frame mem.\n");
1639 ctx->state = MFCINST_ERROR;
1640 }
1641 return ret;
1642 }
1643
1644 static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx)
1645 {
1646 struct s5p_mfc_dev *dev = ctx->dev;
1647 int ret;
1648
1649 dev->curr_ctx = ctx->num;
1650 s5p_mfc_clean_ctx_int_flags(ctx);
1651 ret = s5p_mfc_set_enc_ref_buffer_v6(ctx);
1652 if (ret) {
1653 mfc_err("Failed to alloc frame mem.\n");
1654 ctx->state = MFCINST_ERROR;
1655 }
1656 return ret;
1657 }
1658
1659 /* Try running an operation on hardware */
1660 static void s5p_mfc_try_run_v6(struct s5p_mfc_dev *dev)
1661 {
1662 struct s5p_mfc_ctx *ctx;
1663 int new_ctx;
1664 unsigned int ret = 0;
1665
1666 mfc_debug(1, "Try run dev: %p\n", dev);
1667
1668 /* Check whether hardware is not running */
1669 if (test_and_set_bit(0, &dev->hw_lock) != 0) {
1670 /* This is perfectly ok, the scheduled ctx should wait */
1671 mfc_debug(1, "Couldn't lock HW.\n");
1672 return;
1673 }
1674
1675 /* Choose the context to run */
1676 new_ctx = s5p_mfc_get_new_ctx(dev);
1677 if (new_ctx < 0) {
1678 /* No contexts to run */
1679 if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
1680 mfc_err("Failed to unlock hardware.\n");
1681 return;
1682 }
1683
1684 mfc_debug(1, "No ctx is scheduled to be run.\n");
1685 return;
1686 }
1687
1688 mfc_debug(1, "New context: %d\n", new_ctx);
1689 ctx = dev->ctx[new_ctx];
1690 mfc_debug(1, "Seting new context to %p\n", ctx);
1691 /* Got context to run in ctx */
1692 mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n",
1693 ctx->dst_queue_cnt, ctx->pb_count, ctx->src_queue_cnt);
1694 mfc_debug(1, "ctx->state=%d\n", ctx->state);
1695 /* Last frame has already been sent to MFC
1696 * Now obtaining frames from MFC buffer */
1697
1698 s5p_mfc_clock_on();
1699 if (ctx->type == MFCINST_DECODER) {
1700 switch (ctx->state) {
1701 case MFCINST_FINISHING:
1702 s5p_mfc_run_dec_last_frames(ctx);
1703 break;
1704 case MFCINST_RUNNING:
1705 ret = s5p_mfc_run_dec_frame(ctx);
1706 break;
1707 case MFCINST_INIT:
1708 s5p_mfc_clean_ctx_int_flags(ctx);
1709 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1710 ctx);
1711 break;
1712 case MFCINST_RETURN_INST:
1713 s5p_mfc_clean_ctx_int_flags(ctx);
1714 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1715 ctx);
1716 break;
1717 case MFCINST_GOT_INST:
1718 s5p_mfc_run_init_dec(ctx);
1719 break;
1720 case MFCINST_HEAD_PARSED:
1721 ret = s5p_mfc_run_init_dec_buffers(ctx);
1722 break;
1723 case MFCINST_FLUSH:
1724 s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag);
1725 break;
1726 case MFCINST_RES_CHANGE_INIT:
1727 s5p_mfc_run_dec_last_frames(ctx);
1728 break;
1729 case MFCINST_RES_CHANGE_FLUSH:
1730 s5p_mfc_run_dec_last_frames(ctx);
1731 break;
1732 case MFCINST_RES_CHANGE_END:
1733 mfc_debug(2, "Finished remaining frames after resolution change.\n");
1734 ctx->capture_state = QUEUE_FREE;
1735 mfc_debug(2, "Will re-init the codec`.\n");
1736 s5p_mfc_run_init_dec(ctx);
1737 break;
1738 default:
1739 ret = -EAGAIN;
1740 }
1741 } else if (ctx->type == MFCINST_ENCODER) {
1742 switch (ctx->state) {
1743 case MFCINST_FINISHING:
1744 case MFCINST_RUNNING:
1745 ret = s5p_mfc_run_enc_frame(ctx);
1746 break;
1747 case MFCINST_INIT:
1748 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1749 ctx);
1750 break;
1751 case MFCINST_RETURN_INST:
1752 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1753 ctx);
1754 break;
1755 case MFCINST_GOT_INST:
1756 s5p_mfc_run_init_enc(ctx);
1757 break;
1758 case MFCINST_HEAD_PRODUCED:
1759 ret = s5p_mfc_run_init_enc_buffers(ctx);
1760 break;
1761 default:
1762 ret = -EAGAIN;
1763 }
1764 } else {
1765 mfc_err("invalid context type: %d\n", ctx->type);
1766 ret = -EAGAIN;
1767 }
1768
1769 if (ret) {
1770 /* Free hardware lock */
1771 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
1772 mfc_err("Failed to unlock hardware.\n");
1773
1774 /* This is in deed imporant, as no operation has been
1775 * scheduled, reduce the clock count as no one will
1776 * ever do this, because no interrupt related to this try_run
1777 * will ever come from hardware. */
1778 s5p_mfc_clock_off();
1779 }
1780 }
1781
1782
1783 static void s5p_mfc_cleanup_queue_v6(struct list_head *lh, struct vb2_queue *vq)
1784 {
1785 struct s5p_mfc_buf *b;
1786 int i;
1787
1788 while (!list_empty(lh)) {
1789 b = list_entry(lh->next, struct s5p_mfc_buf, list);
1790 for (i = 0; i < b->b->num_planes; i++)
1791 vb2_set_plane_payload(b->b, i, 0);
1792 vb2_buffer_done(b->b, VB2_BUF_STATE_ERROR);
1793 list_del(&b->list);
1794 }
1795 }
1796
1797 static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev)
1798 {
1799 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
1800 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_INT_V6);
1801 }
1802
1803 static void s5p_mfc_write_info_v6(struct s5p_mfc_ctx *ctx, unsigned int data,
1804 unsigned int ofs)
1805 {
1806 struct s5p_mfc_dev *dev = ctx->dev;
1807
1808 s5p_mfc_clock_on();
1809 WRITEL(data, ofs);
1810 s5p_mfc_clock_off();
1811 }
1812
1813 static unsigned int
1814 s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned int ofs)
1815 {
1816 struct s5p_mfc_dev *dev = ctx->dev;
1817 int ret;
1818
1819 s5p_mfc_clock_on();
1820 ret = READL(ofs);
1821 s5p_mfc_clock_off();
1822
1823 return ret;
1824 }
1825
1826 static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev)
1827 {
1828 return mfc_read(dev, S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6);
1829 }
1830
1831 static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev)
1832 {
1833 return mfc_read(dev, S5P_FIMV_D_DECODED_LUMA_ADDR_V6);
1834 }
1835
1836 static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev)
1837 {
1838 return mfc_read(dev, S5P_FIMV_D_DISPLAY_STATUS_V6);
1839 }
1840
1841 static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev)
1842 {
1843 return mfc_read(dev, S5P_FIMV_D_DECODED_STATUS_V6);
1844 }
1845
1846 static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev)
1847 {
1848 return mfc_read(dev, S5P_FIMV_D_DECODED_FRAME_TYPE_V6) &
1849 S5P_FIMV_DECODE_FRAME_MASK_V6;
1850 }
1851
1852 static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx)
1853 {
1854 return mfc_read(ctx->dev, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6) &
1855 S5P_FIMV_DECODE_FRAME_MASK_V6;
1856 }
1857
1858 static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev)
1859 {
1860 return mfc_read(dev, S5P_FIMV_D_DECODED_NAL_SIZE_V6);
1861 }
1862
1863 static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev)
1864 {
1865 return mfc_read(dev, S5P_FIMV_RISC2HOST_CMD_V6) &
1866 S5P_FIMV_RISC2HOST_CMD_MASK;
1867 }
1868
1869 static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev)
1870 {
1871 return mfc_read(dev, S5P_FIMV_ERROR_CODE_V6);
1872 }
1873
1874 static int s5p_mfc_err_dec_v6(unsigned int err)
1875 {
1876 return (err & S5P_FIMV_ERR_DEC_MASK_V6) >> S5P_FIMV_ERR_DEC_SHIFT_V6;
1877 }
1878
1879 static int s5p_mfc_err_dspl_v6(unsigned int err)
1880 {
1881 return (err & S5P_FIMV_ERR_DSPL_MASK_V6) >> S5P_FIMV_ERR_DSPL_SHIFT_V6;
1882 }
1883
1884 static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev)
1885 {
1886 return mfc_read(dev, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6);
1887 }
1888
1889 static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev)
1890 {
1891 return mfc_read(dev, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6);
1892 }
1893
1894 static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev)
1895 {
1896 return mfc_read(dev, S5P_FIMV_D_MIN_NUM_DPB_V6);
1897 }
1898
1899 static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev)
1900 {
1901 return mfc_read(dev, S5P_FIMV_D_MIN_NUM_MV_V6);
1902 }
1903
1904 static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev)
1905 {
1906 return mfc_read(dev, S5P_FIMV_RET_INSTANCE_ID_V6);
1907 }
1908
1909 static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev)
1910 {
1911 return mfc_read(dev, S5P_FIMV_E_NUM_DPB_V6);
1912 }
1913
1914 static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev)
1915 {
1916 return mfc_read(dev, S5P_FIMV_E_STREAM_SIZE_V6);
1917 }
1918
1919 static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev)
1920 {
1921 return mfc_read(dev, S5P_FIMV_E_SLICE_TYPE_V6);
1922 }
1923
1924 static int s5p_mfc_get_enc_pic_count_v6(struct s5p_mfc_dev *dev)
1925 {
1926 return mfc_read(dev, S5P_FIMV_E_PICTURE_COUNT_V6);
1927 }
1928
1929 static int s5p_mfc_get_sei_avail_status_v6(struct s5p_mfc_ctx *ctx)
1930 {
1931 return mfc_read(ctx->dev, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6);
1932 }
1933
1934 static int s5p_mfc_get_mvc_num_views_v6(struct s5p_mfc_dev *dev)
1935 {
1936 return mfc_read(dev, S5P_FIMV_D_MVC_NUM_VIEWS_V6);
1937 }
1938
1939 static int s5p_mfc_get_mvc_view_id_v6(struct s5p_mfc_dev *dev)
1940 {
1941 return mfc_read(dev, S5P_FIMV_D_MVC_VIEW_ID_V6);
1942 }
1943
1944 static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx)
1945 {
1946 return s5p_mfc_read_info_v6(ctx, PIC_TIME_TOP_V6);
1947 }
1948
1949 static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx)
1950 {
1951 return s5p_mfc_read_info_v6(ctx, PIC_TIME_BOT_V6);
1952 }
1953
1954 static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx)
1955 {
1956 return s5p_mfc_read_info_v6(ctx, CROP_INFO_H_V6);
1957 }
1958
1959 static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
1960 {
1961 return s5p_mfc_read_info_v6(ctx, CROP_INFO_V_V6);
1962 }
1963
1964 /* Initialize opr function pointers for MFC v6 */
1965 static struct s5p_mfc_hw_ops s5p_mfc_ops_v6 = {
1966 .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v6,
1967 .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v6,
1968 .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v6,
1969 .release_codec_buffers = s5p_mfc_release_codec_buffers_v6,
1970 .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v6,
1971 .release_instance_buffer = s5p_mfc_release_instance_buffer_v6,
1972 .alloc_dev_context_buffer =
1973 s5p_mfc_alloc_dev_context_buffer_v6,
1974 .release_dev_context_buffer =
1975 s5p_mfc_release_dev_context_buffer_v6,
1976 .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v6,
1977 .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v6,
1978 .set_dec_stream_buffer = s5p_mfc_set_dec_stream_buffer_v6,
1979 .set_dec_frame_buffer = s5p_mfc_set_dec_frame_buffer_v6,
1980 .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v6,
1981 .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v6,
1982 .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v6,
1983 .set_enc_ref_buffer = s5p_mfc_set_enc_ref_buffer_v6,
1984 .init_decode = s5p_mfc_init_decode_v6,
1985 .init_encode = s5p_mfc_init_encode_v6,
1986 .encode_one_frame = s5p_mfc_encode_one_frame_v6,
1987 .try_run = s5p_mfc_try_run_v6,
1988 .cleanup_queue = s5p_mfc_cleanup_queue_v6,
1989 .clear_int_flags = s5p_mfc_clear_int_flags_v6,
1990 .write_info = s5p_mfc_write_info_v6,
1991 .read_info = s5p_mfc_read_info_v6,
1992 .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v6,
1993 .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v6,
1994 .get_dspl_status = s5p_mfc_get_dspl_status_v6,
1995 .get_dec_status = s5p_mfc_get_dec_status_v6,
1996 .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v6,
1997 .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v6,
1998 .get_consumed_stream = s5p_mfc_get_consumed_stream_v6,
1999 .get_int_reason = s5p_mfc_get_int_reason_v6,
2000 .get_int_err = s5p_mfc_get_int_err_v6,
2001 .err_dec = s5p_mfc_err_dec_v6,
2002 .err_dspl = s5p_mfc_err_dspl_v6,
2003 .get_img_width = s5p_mfc_get_img_width_v6,
2004 .get_img_height = s5p_mfc_get_img_height_v6,
2005 .get_dpb_count = s5p_mfc_get_dpb_count_v6,
2006 .get_mv_count = s5p_mfc_get_mv_count_v6,
2007 .get_inst_no = s5p_mfc_get_inst_no_v6,
2008 .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v6,
2009 .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v6,
2010 .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v6,
2011 .get_enc_pic_count = s5p_mfc_get_enc_pic_count_v6,
2012 .get_sei_avail_status = s5p_mfc_get_sei_avail_status_v6,
2013 .get_mvc_num_views = s5p_mfc_get_mvc_num_views_v6,
2014 .get_mvc_view_id = s5p_mfc_get_mvc_view_id_v6,
2015 .get_pic_type_top = s5p_mfc_get_pic_type_top_v6,
2016 .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v6,
2017 .get_crop_info_h = s5p_mfc_get_crop_info_h_v6,
2018 .get_crop_info_v = s5p_mfc_get_crop_info_v_v6,
2019 };
2020
2021 struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void)
2022 {
2023 return &s5p_mfc_ops_v6;
2024 }
Linux with added FPC-III support