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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / media / platform / soc_camera / mx3_camera.c
blobf975b70086922c866dc415f9eca4506aef3c19ea
1 /*
2 * V4L2 Driver for i.MX3x camera host
3 *
4 * Copyright (C) 2008
5 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/videodev2.h>
15 #include <linux/platform_device.h>
16 #include <linux/clk.h>
17 #include <linux/vmalloc.h>
18 #include <linux/interrupt.h>
19 #include <linux/sched.h>
20 #include <linux/dma/ipu-dma.h>
21
22 #include <media/v4l2-common.h>
23 #include <media/v4l2-dev.h>
24 #include <media/videobuf2-dma-contig.h>
25 #include <media/soc_camera.h>
26 #include <media/soc_mediabus.h>
27
28 #include <linux/platform_data/camera-mx3.h>
29 #include <linux/platform_data/dma-imx.h>
30
31 #define MX3_CAM_DRV_NAME "mx3-camera"
32
33 /* CMOS Sensor Interface Registers */
34 #define CSI_REG_START 0x60
35
36 #define CSI_SENS_CONF (0x60 - CSI_REG_START)
37 #define CSI_SENS_FRM_SIZE (0x64 - CSI_REG_START)
38 #define CSI_ACT_FRM_SIZE (0x68 - CSI_REG_START)
39 #define CSI_OUT_FRM_CTRL (0x6C - CSI_REG_START)
40 #define CSI_TST_CTRL (0x70 - CSI_REG_START)
41 #define CSI_CCIR_CODE_1 (0x74 - CSI_REG_START)
42 #define CSI_CCIR_CODE_2 (0x78 - CSI_REG_START)
43 #define CSI_CCIR_CODE_3 (0x7C - CSI_REG_START)
44 #define CSI_FLASH_STROBE_1 (0x80 - CSI_REG_START)
45 #define CSI_FLASH_STROBE_2 (0x84 - CSI_REG_START)
46
47 #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0
48 #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1
49 #define CSI_SENS_CONF_DATA_POL_SHIFT 2
50 #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3
51 #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4
52 #define CSI_SENS_CONF_SENS_CLKSRC_SHIFT 7
53 #define CSI_SENS_CONF_DATA_FMT_SHIFT 8
54 #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 10
55 #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15
56 #define CSI_SENS_CONF_DIVRATIO_SHIFT 16
57
58 #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 (0UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
59 #define CSI_SENS_CONF_DATA_FMT_YUV422 (2UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
60 #define CSI_SENS_CONF_DATA_FMT_BAYER (3UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
61
62 #define MAX_VIDEO_MEM 16
63
64 struct mx3_camera_buffer {
65 /* common v4l buffer stuff -- must be first */
66 struct vb2_buffer vb;
67 struct list_head queue;
68
69 /* One descriptot per scatterlist (per frame) */
70 struct dma_async_tx_descriptor *txd;
71
72 /* We have to "build" a scatterlist ourselves - one element per frame */
73 struct scatterlist sg;
74 };
75
76 /**
77 * struct mx3_camera_dev - i.MX3x camera (CSI) object
78 * @dev: camera device, to which the coherent buffer is attached
79 * @icd: currently attached camera sensor
80 * @clk: pointer to clock
81 * @base: remapped register base address
82 * @pdata: platform data
83 * @platform_flags: platform flags
84 * @mclk: master clock frequency in Hz
85 * @capture: list of capture videobuffers
86 * @lock: protects video buffer lists
87 * @active: active video buffer
88 * @idmac_channel: array of pointers to IPU DMAC DMA channels
89 * @soc_host: embedded soc_host object
90 */
91 struct mx3_camera_dev {
92 /*
93 * i.MX3x is only supposed to handle one camera on its Camera Sensor
94 * Interface. If anyone ever builds hardware to enable more than one
95 * camera _simultaneously_, they will have to modify this driver too
96 */
97 struct clk *clk;
98
99 void __iomem *base;
100
101 struct mx3_camera_pdata *pdata;
102
103 unsigned long platform_flags;
104 unsigned long mclk;
105 u16 width_flags; /* max 15 bits */
106
107 struct list_head capture;
108 spinlock_t lock; /* Protects video buffer lists */
109 struct mx3_camera_buffer *active;
110 size_t buf_total;
111 struct vb2_alloc_ctx *alloc_ctx;
112 enum v4l2_field field;
113 int sequence;
114
115 /* IDMAC / dmaengine interface */
116 struct idmac_channel *idmac_channel[1]; /* We need one channel */
117
118 struct soc_camera_host soc_host;
119 };
120
121 struct dma_chan_request {
122 struct mx3_camera_dev *mx3_cam;
123 enum ipu_channel id;
124 };
125
126 static u32 csi_reg_read(struct mx3_camera_dev *mx3, off_t reg)
127 {
128 return __raw_readl(mx3->base + reg);
129 }
130
131 static void csi_reg_write(struct mx3_camera_dev *mx3, u32 value, off_t reg)
132 {
133 __raw_writel(value, mx3->base + reg);
134 }
135
136 static struct mx3_camera_buffer *to_mx3_vb(struct vb2_buffer *vb)
137 {
138 return container_of(vb, struct mx3_camera_buffer, vb);
139 }
140
141 /* Called from the IPU IDMAC ISR */
142 static void mx3_cam_dma_done(void *arg)
143 {
144 struct idmac_tx_desc *desc = to_tx_desc(arg);
145 struct dma_chan *chan = desc->txd.chan;
146 struct idmac_channel *ichannel = to_idmac_chan(chan);
147 struct mx3_camera_dev *mx3_cam = ichannel->client;
148
149 dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n",
150 desc->txd.cookie, mx3_cam->active ? sg_dma_address(&mx3_cam->active->sg) : 0);
151
152 spin_lock(&mx3_cam->lock);
153 if (mx3_cam->active) {
154 struct vb2_buffer *vb = &mx3_cam->active->vb;
155 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
156
157 list_del_init(&buf->queue);
158 v4l2_get_timestamp(&vb->v4l2_buf.timestamp);
159 vb->v4l2_buf.field = mx3_cam->field;
160 vb->v4l2_buf.sequence = mx3_cam->sequence++;
161 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
162 }
163
164 if (list_empty(&mx3_cam->capture)) {
165 mx3_cam->active = NULL;
166 spin_unlock(&mx3_cam->lock);
167
168 /*
169 * stop capture - without further buffers IPU_CHA_BUF0_RDY will
170 * not get updated
171 */
172 return;
173 }
174
175 mx3_cam->active = list_entry(mx3_cam->capture.next,
176 struct mx3_camera_buffer, queue);
177 spin_unlock(&mx3_cam->lock);
178 }
179
180 /*
181 * Videobuf operations
182 */
183
184 /*
185 * Calculate the __buffer__ (not data) size and number of buffers.
186 */
187 static int mx3_videobuf_setup(struct vb2_queue *vq,
188 const struct v4l2_format *fmt,
189 unsigned int *count, unsigned int *num_planes,
190 unsigned int sizes[], void *alloc_ctxs[])
191 {
192 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
193 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
194 struct mx3_camera_dev *mx3_cam = ici->priv;
195
196 if (!mx3_cam->idmac_channel[0])
197 return -EINVAL;
198
199 if (fmt) {
200 const struct soc_camera_format_xlate *xlate = soc_camera_xlate_by_fourcc(icd,
201 fmt->fmt.pix.pixelformat);
202 unsigned int bytes_per_line;
203 int ret;
204
205 if (!xlate)
206 return -EINVAL;
207
208 ret = soc_mbus_bytes_per_line(fmt->fmt.pix.width,
209 xlate->host_fmt);
210 if (ret < 0)
211 return ret;
212
213 bytes_per_line = max_t(u32, fmt->fmt.pix.bytesperline, ret);
214
215 ret = soc_mbus_image_size(xlate->host_fmt, bytes_per_line,
216 fmt->fmt.pix.height);
217 if (ret < 0)
218 return ret;
219
220 sizes[0] = max_t(u32, fmt->fmt.pix.sizeimage, ret);
221 } else {
222 /* Called from VIDIOC_REQBUFS or in compatibility mode */
223 sizes[0] = icd->sizeimage;
224 }
225
226 alloc_ctxs[0] = mx3_cam->alloc_ctx;
227
228 if (!vq->num_buffers)
229 mx3_cam->sequence = 0;
230
231 if (!*count)
232 *count = 2;
233
234 /* If *num_planes != 0, we have already verified *count. */
235 if (!*num_planes &&
236 sizes[0] * *count + mx3_cam->buf_total > MAX_VIDEO_MEM * 1024 * 1024)
237 *count = (MAX_VIDEO_MEM * 1024 * 1024 - mx3_cam->buf_total) /
238 sizes[0];
239
240 *num_planes = 1;
241
242 return 0;
243 }
244
245 static enum pixel_fmt fourcc_to_ipu_pix(__u32 fourcc)
246 {
247 /* Add more formats as need arises and test possibilities appear... */
248 switch (fourcc) {
249 case V4L2_PIX_FMT_RGB24:
250 return IPU_PIX_FMT_RGB24;
251 case V4L2_PIX_FMT_UYVY:
252 case V4L2_PIX_FMT_RGB565:
253 default:
254 return IPU_PIX_FMT_GENERIC;
255 }
256 }
257
258 static void mx3_videobuf_queue(struct vb2_buffer *vb)
259 {
260 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
261 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
262 struct mx3_camera_dev *mx3_cam = ici->priv;
263 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
264 struct scatterlist *sg = &buf->sg;
265 struct dma_async_tx_descriptor *txd;
266 struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
267 struct idmac_video_param *video = &ichan->params.video;
268 const struct soc_mbus_pixelfmt *host_fmt = icd->current_fmt->host_fmt;
269 dma_cookie_t cookie;
270 size_t new_size;
271
272 new_size = icd->sizeimage;
273
274 if (vb2_plane_size(vb, 0) < new_size) {
275 dev_err(icd->parent, "Buffer #%d too small (%lu < %zu)\n",
276 vb->v4l2_buf.index, vb2_plane_size(vb, 0), new_size);
277 goto error;
278 }
279
280 if (!buf->txd) {
281 sg_dma_address(sg) = vb2_dma_contig_plane_dma_addr(vb, 0);
282 sg_dma_len(sg) = new_size;
283
284 txd = dmaengine_prep_slave_sg(
285 &ichan->dma_chan, sg, 1, DMA_DEV_TO_MEM,
286 DMA_PREP_INTERRUPT);
287 if (!txd)
288 goto error;
289
290 txd->callback_param = txd;
291 txd->callback = mx3_cam_dma_done;
292
293 buf->txd = txd;
294 } else {
295 txd = buf->txd;
296 }
297
298 vb2_set_plane_payload(vb, 0, new_size);
299
300 /* This is the configuration of one sg-element */
301 video->out_pixel_fmt = fourcc_to_ipu_pix(host_fmt->fourcc);
302
303 if (video->out_pixel_fmt == IPU_PIX_FMT_GENERIC) {
304 /*
305 * If the IPU DMA channel is configured to transfer generic
306 * 8-bit data, we have to set up the geometry parameters
307 * correctly, according to the current pixel format. The DMA
308 * horizontal parameters in this case are expressed in bytes,
309 * not in pixels.
310 */
311 video->out_width = icd->bytesperline;
312 video->out_height = icd->user_height;
313 video->out_stride = icd->bytesperline;
314 } else {
315 /*
316 * For IPU known formats the pixel unit will be managed
317 * successfully by the IPU code
318 */
319 video->out_width = icd->user_width;
320 video->out_height = icd->user_height;
321 video->out_stride = icd->user_width;
322 }
323
324 #ifdef DEBUG
325 /* helps to see what DMA actually has written */
326 if (vb2_plane_vaddr(vb, 0))
327 memset(vb2_plane_vaddr(vb, 0), 0xaa, vb2_get_plane_payload(vb, 0));
328 #endif
329
330 spin_lock_irq(&mx3_cam->lock);
331 list_add_tail(&buf->queue, &mx3_cam->capture);
332
333 if (!mx3_cam->active)
334 mx3_cam->active = buf;
335
336 spin_unlock_irq(&mx3_cam->lock);
337
338 cookie = txd->tx_submit(txd);
339 dev_dbg(icd->parent, "Submitted cookie %d DMA 0x%08x\n",
340 cookie, sg_dma_address(&buf->sg));
341
342 if (cookie >= 0)
343 return;
344
345 spin_lock_irq(&mx3_cam->lock);
346
347 /* Submit error */
348 list_del_init(&buf->queue);
349
350 if (mx3_cam->active == buf)
351 mx3_cam->active = NULL;
352
353 spin_unlock_irq(&mx3_cam->lock);
354 error:
355 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
356 }
357
358 static void mx3_videobuf_release(struct vb2_buffer *vb)
359 {
360 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
361 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
362 struct mx3_camera_dev *mx3_cam = ici->priv;
363 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
364 struct dma_async_tx_descriptor *txd = buf->txd;
365 unsigned long flags;
366
367 dev_dbg(icd->parent,
368 "Release%s DMA 0x%08x, queue %sempty\n",
369 mx3_cam->active == buf ? " active" : "", sg_dma_address(&buf->sg),
370 list_empty(&buf->queue) ? "" : "not ");
371
372 spin_lock_irqsave(&mx3_cam->lock, flags);
373
374 if (mx3_cam->active == buf)
375 mx3_cam->active = NULL;
376
377 /* Doesn't hurt also if the list is empty */
378 list_del_init(&buf->queue);
379
380 if (txd) {
381 buf->txd = NULL;
382 if (mx3_cam->idmac_channel[0])
383 async_tx_ack(txd);
384 }
385
386 spin_unlock_irqrestore(&mx3_cam->lock, flags);
387
388 mx3_cam->buf_total -= vb2_plane_size(vb, 0);
389 }
390
391 static int mx3_videobuf_init(struct vb2_buffer *vb)
392 {
393 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
394 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
395 struct mx3_camera_dev *mx3_cam = ici->priv;
396 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
397
398 if (!buf->txd) {
399 /* This is for locking debugging only */
400 INIT_LIST_HEAD(&buf->queue);
401 sg_init_table(&buf->sg, 1);
402
403 mx3_cam->buf_total += vb2_plane_size(vb, 0);
404 }
405
406 return 0;
407 }
408
409 static int mx3_stop_streaming(struct vb2_queue *q)
410 {
411 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
412 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
413 struct mx3_camera_dev *mx3_cam = ici->priv;
414 struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
415 struct mx3_camera_buffer *buf, *tmp;
416 unsigned long flags;
417
418 if (ichan) {
419 struct dma_chan *chan = &ichan->dma_chan;
420 chan->device->device_control(chan, DMA_PAUSE, 0);
421 }
422
423 spin_lock_irqsave(&mx3_cam->lock, flags);
424
425 mx3_cam->active = NULL;
426
427 list_for_each_entry_safe(buf, tmp, &mx3_cam->capture, queue) {
428 list_del_init(&buf->queue);
429 vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
430 }
431
432 spin_unlock_irqrestore(&mx3_cam->lock, flags);
433
434 return 0;
435 }
436
437 static struct vb2_ops mx3_videobuf_ops = {
438 .queue_setup = mx3_videobuf_setup,
439 .buf_queue = mx3_videobuf_queue,
440 .buf_cleanup = mx3_videobuf_release,
441 .buf_init = mx3_videobuf_init,
442 .wait_prepare = soc_camera_unlock,
443 .wait_finish = soc_camera_lock,
444 .stop_streaming = mx3_stop_streaming,
445 };
446
447 static int mx3_camera_init_videobuf(struct vb2_queue *q,
448 struct soc_camera_device *icd)
449 {
450 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
451 q->io_modes = VB2_MMAP | VB2_USERPTR;
452 q->drv_priv = icd;
453 q->ops = &mx3_videobuf_ops;
454 q->mem_ops = &vb2_dma_contig_memops;
455 q->buf_struct_size = sizeof(struct mx3_camera_buffer);
456 q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
457
458 return vb2_queue_init(q);
459 }
460
461 /* First part of ipu_csi_init_interface() */
462 static void mx3_camera_activate(struct mx3_camera_dev *mx3_cam)
463 {
464 u32 conf;
465 long rate;
466
467 /* Set default size: ipu_csi_set_window_size() */
468 csi_reg_write(mx3_cam, (640 - 1) | ((480 - 1) << 16), CSI_ACT_FRM_SIZE);
469 /* ...and position to 0:0: ipu_csi_set_window_pos() */
470 conf = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000;
471 csi_reg_write(mx3_cam, conf, CSI_OUT_FRM_CTRL);
472
473 /* We use only gated clock synchronisation mode so far */
474 conf = 0 << CSI_SENS_CONF_SENS_PRTCL_SHIFT;
475
476 /* Set generic data, platform-biggest bus-width */
477 conf |= CSI_SENS_CONF_DATA_FMT_BAYER;
478
479 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15)
480 conf |= 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
481 else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10)
482 conf |= 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
483 else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8)
484 conf |= 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
485 else/* if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)*/
486 conf |= 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
487
488 if (mx3_cam->platform_flags & MX3_CAMERA_CLK_SRC)
489 conf |= 1 << CSI_SENS_CONF_SENS_CLKSRC_SHIFT;
490 if (mx3_cam->platform_flags & MX3_CAMERA_EXT_VSYNC)
491 conf |= 1 << CSI_SENS_CONF_EXT_VSYNC_SHIFT;
492 if (mx3_cam->platform_flags & MX3_CAMERA_DP)
493 conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT;
494 if (mx3_cam->platform_flags & MX3_CAMERA_PCP)
495 conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT;
496 if (mx3_cam->platform_flags & MX3_CAMERA_HSP)
497 conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT;
498 if (mx3_cam->platform_flags & MX3_CAMERA_VSP)
499 conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT;
500
501 /* ipu_csi_init_interface() */
502 csi_reg_write(mx3_cam, conf, CSI_SENS_CONF);
503
504 clk_prepare_enable(mx3_cam->clk);
505 rate = clk_round_rate(mx3_cam->clk, mx3_cam->mclk);
506 dev_dbg(mx3_cam->soc_host.v4l2_dev.dev, "Set SENS_CONF to %x, rate %ld\n", conf, rate);
507 if (rate)
508 clk_set_rate(mx3_cam->clk, rate);
509 }
510
511 static int mx3_camera_add_device(struct soc_camera_device *icd)
512 {
513 dev_info(icd->parent, "MX3 Camera driver attached to camera %d\n",
514 icd->devnum);
515
516 return 0;
517 }
518
519 static void mx3_camera_remove_device(struct soc_camera_device *icd)
520 {
521 dev_info(icd->parent, "MX3 Camera driver detached from camera %d\n",
522 icd->devnum);
523 }
524
525 /* Called with .host_lock held */
526 static int mx3_camera_clock_start(struct soc_camera_host *ici)
527 {
528 struct mx3_camera_dev *mx3_cam = ici->priv;
529
530 mx3_camera_activate(mx3_cam);
531
532 mx3_cam->buf_total = 0;
533
534 return 0;
535 }
536
537 /* Called with .host_lock held */
538 static void mx3_camera_clock_stop(struct soc_camera_host *ici)
539 {
540 struct mx3_camera_dev *mx3_cam = ici->priv;
541 struct idmac_channel **ichan = &mx3_cam->idmac_channel[0];
542
543 if (*ichan) {
544 dma_release_channel(&(*ichan)->dma_chan);
545 *ichan = NULL;
546 }
547
548 clk_disable_unprepare(mx3_cam->clk);
549 }
550
551 static int test_platform_param(struct mx3_camera_dev *mx3_cam,
552 unsigned char buswidth, unsigned long *flags)
553 {
554 /*
555 * If requested data width is supported by the platform, use it or any
556 * possible lower value - i.MX31 is smart enough to shift bits
557 */
558 if (buswidth > fls(mx3_cam->width_flags))
559 return -EINVAL;
560
561 /*
562 * Platform specified synchronization and pixel clock polarities are
563 * only a recommendation and are only used during probing. MX3x
564 * camera interface only works in master mode, i.e., uses HSYNC and
565 * VSYNC signals from the sensor
566 */
567 *flags = V4L2_MBUS_MASTER |
568 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
569 V4L2_MBUS_HSYNC_ACTIVE_LOW |
570 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
571 V4L2_MBUS_VSYNC_ACTIVE_LOW |
572 V4L2_MBUS_PCLK_SAMPLE_RISING |
573 V4L2_MBUS_PCLK_SAMPLE_FALLING |
574 V4L2_MBUS_DATA_ACTIVE_HIGH |
575 V4L2_MBUS_DATA_ACTIVE_LOW;
576
577 return 0;
578 }
579
580 static int mx3_camera_try_bus_param(struct soc_camera_device *icd,
581 const unsigned int depth)
582 {
583 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
584 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
585 struct mx3_camera_dev *mx3_cam = ici->priv;
586 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
587 unsigned long bus_flags, common_flags;
588 int ret = test_platform_param(mx3_cam, depth, &bus_flags);
589
590 dev_dbg(icd->parent, "request bus width %d bit: %d\n", depth, ret);
591
592 if (ret < 0)
593 return ret;
594
595 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
596 if (!ret) {
597 common_flags = soc_mbus_config_compatible(&cfg,
598 bus_flags);
599 if (!common_flags) {
600 dev_warn(icd->parent,
601 "Flags incompatible: camera 0x%x, host 0x%lx\n",
602 cfg.flags, bus_flags);
603 return -EINVAL;
604 }
605 } else if (ret != -ENOIOCTLCMD) {
606 return ret;
607 }
608
609 return 0;
610 }
611
612 static bool chan_filter(struct dma_chan *chan, void *arg)
613 {
614 struct dma_chan_request *rq = arg;
615 struct mx3_camera_pdata *pdata;
616
617 if (!imx_dma_is_ipu(chan))
618 return false;
619
620 if (!rq)
621 return false;
622
623 pdata = rq->mx3_cam->soc_host.v4l2_dev.dev->platform_data;
624
625 return rq->id == chan->chan_id &&
626 pdata->dma_dev == chan->device->dev;
627 }
628
629 static const struct soc_mbus_pixelfmt mx3_camera_formats[] = {
630 {
631 .fourcc = V4L2_PIX_FMT_SBGGR8,
632 .name = "Bayer BGGR (sRGB) 8 bit",
633 .bits_per_sample = 8,
634 .packing = SOC_MBUS_PACKING_NONE,
635 .order = SOC_MBUS_ORDER_LE,
636 .layout = SOC_MBUS_LAYOUT_PACKED,
637 }, {
638 .fourcc = V4L2_PIX_FMT_GREY,
639 .name = "Monochrome 8 bit",
640 .bits_per_sample = 8,
641 .packing = SOC_MBUS_PACKING_NONE,
642 .order = SOC_MBUS_ORDER_LE,
643 .layout = SOC_MBUS_LAYOUT_PACKED,
644 },
645 };
646
647 /* This will be corrected as we get more formats */
648 static bool mx3_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
649 {
650 return fmt->packing == SOC_MBUS_PACKING_NONE ||
651 (fmt->bits_per_sample == 8 &&
652 fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
653 (fmt->bits_per_sample > 8 &&
654 fmt->packing == SOC_MBUS_PACKING_EXTEND16);
655 }
656
657 static int mx3_camera_get_formats(struct soc_camera_device *icd, unsigned int idx,
658 struct soc_camera_format_xlate *xlate)
659 {
660 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
661 struct device *dev = icd->parent;
662 int formats = 0, ret;
663 enum v4l2_mbus_pixelcode code;
664 const struct soc_mbus_pixelfmt *fmt;
665
666 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
667 if (ret < 0)
668 /* No more formats */
669 return 0;
670
671 fmt = soc_mbus_get_fmtdesc(code);
672 if (!fmt) {
673 dev_warn(icd->parent,
674 "Unsupported format code #%u: 0x%x\n", idx, code);
675 return 0;
676 }
677
678 /* This also checks support for the requested bits-per-sample */
679 ret = mx3_camera_try_bus_param(icd, fmt->bits_per_sample);
680 if (ret < 0)
681 return 0;
682
683 switch (code) {
684 case V4L2_MBUS_FMT_SBGGR10_1X10:
685 formats++;
686 if (xlate) {
687 xlate->host_fmt = &mx3_camera_formats[0];
688 xlate->code = code;
689 xlate++;
690 dev_dbg(dev, "Providing format %s using code 0x%x\n",
691 mx3_camera_formats[0].name, code);
692 }
693 break;
694 case V4L2_MBUS_FMT_Y10_1X10:
695 formats++;
696 if (xlate) {
697 xlate->host_fmt = &mx3_camera_formats[1];
698 xlate->code = code;
699 xlate++;
700 dev_dbg(dev, "Providing format %s using code 0x%x\n",
701 mx3_camera_formats[1].name, code);
702 }
703 break;
704 default:
705 if (!mx3_camera_packing_supported(fmt))
706 return 0;
707 }
708
709 /* Generic pass-through */
710 formats++;
711 if (xlate) {
712 xlate->host_fmt = fmt;
713 xlate->code = code;
714 dev_dbg(dev, "Providing format %c%c%c%c in pass-through mode\n",
715 (fmt->fourcc >> (0*8)) & 0xFF,
716 (fmt->fourcc >> (1*8)) & 0xFF,
717 (fmt->fourcc >> (2*8)) & 0xFF,
718 (fmt->fourcc >> (3*8)) & 0xFF);
719 xlate++;
720 }
721
722 return formats;
723 }
724
725 static void configure_geometry(struct mx3_camera_dev *mx3_cam,
726 unsigned int width, unsigned int height,
727 const struct soc_mbus_pixelfmt *fmt)
728 {
729 u32 ctrl, width_field, height_field;
730
731 if (fourcc_to_ipu_pix(fmt->fourcc) == IPU_PIX_FMT_GENERIC) {
732 /*
733 * As the CSI will be configured to output BAYER, here
734 * the width parameter count the number of samples to
735 * capture to complete the whole image width.
736 */
737 unsigned int num, den;
738 int ret = soc_mbus_samples_per_pixel(fmt, &num, &den);
739 BUG_ON(ret < 0);
740 width = width * num / den;
741 }
742
743 /* Setup frame size - this cannot be changed on-the-fly... */
744 width_field = width - 1;
745 height_field = height - 1;
746 csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_SENS_FRM_SIZE);
747
748 csi_reg_write(mx3_cam, width_field << 16, CSI_FLASH_STROBE_1);
749 csi_reg_write(mx3_cam, (height_field << 16) | 0x22, CSI_FLASH_STROBE_2);
750
751 csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_ACT_FRM_SIZE);
752
753 /* ...and position */
754 ctrl = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000;
755 /* Sensor does the cropping */
756 csi_reg_write(mx3_cam, ctrl | 0 | (0 << 8), CSI_OUT_FRM_CTRL);
757 }
758
759 static int acquire_dma_channel(struct mx3_camera_dev *mx3_cam)
760 {
761 dma_cap_mask_t mask;
762 struct dma_chan *chan;
763 struct idmac_channel **ichan = &mx3_cam->idmac_channel[0];
764 /* We have to use IDMAC_IC_7 for Bayer / generic data */
765 struct dma_chan_request rq = {.mx3_cam = mx3_cam,
766 .id = IDMAC_IC_7};
767
768 dma_cap_zero(mask);
769 dma_cap_set(DMA_SLAVE, mask);
770 dma_cap_set(DMA_PRIVATE, mask);
771 chan = dma_request_channel(mask, chan_filter, &rq);
772 if (!chan)
773 return -EBUSY;
774
775 *ichan = to_idmac_chan(chan);
776 (*ichan)->client = mx3_cam;
777
778 return 0;
779 }
780
781 /*
782 * FIXME: learn to use stride != width, then we can keep stride properly aligned
783 * and support arbitrary (even) widths.
784 */
785 static inline void stride_align(__u32 *width)
786 {
787 if (ALIGN(*width, 8) < 4096)
788 *width = ALIGN(*width, 8);
789 else
790 *width = *width & ~7;
791 }
792
793 /*
794 * As long as we don't implement host-side cropping and scaling, we can use
795 * default g_crop and cropcap from soc_camera.c
796 */
797 static int mx3_camera_set_crop(struct soc_camera_device *icd,
798 const struct v4l2_crop *a)
799 {
800 struct v4l2_crop a_writable = *a;
801 struct v4l2_rect *rect = &a_writable.c;
802 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
803 struct mx3_camera_dev *mx3_cam = ici->priv;
804 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
805 struct v4l2_mbus_framefmt mf;
806 int ret;
807
808 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
809 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
810
811 ret = v4l2_subdev_call(sd, video, s_crop, a);
812 if (ret < 0)
813 return ret;
814
815 /* The capture device might have changed its output sizes */
816 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
817 if (ret < 0)
818 return ret;
819
820 if (mf.code != icd->current_fmt->code)
821 return -EINVAL;
822
823 if (mf.width & 7) {
824 /* Ouch! We can only handle 8-byte aligned width... */
825 stride_align(&mf.width);
826 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
827 if (ret < 0)
828 return ret;
829 }
830
831 if (mf.width != icd->user_width || mf.height != icd->user_height)
832 configure_geometry(mx3_cam, mf.width, mf.height,
833 icd->current_fmt->host_fmt);
834
835 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
836 mf.width, mf.height);
837
838 icd->user_width = mf.width;
839 icd->user_height = mf.height;
840
841 return ret;
842 }
843
844 static int mx3_camera_set_fmt(struct soc_camera_device *icd,
845 struct v4l2_format *f)
846 {
847 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
848 struct mx3_camera_dev *mx3_cam = ici->priv;
849 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
850 const struct soc_camera_format_xlate *xlate;
851 struct v4l2_pix_format *pix = &f->fmt.pix;
852 struct v4l2_mbus_framefmt mf;
853 int ret;
854
855 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
856 if (!xlate) {
857 dev_warn(icd->parent, "Format %x not found\n",
858 pix->pixelformat);
859 return -EINVAL;
860 }
861
862 stride_align(&pix->width);
863 dev_dbg(icd->parent, "Set format %dx%d\n", pix->width, pix->height);
864
865 /*
866 * Might have to perform a complete interface initialisation like in
867 * ipu_csi_init_interface() in mxc_v4l2_s_param(). Also consider
868 * mxc_v4l2_s_fmt()
869 */
870
871 configure_geometry(mx3_cam, pix->width, pix->height, xlate->host_fmt);
872
873 mf.width = pix->width;
874 mf.height = pix->height;
875 mf.field = pix->field;
876 mf.colorspace = pix->colorspace;
877 mf.code = xlate->code;
878
879 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
880 if (ret < 0)
881 return ret;
882
883 if (mf.code != xlate->code)
884 return -EINVAL;
885
886 if (!mx3_cam->idmac_channel[0]) {
887 ret = acquire_dma_channel(mx3_cam);
888 if (ret < 0)
889 return ret;
890 }
891
892 pix->width = mf.width;
893 pix->height = mf.height;
894 pix->field = mf.field;
895 mx3_cam->field = mf.field;
896 pix->colorspace = mf.colorspace;
897 icd->current_fmt = xlate;
898
899 dev_dbg(icd->parent, "Sensor set %dx%d\n", pix->width, pix->height);
900
901 return ret;
902 }
903
904 static int mx3_camera_try_fmt(struct soc_camera_device *icd,
905 struct v4l2_format *f)
906 {
907 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
908 const struct soc_camera_format_xlate *xlate;
909 struct v4l2_pix_format *pix = &f->fmt.pix;
910 struct v4l2_mbus_framefmt mf;
911 __u32 pixfmt = pix->pixelformat;
912 int ret;
913
914 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
915 if (pixfmt && !xlate) {
916 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
917 return -EINVAL;
918 }
919
920 /* limit to MX3 hardware capabilities */
921 if (pix->height > 4096)
922 pix->height = 4096;
923 if (pix->width > 4096)
924 pix->width = 4096;
925
926 /* limit to sensor capabilities */
927 mf.width = pix->width;
928 mf.height = pix->height;
929 mf.field = pix->field;
930 mf.colorspace = pix->colorspace;
931 mf.code = xlate->code;
932
933 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
934 if (ret < 0)
935 return ret;
936
937 pix->width = mf.width;
938 pix->height = mf.height;
939 pix->colorspace = mf.colorspace;
940
941 switch (mf.field) {
942 case V4L2_FIELD_ANY:
943 pix->field = V4L2_FIELD_NONE;
944 break;
945 case V4L2_FIELD_NONE:
946 break;
947 default:
948 dev_err(icd->parent, "Field type %d unsupported.\n",
949 mf.field);
950 ret = -EINVAL;
951 }
952
953 return ret;
954 }
955
956 static int mx3_camera_reqbufs(struct soc_camera_device *icd,
957 struct v4l2_requestbuffers *p)
958 {
959 return 0;
960 }
961
962 static unsigned int mx3_camera_poll(struct file *file, poll_table *pt)
963 {
964 struct soc_camera_device *icd = file->private_data;
965
966 return vb2_poll(&icd->vb2_vidq, file, pt);
967 }
968
969 static int mx3_camera_querycap(struct soc_camera_host *ici,
970 struct v4l2_capability *cap)
971 {
972 /* cap->name is set by the firendly caller:-> */
973 strlcpy(cap->card, "i.MX3x Camera", sizeof(cap->card));
974 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
975
976 return 0;
977 }
978
979 static int mx3_camera_set_bus_param(struct soc_camera_device *icd)
980 {
981 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
982 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
983 struct mx3_camera_dev *mx3_cam = ici->priv;
984 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
985 u32 pixfmt = icd->current_fmt->host_fmt->fourcc;
986 unsigned long bus_flags, common_flags;
987 u32 dw, sens_conf;
988 const struct soc_mbus_pixelfmt *fmt;
989 int buswidth;
990 int ret;
991 const struct soc_camera_format_xlate *xlate;
992 struct device *dev = icd->parent;
993
994 fmt = soc_mbus_get_fmtdesc(icd->current_fmt->code);
995 if (!fmt)
996 return -EINVAL;
997
998 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
999 if (!xlate) {
1000 dev_warn(dev, "Format %x not found\n", pixfmt);
1001 return -EINVAL;
1002 }
1003
1004 buswidth = fmt->bits_per_sample;
1005 ret = test_platform_param(mx3_cam, buswidth, &bus_flags);
1006
1007 dev_dbg(dev, "requested bus width %d bit: %d\n", buswidth, ret);
1008
1009 if (ret < 0)
1010 return ret;
1011
1012 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1013 if (!ret) {
1014 common_flags = soc_mbus_config_compatible(&cfg,
1015 bus_flags);
1016 if (!common_flags) {
1017 dev_warn(icd->parent,
1018 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1019 cfg.flags, bus_flags);
1020 return -EINVAL;
1021 }
1022 } else if (ret != -ENOIOCTLCMD) {
1023 return ret;
1024 } else {
1025 common_flags = bus_flags;
1026 }
1027
1028 dev_dbg(dev, "Flags cam: 0x%x host: 0x%lx common: 0x%lx\n",
1029 cfg.flags, bus_flags, common_flags);
1030
1031 /* Make choices, based on platform preferences */
1032 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1033 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1034 if (mx3_cam->platform_flags & MX3_CAMERA_HSP)
1035 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1036 else
1037 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1038 }
1039
1040 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1041 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1042 if (mx3_cam->platform_flags & MX3_CAMERA_VSP)
1043 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1044 else
1045 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1046 }
1047
1048 if ((common_flags & V4L2_MBUS_DATA_ACTIVE_HIGH) &&
1049 (common_flags & V4L2_MBUS_DATA_ACTIVE_LOW)) {
1050 if (mx3_cam->platform_flags & MX3_CAMERA_DP)
1051 common_flags &= ~V4L2_MBUS_DATA_ACTIVE_HIGH;
1052 else
1053 common_flags &= ~V4L2_MBUS_DATA_ACTIVE_LOW;
1054 }
1055
1056 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1057 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1058 if (mx3_cam->platform_flags & MX3_CAMERA_PCP)
1059 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1060 else
1061 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1062 }
1063
1064 cfg.flags = common_flags;
1065 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
1066 if (ret < 0 && ret != -ENOIOCTLCMD) {
1067 dev_dbg(dev, "camera s_mbus_config(0x%lx) returned %d\n",
1068 common_flags, ret);
1069 return ret;
1070 }
1071
1072 /*
1073 * So far only gated clock mode is supported. Add a line
1074 * (3 << CSI_SENS_CONF_SENS_PRTCL_SHIFT) |
1075 * below and select the required mode when supporting other
1076 * synchronisation protocols.
1077 */
1078 sens_conf = csi_reg_read(mx3_cam, CSI_SENS_CONF) &
1079 ~((1 << CSI_SENS_CONF_VSYNC_POL_SHIFT) |
1080 (1 << CSI_SENS_CONF_HSYNC_POL_SHIFT) |
1081 (1 << CSI_SENS_CONF_DATA_POL_SHIFT) |
1082 (1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT) |
1083 (3 << CSI_SENS_CONF_DATA_FMT_SHIFT) |
1084 (3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT));
1085
1086 /* TODO: Support RGB and YUV formats */
1087
1088 /* This has been set in mx3_camera_activate(), but we clear it above */
1089 sens_conf |= CSI_SENS_CONF_DATA_FMT_BAYER;
1090
1091 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1092 sens_conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT;
1093 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1094 sens_conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT;
1095 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1096 sens_conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT;
1097 if (common_flags & V4L2_MBUS_DATA_ACTIVE_LOW)
1098 sens_conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT;
1099
1100 /* Just do what we're asked to do */
1101 switch (xlate->host_fmt->bits_per_sample) {
1102 case 4:
1103 dw = 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1104 break;
1105 case 8:
1106 dw = 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1107 break;
1108 case 10:
1109 dw = 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1110 break;
1111 default:
1112 /*
1113 * Actually it can only be 15 now, default is just to silence
1114 * compiler warnings
1115 */
1116 case 15:
1117 dw = 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1118 }
1119
1120 csi_reg_write(mx3_cam, sens_conf | dw, CSI_SENS_CONF);
1121
1122 dev_dbg(dev, "Set SENS_CONF to %x\n", sens_conf | dw);
1123
1124 return 0;
1125 }
1126
1127 static struct soc_camera_host_ops mx3_soc_camera_host_ops = {
1128 .owner = THIS_MODULE,
1129 .add = mx3_camera_add_device,
1130 .remove = mx3_camera_remove_device,
1131 .clock_start = mx3_camera_clock_start,
1132 .clock_stop = mx3_camera_clock_stop,
1133 .set_crop = mx3_camera_set_crop,
1134 .set_fmt = mx3_camera_set_fmt,
1135 .try_fmt = mx3_camera_try_fmt,
1136 .get_formats = mx3_camera_get_formats,
1137 .init_videobuf2 = mx3_camera_init_videobuf,
1138 .reqbufs = mx3_camera_reqbufs,
1139 .poll = mx3_camera_poll,
1140 .querycap = mx3_camera_querycap,
1141 .set_bus_param = mx3_camera_set_bus_param,
1142 };
1143
1144 static int mx3_camera_probe(struct platform_device *pdev)
1145 {
1146 struct mx3_camera_pdata *pdata = pdev->dev.platform_data;
1147 struct mx3_camera_dev *mx3_cam;
1148 struct resource *res;
1149 void __iomem *base;
1150 int err = 0;
1151 struct soc_camera_host *soc_host;
1152
1153 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1154 base = devm_ioremap_resource(&pdev->dev, res);
1155 if (IS_ERR(base))
1156 return PTR_ERR(base);
1157
1158 if (!pdata)
1159 return -EINVAL;
1160
1161 mx3_cam = devm_kzalloc(&pdev->dev, sizeof(*mx3_cam), GFP_KERNEL);
1162 if (!mx3_cam) {
1163 dev_err(&pdev->dev, "Could not allocate mx3 camera object\n");
1164 return -ENOMEM;
1165 }
1166
1167 mx3_cam->clk = devm_clk_get(&pdev->dev, NULL);
1168 if (IS_ERR(mx3_cam->clk))
1169 return PTR_ERR(mx3_cam->clk);
1170
1171 mx3_cam->pdata = pdata;
1172 mx3_cam->platform_flags = pdata->flags;
1173 if (!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_MASK)) {
1174 /*
1175 * Platform hasn't set available data widths. This is bad.
1176 * Warn and use a default.
1177 */
1178 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1179 "data widths, using default 8 bit\n");
1180 mx3_cam->platform_flags |= MX3_CAMERA_DATAWIDTH_8;
1181 }
1182 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)
1183 mx3_cam->width_flags = 1 << 3;
1184 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8)
1185 mx3_cam->width_flags |= 1 << 7;
1186 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10)
1187 mx3_cam->width_flags |= 1 << 9;
1188 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15)
1189 mx3_cam->width_flags |= 1 << 14;
1190
1191 mx3_cam->mclk = pdata->mclk_10khz * 10000;
1192 if (!mx3_cam->mclk) {
1193 dev_warn(&pdev->dev,
1194 "mclk_10khz == 0! Please, fix your platform data. "
1195 "Using default 20MHz\n");
1196 mx3_cam->mclk = 20000000;
1197 }
1198
1199 /* list of video-buffers */
1200 INIT_LIST_HEAD(&mx3_cam->capture);
1201 spin_lock_init(&mx3_cam->lock);
1202
1203 mx3_cam->base = base;
1204
1205 soc_host = &mx3_cam->soc_host;
1206 soc_host->drv_name = MX3_CAM_DRV_NAME;
1207 soc_host->ops = &mx3_soc_camera_host_ops;
1208 soc_host->priv = mx3_cam;
1209 soc_host->v4l2_dev.dev = &pdev->dev;
1210 soc_host->nr = pdev->id;
1211
1212 mx3_cam->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1213 if (IS_ERR(mx3_cam->alloc_ctx))
1214 return PTR_ERR(mx3_cam->alloc_ctx);
1215
1216 if (pdata->asd_sizes) {
1217 soc_host->asd = pdata->asd;
1218 soc_host->asd_sizes = pdata->asd_sizes;
1219 }
1220
1221 err = soc_camera_host_register(soc_host);
1222 if (err)
1223 goto ecamhostreg;
1224
1225 /* IDMAC interface */
1226 dmaengine_get();
1227
1228 return 0;
1229
1230 ecamhostreg:
1231 vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx);
1232 return err;
1233 }
1234
1235 static int mx3_camera_remove(struct platform_device *pdev)
1236 {
1237 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1238 struct mx3_camera_dev *mx3_cam = container_of(soc_host,
1239 struct mx3_camera_dev, soc_host);
1240
1241 soc_camera_host_unregister(soc_host);
1242
1243 /*
1244 * The channel has either not been allocated,
1245 * or should have been released
1246 */
1247 if (WARN_ON(mx3_cam->idmac_channel[0]))
1248 dma_release_channel(&mx3_cam->idmac_channel[0]->dma_chan);
1249
1250 vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx);
1251
1252 dmaengine_put();
1253
1254 return 0;
1255 }
1256
1257 static struct platform_driver mx3_camera_driver = {
1258 .driver = {
1259 .name = MX3_CAM_DRV_NAME,
1260 .owner = THIS_MODULE,
1261 },
1262 .probe = mx3_camera_probe,
1263 .remove = mx3_camera_remove,
1264 };
1265
1266 module_platform_driver(mx3_camera_driver);
1267
1268 MODULE_DESCRIPTION("i.MX3x SoC Camera Host driver");
1269 MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
1270 MODULE_LICENSE("GPL v2");
1271 MODULE_VERSION("0.2.3");
1272 MODULE_ALIAS("platform:" MX3_CAM_DRV_NAME);
Linux with added FPC-III support