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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / mmc / host / rtsx_pci_sdmmc.c
blob2985efd7bdb2b2ec83cc613f26592feb2ed8de72
1 /* Realtek PCI-Express SD/MMC Card Interface driver
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 */
21
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/highmem.h>
25 #include <linux/delay.h>
26 #include <linux/platform_device.h>
27 #include <linux/mmc/host.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/sd.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mfd/rtsx_pci.h>
32 #include <asm/unaligned.h>
33
34 /* SD Tuning Data Structure
35 * Record continuous timing phase path
36 */
37 struct timing_phase_path {
38 int start;
39 int end;
40 int mid;
41 int len;
42 };
43
44 struct realtek_pci_sdmmc {
45 struct platform_device *pdev;
46 struct rtsx_pcr *pcr;
47 struct mmc_host *mmc;
48 struct mmc_request *mrq;
49
50 struct mutex host_mutex;
51
52 u8 ssc_depth;
53 unsigned int clock;
54 bool vpclk;
55 bool double_clk;
56 bool eject;
57 bool initial_mode;
58 int power_state;
59 #define SDMMC_POWER_ON 1
60 #define SDMMC_POWER_OFF 0
61 };
62
63 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
64 {
65 return &(host->pdev->dev);
66 }
67
68 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
69 {
70 rtsx_pci_write_register(host->pcr, CARD_STOP,
71 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
72 }
73
74 #ifdef DEBUG
75 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
76 {
77 struct rtsx_pcr *pcr = host->pcr;
78 u16 i;
79 u8 *ptr;
80
81 /* Print SD host internal registers */
82 rtsx_pci_init_cmd(pcr);
83 for (i = 0xFDA0; i <= 0xFDAE; i++)
84 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
85 for (i = 0xFD52; i <= 0xFD69; i++)
86 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
87 rtsx_pci_send_cmd(pcr, 100);
88
89 ptr = rtsx_pci_get_cmd_data(pcr);
90 for (i = 0xFDA0; i <= 0xFDAE; i++)
91 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
92 for (i = 0xFD52; i <= 0xFD69; i++)
93 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
94 }
95 #else
96 #define sd_print_debug_regs(host)
97 #endif /* DEBUG */
98
99 static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
100 u8 *buf, int buf_len, int timeout)
101 {
102 struct rtsx_pcr *pcr = host->pcr;
103 int err, i;
104 u8 trans_mode;
105
106 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40);
107
108 if (!buf)
109 buf_len = 0;
110
111 if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK)
112 trans_mode = SD_TM_AUTO_TUNING;
113 else
114 trans_mode = SD_TM_NORMAL_READ;
115
116 rtsx_pci_init_cmd(pcr);
117
118 for (i = 0; i < 5; i++)
119 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]);
120
121 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
122 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
123 0xFF, (u8)(byte_cnt >> 8));
124 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
125 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
126
127 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
128 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
129 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
130 if (trans_mode != SD_TM_AUTO_TUNING)
131 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
132 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
133
134 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
135 0xFF, trans_mode | SD_TRANSFER_START);
136 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
137 SD_TRANSFER_END, SD_TRANSFER_END);
138
139 err = rtsx_pci_send_cmd(pcr, timeout);
140 if (err < 0) {
141 sd_print_debug_regs(host);
142 dev_dbg(sdmmc_dev(host),
143 "rtsx_pci_send_cmd fail (err = %d)\n", err);
144 return err;
145 }
146
147 if (buf && buf_len) {
148 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
149 if (err < 0) {
150 dev_dbg(sdmmc_dev(host),
151 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
152 return err;
153 }
154 }
155
156 return 0;
157 }
158
159 static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
160 u8 *buf, int buf_len, int timeout)
161 {
162 struct rtsx_pcr *pcr = host->pcr;
163 int err, i;
164 u8 trans_mode;
165
166 if (!buf)
167 buf_len = 0;
168
169 if (buf && buf_len) {
170 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
171 if (err < 0) {
172 dev_dbg(sdmmc_dev(host),
173 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
174 return err;
175 }
176 }
177
178 trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3;
179 rtsx_pci_init_cmd(pcr);
180
181 if (cmd) {
182 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__,
183 cmd[0] - 0x40);
184
185 for (i = 0; i < 5; i++)
186 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
187 SD_CMD0 + i, 0xFF, cmd[i]);
188 }
189
190 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
191 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
192 0xFF, (u8)(byte_cnt >> 8));
193 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
194 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
195
196 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
197 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
198 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
199
200 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
201 trans_mode | SD_TRANSFER_START);
202 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
203 SD_TRANSFER_END, SD_TRANSFER_END);
204
205 err = rtsx_pci_send_cmd(pcr, timeout);
206 if (err < 0) {
207 sd_print_debug_regs(host);
208 dev_dbg(sdmmc_dev(host),
209 "rtsx_pci_send_cmd fail (err = %d)\n", err);
210 return err;
211 }
212
213 return 0;
214 }
215
216 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
217 struct mmc_command *cmd)
218 {
219 struct rtsx_pcr *pcr = host->pcr;
220 u8 cmd_idx = (u8)cmd->opcode;
221 u32 arg = cmd->arg;
222 int err = 0;
223 int timeout = 100;
224 int i;
225 u8 *ptr;
226 int stat_idx = 0;
227 u8 rsp_type;
228 int rsp_len = 5;
229 bool clock_toggled = false;
230
231 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
232 __func__, cmd_idx, arg);
233
234 /* Response type:
235 * R0
236 * R1, R5, R6, R7
237 * R1b
238 * R2
239 * R3, R4
240 */
241 switch (mmc_resp_type(cmd)) {
242 case MMC_RSP_NONE:
243 rsp_type = SD_RSP_TYPE_R0;
244 rsp_len = 0;
245 break;
246 case MMC_RSP_R1:
247 rsp_type = SD_RSP_TYPE_R1;
248 break;
249 case MMC_RSP_R1 & ~MMC_RSP_CRC:
250 rsp_type = SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
251 break;
252 case MMC_RSP_R1B:
253 rsp_type = SD_RSP_TYPE_R1b;
254 break;
255 case MMC_RSP_R2:
256 rsp_type = SD_RSP_TYPE_R2;
257 rsp_len = 16;
258 break;
259 case MMC_RSP_R3:
260 rsp_type = SD_RSP_TYPE_R3;
261 break;
262 default:
263 dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n");
264 err = -EINVAL;
265 goto out;
266 }
267
268 if (rsp_type == SD_RSP_TYPE_R1b)
269 timeout = 3000;
270
271 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
272 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
273 0xFF, SD_CLK_TOGGLE_EN);
274 if (err < 0)
275 goto out;
276
277 clock_toggled = true;
278 }
279
280 rtsx_pci_init_cmd(pcr);
281
282 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
283 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24));
284 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16));
285 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8));
286 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg);
287
288 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
289 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
290 0x01, PINGPONG_BUFFER);
291 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
292 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
293 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
294 SD_TRANSFER_END | SD_STAT_IDLE,
295 SD_TRANSFER_END | SD_STAT_IDLE);
296
297 if (rsp_type == SD_RSP_TYPE_R2) {
298 /* Read data from ping-pong buffer */
299 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
300 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
301 stat_idx = 16;
302 } else if (rsp_type != SD_RSP_TYPE_R0) {
303 /* Read data from SD_CMDx registers */
304 for (i = SD_CMD0; i <= SD_CMD4; i++)
305 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
306 stat_idx = 5;
307 }
308
309 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
310
311 err = rtsx_pci_send_cmd(pcr, timeout);
312 if (err < 0) {
313 sd_print_debug_regs(host);
314 sd_clear_error(host);
315 dev_dbg(sdmmc_dev(host),
316 "rtsx_pci_send_cmd error (err = %d)\n", err);
317 goto out;
318 }
319
320 if (rsp_type == SD_RSP_TYPE_R0) {
321 err = 0;
322 goto out;
323 }
324
325 /* Eliminate returned value of CHECK_REG_CMD */
326 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
327
328 /* Check (Start,Transmission) bit of Response */
329 if ((ptr[0] & 0xC0) != 0) {
330 err = -EILSEQ;
331 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
332 goto out;
333 }
334
335 /* Check CRC7 */
336 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
337 if (ptr[stat_idx] & SD_CRC7_ERR) {
338 err = -EILSEQ;
339 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
340 goto out;
341 }
342 }
343
344 if (rsp_type == SD_RSP_TYPE_R2) {
345 /*
346 * The controller offloads the last byte {CRC-7, end bit 1'b1}
347 * of response type R2. Assign dummy CRC, 0, and end bit to the
348 * byte(ptr[16], goes into the LSB of resp[3] later).
349 */
350 ptr[16] = 1;
351
352 for (i = 0; i < 4; i++) {
353 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
354 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
355 i, cmd->resp[i]);
356 }
357 } else {
358 cmd->resp[0] = get_unaligned_be32(ptr + 1);
359 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
360 cmd->resp[0]);
361 }
362
363 out:
364 cmd->error = err;
365
366 if (err && clock_toggled)
367 rtsx_pci_write_register(pcr, SD_BUS_STAT,
368 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
369 }
370
371 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
372 {
373 struct rtsx_pcr *pcr = host->pcr;
374 struct mmc_host *mmc = host->mmc;
375 struct mmc_card *card = mmc->card;
376 struct mmc_data *data = mrq->data;
377 int uhs = mmc_sd_card_uhs(card);
378 int read = (data->flags & MMC_DATA_READ) ? 1 : 0;
379 u8 cfg2, trans_mode;
380 int err;
381 size_t data_len = data->blksz * data->blocks;
382
383 if (read) {
384 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
385 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0;
386 trans_mode = SD_TM_AUTO_READ_3;
387 } else {
388 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
389 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
390 trans_mode = SD_TM_AUTO_WRITE_3;
391 }
392
393 if (!uhs)
394 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
395
396 rtsx_pci_init_cmd(pcr);
397
398 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
399 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
400 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L,
401 0xFF, (u8)data->blocks);
402 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H,
403 0xFF, (u8)(data->blocks >> 8));
404
405 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
406 DMA_DONE_INT, DMA_DONE_INT);
407 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
408 0xFF, (u8)(data_len >> 24));
409 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
410 0xFF, (u8)(data_len >> 16));
411 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
412 0xFF, (u8)(data_len >> 8));
413 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
414 if (read) {
415 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
416 0x03 | DMA_PACK_SIZE_MASK,
417 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
418 } else {
419 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
420 0x03 | DMA_PACK_SIZE_MASK,
421 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
422 }
423
424 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
425 0x01, RING_BUFFER);
426
427 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
428 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
429 trans_mode | SD_TRANSFER_START);
430 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
431 SD_TRANSFER_END, SD_TRANSFER_END);
432
433 rtsx_pci_send_cmd_no_wait(pcr);
434
435 err = rtsx_pci_transfer_data(pcr, data->sg, data->sg_len, read, 10000);
436 if (err < 0) {
437 sd_clear_error(host);
438 return err;
439 }
440
441 return 0;
442 }
443
444 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
445 {
446 rtsx_pci_write_register(host->pcr, SD_CFG1,
447 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
448 }
449
450 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
451 {
452 rtsx_pci_write_register(host->pcr, SD_CFG1,
453 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
454 }
455
456 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
457 struct mmc_request *mrq)
458 {
459 struct mmc_command *cmd = mrq->cmd;
460 struct mmc_data *data = mrq->data;
461 u8 _cmd[5], *buf;
462
463 _cmd[0] = 0x40 | (u8)cmd->opcode;
464 put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1]));
465
466 buf = kzalloc(data->blksz, GFP_NOIO);
467 if (!buf) {
468 cmd->error = -ENOMEM;
469 return;
470 }
471
472 if (data->flags & MMC_DATA_READ) {
473 if (host->initial_mode)
474 sd_disable_initial_mode(host);
475
476 cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf,
477 data->blksz, 200);
478
479 if (host->initial_mode)
480 sd_enable_initial_mode(host);
481
482 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
483 } else {
484 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
485
486 cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf,
487 data->blksz, 200);
488 }
489
490 kfree(buf);
491 }
492
493 static int sd_change_phase(struct realtek_pci_sdmmc *host,
494 u8 sample_point, bool rx)
495 {
496 struct rtsx_pcr *pcr = host->pcr;
497 int err;
498
499 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
500 __func__, rx ? "RX" : "TX", sample_point);
501
502 rtsx_pci_init_cmd(pcr);
503
504 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
505 if (rx)
506 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
507 SD_VPRX_CTL, 0x1F, sample_point);
508 else
509 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
510 SD_VPTX_CTL, 0x1F, sample_point);
511 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
512 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
513 PHASE_NOT_RESET, PHASE_NOT_RESET);
514 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
515 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
516
517 err = rtsx_pci_send_cmd(pcr, 100);
518 if (err < 0)
519 return err;
520
521 return 0;
522 }
523
524 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
525 {
526 struct timing_phase_path path[MAX_PHASE + 1];
527 int i, j, cont_path_cnt;
528 int new_block, max_len, final_path_idx;
529 u8 final_phase = 0xFF;
530
531 /* Parse phase_map, take it as a bit-ring */
532 cont_path_cnt = 0;
533 new_block = 1;
534 j = 0;
535 for (i = 0; i < MAX_PHASE + 1; i++) {
536 if (phase_map & (1 << i)) {
537 if (new_block) {
538 new_block = 0;
539 j = cont_path_cnt++;
540 path[j].start = i;
541 path[j].end = i;
542 } else {
543 path[j].end = i;
544 }
545 } else {
546 new_block = 1;
547 if (cont_path_cnt) {
548 /* Calculate path length and middle point */
549 int idx = cont_path_cnt - 1;
550 path[idx].len =
551 path[idx].end - path[idx].start + 1;
552 path[idx].mid =
553 path[idx].start + path[idx].len / 2;
554 }
555 }
556 }
557
558 if (cont_path_cnt == 0) {
559 dev_dbg(sdmmc_dev(host), "No continuous phase path\n");
560 goto finish;
561 } else {
562 /* Calculate last continuous path length and middle point */
563 int idx = cont_path_cnt - 1;
564 path[idx].len = path[idx].end - path[idx].start + 1;
565 path[idx].mid = path[idx].start + path[idx].len / 2;
566 }
567
568 /* Connect the first and last continuous paths if they are adjacent */
569 if (!path[0].start && (path[cont_path_cnt - 1].end == MAX_PHASE)) {
570 /* Using negative index */
571 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
572 path[0].len += path[cont_path_cnt - 1].len;
573 path[0].mid = path[0].start + path[0].len / 2;
574 /* Convert negative middle point index to positive one */
575 if (path[0].mid < 0)
576 path[0].mid += MAX_PHASE + 1;
577 cont_path_cnt--;
578 }
579
580 /* Choose the longest continuous phase path */
581 max_len = 0;
582 final_phase = 0;
583 final_path_idx = 0;
584 for (i = 0; i < cont_path_cnt; i++) {
585 if (path[i].len > max_len) {
586 max_len = path[i].len;
587 final_phase = (u8)path[i].mid;
588 final_path_idx = i;
589 }
590
591 dev_dbg(sdmmc_dev(host), "path[%d].start = %d\n",
592 i, path[i].start);
593 dev_dbg(sdmmc_dev(host), "path[%d].end = %d\n",
594 i, path[i].end);
595 dev_dbg(sdmmc_dev(host), "path[%d].len = %d\n",
596 i, path[i].len);
597 dev_dbg(sdmmc_dev(host), "path[%d].mid = %d\n",
598 i, path[i].mid);
599 }
600
601 finish:
602 dev_dbg(sdmmc_dev(host), "Final chosen phase: %d\n", final_phase);
603 return final_phase;
604 }
605
606 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
607 {
608 int err, i;
609 u8 val = 0;
610
611 for (i = 0; i < 100; i++) {
612 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
613 if (val & SD_DATA_IDLE)
614 return;
615
616 udelay(100);
617 }
618 }
619
620 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
621 u8 opcode, u8 sample_point)
622 {
623 int err;
624 u8 cmd[5] = {0};
625
626 err = sd_change_phase(host, sample_point, true);
627 if (err < 0)
628 return err;
629
630 cmd[0] = 0x40 | opcode;
631 err = sd_read_data(host, cmd, 0x40, NULL, 0, 100);
632 if (err < 0) {
633 /* Wait till SD DATA IDLE */
634 sd_wait_data_idle(host);
635 sd_clear_error(host);
636 return err;
637 }
638
639 return 0;
640 }
641
642 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
643 u8 opcode, u32 *phase_map)
644 {
645 int err, i;
646 u32 raw_phase_map = 0;
647
648 for (i = MAX_PHASE; i >= 0; i--) {
649 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
650 if (err == 0)
651 raw_phase_map |= 1 << i;
652 }
653
654 if (phase_map)
655 *phase_map = raw_phase_map;
656
657 return 0;
658 }
659
660 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
661 {
662 int err, i;
663 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
664 u8 final_phase;
665
666 for (i = 0; i < RX_TUNING_CNT; i++) {
667 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
668 if (err < 0)
669 return err;
670
671 if (raw_phase_map[i] == 0)
672 break;
673 }
674
675 phase_map = 0xFFFFFFFF;
676 for (i = 0; i < RX_TUNING_CNT; i++) {
677 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
678 i, raw_phase_map[i]);
679 phase_map &= raw_phase_map[i];
680 }
681 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
682
683 if (phase_map) {
684 final_phase = sd_search_final_phase(host, phase_map);
685 if (final_phase == 0xFF)
686 return -EINVAL;
687
688 err = sd_change_phase(host, final_phase, true);
689 if (err < 0)
690 return err;
691 } else {
692 return -EINVAL;
693 }
694
695 return 0;
696 }
697
698 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
699 {
700 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
701 struct rtsx_pcr *pcr = host->pcr;
702 struct mmc_command *cmd = mrq->cmd;
703 struct mmc_data *data = mrq->data;
704 unsigned int data_size = 0;
705 int err;
706
707 if (host->eject) {
708 cmd->error = -ENOMEDIUM;
709 goto finish;
710 }
711
712 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
713 if (err) {
714 cmd->error = err;
715 goto finish;
716 }
717
718 mutex_lock(&pcr->pcr_mutex);
719
720 rtsx_pci_start_run(pcr);
721
722 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
723 host->initial_mode, host->double_clk, host->vpclk);
724 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
725 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
726 CARD_SHARE_MASK, CARD_SHARE_48_SD);
727
728 mutex_lock(&host->host_mutex);
729 host->mrq = mrq;
730 mutex_unlock(&host->host_mutex);
731
732 if (mrq->data)
733 data_size = data->blocks * data->blksz;
734
735 if (!data_size || mmc_op_multi(cmd->opcode) ||
736 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
737 (cmd->opcode == MMC_WRITE_BLOCK)) {
738 sd_send_cmd_get_rsp(host, cmd);
739
740 if (!cmd->error && data_size) {
741 sd_rw_multi(host, mrq);
742
743 if (mmc_op_multi(cmd->opcode) && mrq->stop)
744 sd_send_cmd_get_rsp(host, mrq->stop);
745 }
746 } else {
747 sd_normal_rw(host, mrq);
748 }
749
750 if (mrq->data) {
751 if (cmd->error || data->error)
752 data->bytes_xfered = 0;
753 else
754 data->bytes_xfered = data->blocks * data->blksz;
755 }
756
757 mutex_unlock(&pcr->pcr_mutex);
758
759 finish:
760 if (cmd->error)
761 dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error);
762
763 mutex_lock(&host->host_mutex);
764 host->mrq = NULL;
765 mutex_unlock(&host->host_mutex);
766
767 mmc_request_done(mmc, mrq);
768 }
769
770 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
771 unsigned char bus_width)
772 {
773 int err = 0;
774 u8 width[] = {
775 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
776 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
777 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
778 };
779
780 if (bus_width <= MMC_BUS_WIDTH_8)
781 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
782 0x03, width[bus_width]);
783
784 return err;
785 }
786
787 static int sd_power_on(struct realtek_pci_sdmmc *host)
788 {
789 struct rtsx_pcr *pcr = host->pcr;
790 int err;
791
792 if (host->power_state == SDMMC_POWER_ON)
793 return 0;
794
795 rtsx_pci_init_cmd(pcr);
796 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
797 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
798 CARD_SHARE_MASK, CARD_SHARE_48_SD);
799 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
800 SD_CLK_EN, SD_CLK_EN);
801 err = rtsx_pci_send_cmd(pcr, 100);
802 if (err < 0)
803 return err;
804
805 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
806 if (err < 0)
807 return err;
808
809 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
810 if (err < 0)
811 return err;
812
813 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
814 if (err < 0)
815 return err;
816
817 host->power_state = SDMMC_POWER_ON;
818 return 0;
819 }
820
821 static int sd_power_off(struct realtek_pci_sdmmc *host)
822 {
823 struct rtsx_pcr *pcr = host->pcr;
824 int err;
825
826 host->power_state = SDMMC_POWER_OFF;
827
828 rtsx_pci_init_cmd(pcr);
829
830 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
831 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
832
833 err = rtsx_pci_send_cmd(pcr, 100);
834 if (err < 0)
835 return err;
836
837 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
838 if (err < 0)
839 return err;
840
841 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
842 }
843
844 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
845 unsigned char power_mode)
846 {
847 int err;
848
849 if (power_mode == MMC_POWER_OFF)
850 err = sd_power_off(host);
851 else
852 err = sd_power_on(host);
853
854 return err;
855 }
856
857 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
858 {
859 struct rtsx_pcr *pcr = host->pcr;
860 int err = 0;
861
862 rtsx_pci_init_cmd(pcr);
863
864 switch (timing) {
865 case MMC_TIMING_UHS_SDR104:
866 case MMC_TIMING_UHS_SDR50:
867 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
868 0x0C | SD_ASYNC_FIFO_NOT_RST,
869 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
870 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
871 CLK_LOW_FREQ, CLK_LOW_FREQ);
872 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
873 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
874 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
875 break;
876
877 case MMC_TIMING_UHS_DDR50:
878 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
879 0x0C | SD_ASYNC_FIFO_NOT_RST,
880 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
881 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
882 CLK_LOW_FREQ, CLK_LOW_FREQ);
883 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
884 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
885 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
886 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
887 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
888 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
889 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
890 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
891 break;
892
893 case MMC_TIMING_MMC_HS:
894 case MMC_TIMING_SD_HS:
895 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
896 0x0C, SD_20_MODE);
897 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
898 CLK_LOW_FREQ, CLK_LOW_FREQ);
899 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
900 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
901 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
902 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
903 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
904 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
905 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
906 break;
907
908 default:
909 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
910 SD_CFG1, 0x0C, SD_20_MODE);
911 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
912 CLK_LOW_FREQ, CLK_LOW_FREQ);
913 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
914 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
915 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
916 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
917 SD_PUSH_POINT_CTL, 0xFF, 0);
918 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
919 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
920 break;
921 }
922
923 err = rtsx_pci_send_cmd(pcr, 100);
924
925 return err;
926 }
927
928 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
929 {
930 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
931 struct rtsx_pcr *pcr = host->pcr;
932
933 if (host->eject)
934 return;
935
936 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
937 return;
938
939 mutex_lock(&pcr->pcr_mutex);
940
941 rtsx_pci_start_run(pcr);
942
943 sd_set_bus_width(host, ios->bus_width);
944 sd_set_power_mode(host, ios->power_mode);
945 sd_set_timing(host, ios->timing);
946
947 host->vpclk = false;
948 host->double_clk = true;
949
950 switch (ios->timing) {
951 case MMC_TIMING_UHS_SDR104:
952 case MMC_TIMING_UHS_SDR50:
953 host->ssc_depth = RTSX_SSC_DEPTH_2M;
954 host->vpclk = true;
955 host->double_clk = false;
956 break;
957 case MMC_TIMING_UHS_DDR50:
958 case MMC_TIMING_UHS_SDR25:
959 host->ssc_depth = RTSX_SSC_DEPTH_1M;
960 break;
961 default:
962 host->ssc_depth = RTSX_SSC_DEPTH_500K;
963 break;
964 }
965
966 host->initial_mode = (ios->clock <= 1000000) ? true : false;
967
968 host->clock = ios->clock;
969 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
970 host->initial_mode, host->double_clk, host->vpclk);
971
972 mutex_unlock(&pcr->pcr_mutex);
973 }
974
975 static int sdmmc_get_ro(struct mmc_host *mmc)
976 {
977 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
978 struct rtsx_pcr *pcr = host->pcr;
979 int ro = 0;
980 u32 val;
981
982 if (host->eject)
983 return -ENOMEDIUM;
984
985 mutex_lock(&pcr->pcr_mutex);
986
987 rtsx_pci_start_run(pcr);
988
989 /* Check SD mechanical write-protect switch */
990 val = rtsx_pci_readl(pcr, RTSX_BIPR);
991 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
992 if (val & SD_WRITE_PROTECT)
993 ro = 1;
994
995 mutex_unlock(&pcr->pcr_mutex);
996
997 return ro;
998 }
999
1000 static int sdmmc_get_cd(struct mmc_host *mmc)
1001 {
1002 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1003 struct rtsx_pcr *pcr = host->pcr;
1004 int cd = 0;
1005 u32 val;
1006
1007 if (host->eject)
1008 return -ENOMEDIUM;
1009
1010 mutex_lock(&pcr->pcr_mutex);
1011
1012 rtsx_pci_start_run(pcr);
1013
1014 /* Check SD card detect */
1015 val = rtsx_pci_card_exist(pcr);
1016 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1017 if (val & SD_EXIST)
1018 cd = 1;
1019
1020 mutex_unlock(&pcr->pcr_mutex);
1021
1022 return cd;
1023 }
1024
1025 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1026 {
1027 struct rtsx_pcr *pcr = host->pcr;
1028 int err;
1029 u8 stat;
1030
1031 /* Reference to Signal Voltage Switch Sequence in SD spec.
1032 * Wait for a period of time so that the card can drive SD_CMD and
1033 * SD_DAT[3:0] to low after sending back CMD11 response.
1034 */
1035 mdelay(1);
1036
1037 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1038 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1039 * abort the voltage switch sequence;
1040 */
1041 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1042 if (err < 0)
1043 return err;
1044
1045 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1046 SD_DAT1_STATUS | SD_DAT0_STATUS))
1047 return -EINVAL;
1048
1049 /* Stop toggle SD clock */
1050 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1051 0xFF, SD_CLK_FORCE_STOP);
1052 if (err < 0)
1053 return err;
1054
1055 return 0;
1056 }
1057
1058 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1059 {
1060 struct rtsx_pcr *pcr = host->pcr;
1061 int err;
1062 u8 stat, mask, val;
1063
1064 /* Wait 1.8V output of voltage regulator in card stable */
1065 msleep(50);
1066
1067 /* Toggle SD clock again */
1068 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1069 if (err < 0)
1070 return err;
1071
1072 /* Wait for a period of time so that the card can drive
1073 * SD_DAT[3:0] to high at 1.8V
1074 */
1075 msleep(20);
1076
1077 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1078 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1079 if (err < 0)
1080 return err;
1081
1082 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1083 SD_DAT1_STATUS | SD_DAT0_STATUS;
1084 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1085 SD_DAT1_STATUS | SD_DAT0_STATUS;
1086 if ((stat & mask) != val) {
1087 dev_dbg(sdmmc_dev(host),
1088 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1089 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1090 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1091 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1092 return -EINVAL;
1093 }
1094
1095 return 0;
1096 }
1097
1098 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1099 {
1100 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1101 struct rtsx_pcr *pcr = host->pcr;
1102 int err = 0;
1103 u8 voltage;
1104
1105 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1106 __func__, ios->signal_voltage);
1107
1108 if (host->eject)
1109 return -ENOMEDIUM;
1110
1111 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1112 if (err)
1113 return err;
1114
1115 mutex_lock(&pcr->pcr_mutex);
1116
1117 rtsx_pci_start_run(pcr);
1118
1119 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1120 voltage = OUTPUT_3V3;
1121 else
1122 voltage = OUTPUT_1V8;
1123
1124 if (voltage == OUTPUT_1V8) {
1125 err = sd_wait_voltage_stable_1(host);
1126 if (err < 0)
1127 goto out;
1128 }
1129
1130 err = rtsx_pci_switch_output_voltage(pcr, voltage);
1131 if (err < 0)
1132 goto out;
1133
1134 if (voltage == OUTPUT_1V8) {
1135 err = sd_wait_voltage_stable_2(host);
1136 if (err < 0)
1137 goto out;
1138 }
1139
1140 out:
1141 /* Stop toggle SD clock in idle */
1142 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1143 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1144
1145 mutex_unlock(&pcr->pcr_mutex);
1146
1147 return err;
1148 }
1149
1150 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1151 {
1152 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1153 struct rtsx_pcr *pcr = host->pcr;
1154 int err = 0;
1155
1156 if (host->eject)
1157 return -ENOMEDIUM;
1158
1159 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1160 if (err)
1161 return err;
1162
1163 mutex_lock(&pcr->pcr_mutex);
1164
1165 rtsx_pci_start_run(pcr);
1166
1167 /* Set initial TX phase */
1168 switch (mmc->ios.timing) {
1169 case MMC_TIMING_UHS_SDR104:
1170 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1171 break;
1172
1173 case MMC_TIMING_UHS_SDR50:
1174 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1175 break;
1176
1177 case MMC_TIMING_UHS_DDR50:
1178 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1179 break;
1180
1181 default:
1182 err = 0;
1183 }
1184
1185 if (err)
1186 goto out;
1187
1188 /* Tuning RX phase */
1189 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1190 (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1191 err = sd_tuning_rx(host, opcode);
1192 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1193 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1194
1195 out:
1196 mutex_unlock(&pcr->pcr_mutex);
1197
1198 return err;
1199 }
1200
1201 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1202 .request = sdmmc_request,
1203 .set_ios = sdmmc_set_ios,
1204 .get_ro = sdmmc_get_ro,
1205 .get_cd = sdmmc_get_cd,
1206 .start_signal_voltage_switch = sdmmc_switch_voltage,
1207 .execute_tuning = sdmmc_execute_tuning,
1208 };
1209
1210 #ifdef CONFIG_PM
1211 static int rtsx_pci_sdmmc_suspend(struct platform_device *pdev,
1212 pm_message_t state)
1213 {
1214 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1215 struct mmc_host *mmc = host->mmc;
1216 int err;
1217
1218 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1219
1220 err = mmc_suspend_host(mmc);
1221 if (err)
1222 return err;
1223
1224 return 0;
1225 }
1226
1227 static int rtsx_pci_sdmmc_resume(struct platform_device *pdev)
1228 {
1229 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1230 struct mmc_host *mmc = host->mmc;
1231
1232 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1233
1234 return mmc_resume_host(mmc);
1235 }
1236 #else /* CONFIG_PM */
1237 #define rtsx_pci_sdmmc_suspend NULL
1238 #define rtsx_pci_sdmmc_resume NULL
1239 #endif /* CONFIG_PM */
1240
1241 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1242 {
1243 struct mmc_host *mmc = host->mmc;
1244 struct rtsx_pcr *pcr = host->pcr;
1245
1246 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1247
1248 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1249 mmc->caps |= MMC_CAP_UHS_SDR50;
1250 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1251 mmc->caps |= MMC_CAP_UHS_SDR104;
1252 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1253 mmc->caps |= MMC_CAP_UHS_DDR50;
1254 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1255 mmc->caps |= MMC_CAP_1_8V_DDR;
1256 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1257 mmc->caps |= MMC_CAP_8_BIT_DATA;
1258 }
1259
1260 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1261 {
1262 struct mmc_host *mmc = host->mmc;
1263
1264 mmc->f_min = 250000;
1265 mmc->f_max = 208000000;
1266 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1267 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1268 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1269 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1270 mmc->max_current_330 = 400;
1271 mmc->max_current_180 = 800;
1272 mmc->ops = &realtek_pci_sdmmc_ops;
1273
1274 init_extra_caps(host);
1275
1276 mmc->max_segs = 256;
1277 mmc->max_seg_size = 65536;
1278 mmc->max_blk_size = 512;
1279 mmc->max_blk_count = 65535;
1280 mmc->max_req_size = 524288;
1281 }
1282
1283 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1284 {
1285 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1286
1287 mmc_detect_change(host->mmc, 0);
1288 }
1289
1290 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1291 {
1292 struct mmc_host *mmc;
1293 struct realtek_pci_sdmmc *host;
1294 struct rtsx_pcr *pcr;
1295 struct pcr_handle *handle = pdev->dev.platform_data;
1296
1297 if (!handle)
1298 return -ENXIO;
1299
1300 pcr = handle->pcr;
1301 if (!pcr)
1302 return -ENXIO;
1303
1304 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1305
1306 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1307 if (!mmc)
1308 return -ENOMEM;
1309
1310 host = mmc_priv(mmc);
1311 host->pcr = pcr;
1312 host->mmc = mmc;
1313 host->pdev = pdev;
1314 host->power_state = SDMMC_POWER_OFF;
1315 platform_set_drvdata(pdev, host);
1316 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1317 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1318
1319 mutex_init(&host->host_mutex);
1320
1321 realtek_init_host(host);
1322
1323 mmc_add_host(mmc);
1324
1325 return 0;
1326 }
1327
1328 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1329 {
1330 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1331 struct rtsx_pcr *pcr;
1332 struct mmc_host *mmc;
1333
1334 if (!host)
1335 return 0;
1336
1337 pcr = host->pcr;
1338 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1339 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1340 mmc = host->mmc;
1341 host->eject = true;
1342
1343 mutex_lock(&host->host_mutex);
1344 if (host->mrq) {
1345 dev_dbg(&(pdev->dev),
1346 "%s: Controller removed during transfer\n",
1347 mmc_hostname(mmc));
1348
1349 rtsx_pci_complete_unfinished_transfer(pcr);
1350
1351 host->mrq->cmd->error = -ENOMEDIUM;
1352 if (host->mrq->stop)
1353 host->mrq->stop->error = -ENOMEDIUM;
1354 mmc_request_done(mmc, host->mrq);
1355 }
1356 mutex_unlock(&host->host_mutex);
1357
1358 mmc_remove_host(mmc);
1359 mmc_free_host(mmc);
1360
1361 dev_dbg(&(pdev->dev),
1362 ": Realtek PCI-E SDMMC controller has been removed\n");
1363
1364 return 0;
1365 }
1366
1367 static struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1368 {
1369 .name = DRV_NAME_RTSX_PCI_SDMMC,
1370 }, {
1371 /* sentinel */
1372 }
1373 };
1374 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1375
1376 static struct platform_driver rtsx_pci_sdmmc_driver = {
1377 .probe = rtsx_pci_sdmmc_drv_probe,
1378 .remove = rtsx_pci_sdmmc_drv_remove,
1379 .id_table = rtsx_pci_sdmmc_ids,
1380 .suspend = rtsx_pci_sdmmc_suspend,
1381 .resume = rtsx_pci_sdmmc_resume,
1382 .driver = {
1383 .owner = THIS_MODULE,
1384 .name = DRV_NAME_RTSX_PCI_SDMMC,
1385 },
1386 };
1387 module_platform_driver(rtsx_pci_sdmmc_driver);
1388
1389 MODULE_LICENSE("GPL");
1390 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1391 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
Linux with added FPC-III support